1 Introduction

Nowadays, with the rapid prospering of the portable electronics market, low power and high stability have become two main design features of a system-on-chip (SoC) [14, 26]. Lowering the power consumption in static random access memories (SRAMs) is an important task, which can reduce the total power of the SoC. This is because SRAMs are the main contributor to the SoC’s area and consequently its power [26]. There are many approaches to achieve low power and/or high stability in the SRAM cells such as minimizing the supply voltage (VDD) to reduce total power, utilizing multi-threshold complementary metal–oxide–semiconductor (CMOS) process to decrease leakage power, and using multiple SRAM sub-macros rather than one single SRAM macro to increase stability and to minimize dynamic power [14]. Among them, VDD scaling is the well-known and efficient approach to access the low-power operation in the SRAM cell due to the existence of a linear and a quadratic relation between pairs of VDD and leakage current and VDD and dynamic power, respectively [3]. Nevertheless, VDD reduction poses many problems as follows. The delay increases with VDD reduction, and therefore, energy consumption increases [24]. The voltage difference between VDD and threshold voltage (Vth) reduces with downscaling VDD, which leads to the grave degradation of static noise margin (SNM) and makes the circuit unreliable [23]. In the severe low-VDD operation, the sensitivity of the SRAM cell’s parameters to process variations such as line edge roughness (LER) and random dopant fluctuation (RDF) increases, which may lead to Vth mismatch between adjacent transistors in the cell [20]. Furthermore, increased manufacturing process, voltage, and temperature (PVT) variations at severe low-VDD further degrade the SRAM cell’s stability [25]. The conventional 6T SRAM cell suffers from poor SNM induced by read current disturbance and therefore cannot operate at severe low-VDD [13]. Furthermore, it offers undesirable read SNM (RSNM) and write SNM (WSNM), as a measure of read stability and writability, respectively, at low-VDD, which increase the probability of operational failure [27]. These issues are further worsened by contradicting requirements for RSNM and WSNM [13, 24].

Therefore, it is necessary to design a highly stable and robust SRAM cell that can overcome the aforementioned challenges and work well at low-VDD to gain the advantages of the VDD scaling. Various configurations of SRAM cells have been proposed in the literature over the years to achieve better performance than conventional design. SRAM cells proposed in [17, 22, 27] utilize the read decoupling technique to isolate the data storing nodes from the reading access path during the read operation to overcome conflicting read/write requirements induced by the conventional 6T SRAM cell. This technique improves the cell’s RSNM to be as high as hold SNM (HSNM). The conventional 8T SRAM cell presented in [15] improves the RSNM by application of two extra read-access transistors, one read bitline, and one read wordline to form the isolated read path. This improvement is achieved at the cost of leakage in the read path, which is further pronounced with technology scaling. To reduce this leakage and also to increase the RSNM, a modified version of the isolated read path has been individually used in the design of SRAM cell proposed in [17]. This reduction is attributed to data-independent read port leakage. Due to offering better voltage transfer characteristics (VTCs) as a direct consequence of the feedback mechanism, the normal inverter has been replaced by the Schmitt-trigger (ST)-based inverter to form the cell core of the SRAM cells designed in [20, 21] to improve both RSNM and WSNM simultaneously. Moreover, these designs are tolerant to PVT variations and modulate the Vth of the latch transistors to compensate for the variations. However, the read-disturbance problem is still sensed in these SRAM cells.

Various SRAM cells have been presented in the literature [2, 6, 22, 27] to achieve the low-power operation. This is due to the application of single bitline to reduce the switching activity factor of the bitline (\({\alpha }_{bitline}\)) to less than half during the read/write operation. Other SRAM cells proposed in [7, 9] employ separate bitlines to perform read and write operations. In these designs, \({\alpha }_{\mathrm{bitline}}\) also reduces to less than 0.5; consequently, power consumption reduces. However, single-ended SRAM cells suffer highly from writing ‘1’ ability degradation without any write-assist techniques, leading to a writing ‘1’ failure [27]. To solve this problem, a feedback-cutting NMOS transistor or transmission gate is inserted inside the cell core of the SRAM cells proposed in [2, 10, 27] to remove the feedback path of the cross-coupled inverters pair during the write operation, resulting in WSNM improvement. The single-bitline 11T SRAM cell projected in [22] employs power-gated transistors to cut the power rails off from the data storing node Q or QB during the write operation to improve the WSNM. Furthermore, the connection of several access transistors to the same bitline increases overall bitline capacitance, and therefore, the 11T cell [22] shows longer read delay and higher dynamic power. To mitigate the read disturbance, a one-sided ST-based 9T SRAM cell was proposed in [16]. In this cell, the power rails are cut from the internal storage node Q during the write operation to increase the WSNM. Another technique to eliminate the writing ‘1’ issue in the single-ended SRAM cells is to use data-aware power cutoff (DAPC) write-assist mechanism. The 11T [3] SRAM cell uses this technique to improve the WSNM but suffers from high dynamic power due to increased bitline capacitance.

Therefore, this paper proposes a highly stable and robust 10T SRAM cell appropriate for low-power portable applications such as mobile phones and medical instruments like pacemaker to solve the above-mentioned challenges. The proposed 10T SRAM cell will be called New10T, hereafter. The main characteristics of the proposed SRAM cell are as follows:

  1. 1.

    A normal inverter is combined with ST inverter to form the cell core of the proposed cell, resulting in HSNM enhancement.

  2. 2.

    Furthermore, the application of the read decoupling technique improves the RSNM.

  3. 3.

    The writing ‘1’ issue is eliminated by the New10T SRAM cell through inserting a feedback-cutting NMOS transistor inside the cell core, therefore resulting in WSNM enhancement.

  4. 4.

    The dynamic power consumption is reduced by the proposed design due to the use of single-ended structure.

  5. 5.

    The presence of stacked transistors in the cell core along with a double-length pull-up transistor in the ST inverter minimizes the leakage power dissipated by the proposed cell.

The rest of this paper is organized as follows. Section 2 introduces the New10T SRAM cell. The simulation results and discussion are presented in Sect. 3. Finally, Sect. 4 concludes this paper.

2 The New10T Sram Cell

The schematic of the New10T SRAM cell is shown in Fig. 1. The normal inverter with a stacked NMOS transistor (MNL1, MNL2, and MPL), gated by PQ node, and the ST-based inverter (MNR1, MNR2, MNR3, and MPR), gated by QB node, make the cell core of the proposed design to maintain the cell content. The write-access transistor WAT, driven by the write wordline (WWL), establishes a write path to write a desired data into the cell by the column-based write bitline (WBL). Due to single-ended writing structure, a feedback-cutting transistor FCT, controlled by the columnar selection line (CSL) control signal, is inserted inside the cell core of the proposed design. This transistor is at OFF state during the write operation to eliminate the feedback path of the cell core to ensure that a successful write ‘1’ operation is performed. Furthermore, in the ST-based inverter, the source of the feedback transistor MNR3 is connected to the CSL. As the CSL is grounded during the write operation, the feedback action from the feedback transistor MNR3 in the ST-based inverter is removed, which in turn helps to increase the writing speed. The columnar read bitline (RBL) is accessed to the cell by the read-access transistor (RAT), gated by the read wordline (RWL), to perform a read operation. The read path does not include the true internal data storing nodes Q and QB. Moreover, during the read operation, an increase in voltage of the PQB and QB nodes has no harmful effects on the Q node because the voltage trip level of the ST inverter is higher than the normal inverter, and thus, the QB node never reaches it. Therefore, the read-disturbance issue is removed by the proposed design. Table 1 gives the status of the control signals used in the proposed design for the hold, read, and write operations.

Fig. 1
figure 1

The schematic of the New10T SRAM cell annotated with channel width-to-channel length ratio (W/L) in nm

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Table 1 Control signals for the New10T SRAM cell
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3 Cell Performance and Comparison

In this section, various performance parameters of the New10T SRAM cell are extracted using HSPICE and 16-nm CMOS technology node [28]. To estimate the relative strength of the proposed cell, it is compared with existing SRAM cells such as conventional 6T [19], transmission-gate 9T (TG9T) [27], differential writing 10T (10T-P1) [17], and single-bitline 11T (SB11T) [22], as shown in Fig. 2, in terms of major design metrics. The size of each transistor is annotated in Fig. 2.

Fig. 2
figure 2

The schematic of the considered SRAM cells with W/L ratio in nm. a 6T [19], b TG9T [27], c 10T-P1 [17] and d SB11T [22]

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In advanced technology, the impact of PVT variations becomes a series issue. Therefore, we analyzed their impact on the SRAM cells’ performance using Monte Carlo (MC) simulations with 10,000 samples. For this reason, we take into consideration the changes in the various process and device parameters including channel length (L), channel width (W), channel doping concentration (NDEP), oxide thickness (Tox), threshold voltage (Vth), mobility (µ0), and supply voltage (VDD). All the above-mentioned parameters are assumed to have an independent normal Gaussian distribution with a 3σ variation of 10% [2].

A comparison of different performance metrics for under-test SRAM cells is presented in the following subsections.

3.1 Read-Access Time

As shown in Fig. 3a, b, to read the stored data in the cell, the RBL is precharged to VDD. The WBL and WWL are kept at VDD and GND, respectively. Therefore, the write-access transistor WAT is turned off as the WWL is grounded, to remove the write path. The CSL is set to VDD to establish the feedback path of the cell core and to activate the feedback mechanism of the ST-based inverter offered by the MNR3 transistor. The RWL is raised high to turn on the read-access transistor (RAT). Depending upon the content of the data storing node Q or QB, the RBL either discharges to GND through the pass transistors comprising RAT and MNL1 or remains at its initial high precharged value (VDD).

Fig. 3
figure 3

a read ‘0’ operation b transient response during read ‘0’ operation c VTC of the normal- and ST-based inverters and d read ‘1’ operation of the New10T SRAM cell

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To show the read ‘0’ operation of the New10T SRAM cell (Fig. 3a), let us consider the case in which the storage node Q/QB is storing ‘1’/‘0’ logic value. The transistors MNL1 and MNL2 of the normal inverter are turned on as storage node Q stores ‘1’. Then, a discharging path formed by RAT and MNL1 is created for the RBL. As the RBL is discharging to the ground through this path, the voltage level of the PQB node is raised from zero to the positive value, which is almost equal to 0.15 V based on the transient response of the proposed design during the read ‘0’ operation when subjected to PVT variations (worst-case sample), as shown in Fig. 3b. An increase in the PQB node voltage leads to an increase in the QB node voltage, as MNL2 is at ON state. However, the MNL2 is an n-type MOSFET and cannot pass the strong ‘1’ logic value. On the other hand, the voltage level of the QB node never reaches the trip voltage level of the ST-based inverter (see Fig. 3c, blue curve) to flip the Q node state. Therefore, the RBL discharges to the ground without flipping the content of the cell, resulting in the read-disturbance removal. This issue increases the cell’s RSNM to be equal to HSNM. However, as shown in Fig. 3c, when the output voltage of ST inverter is high (Vout = VDD), NF is turned on, and therefore, charges Vx node. This issue makes it hard to change the high value of Vout. Therefore, we have doubled the channel length of the PUR (i.e., \({L}_{PUR}=2\times {L}_{min}=\) 32 nm) in the ST inverter to equalize ‘0’ and ‘1’ margins. Its voltage transfer characteristics (VTC) are shown in Fig. 3c as the red curve.

Now, assume that the data storing node Q/QB is initially storing ‘0’/‘1’ logic value. The pull-down network of the normal inverter is at OFF state because data stored at Q node is ‘0’. Therefore, the RBL remains at its initial high precharged value (VDD), which shows that the Q node is storing ‘0’ (Fig. 3d).

The read delay (TRA) is a measure of the speed of the SRAM cell during the read operation. The definition of the TRA for single-ended and differential SRAM cells is different. For differential reading structure, the TRA is calculated as the time when the voltage difference of two bitlines becomes 50 mV right after wordline activation [11, 12]. For single-ended reading structure, on the other hand, the TRA is defined as the time when read bitline is discharged from VDD to its half immediately after assertion of wordline [18]. Figure 4 shows the comparison of the TRA of the investigated SRAM cells at different VDD values. SRAM cells including TG9T, 10T-P1, SB11T, and New10T utilize single-ended reading structure, and therefore, their TRA is higher than that of 6T SRAM cell, which is using differential reading structure. Due to the connection of several transistors to the same bitline, which increases overall bitline capacitance, the SB11T SRAM cell shows the highest TRA among all the SRAM cells. The read path of 10T-P1 SRAM cell constitutes three NMOS access transistors, resulting in TRA increase. Due to the same read path, formed by two NMOS access transistors, SRAM cells such as TG9T and New10T show equal TRA and lower than those of aforementioned SRAM cells. The New10T SRAM cell exhibits 2.76X/1.54X lower and 3.92X higher TRA compared with SB11T/10T-P1 and 6T SRAM cells, respectively, at VDD = 0.7 V.

Fig. 4
figure 4

TRA of the tested SRAM cells versus VDD

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3.2 Write-Access Time

The write operation in the New10T SRAM cell performs as follows. As shown in Fig. 5a, b, the CSL is set to GND to turn off the FCT. This in turn removes the feedback path of the cross-coupled normal- and ST-based inverters pair to eliminate writing ‘1’ issue in the proposed single-ended design and to facilitate the write ‘1’ operation. Furthermore, by pulling down the CSL, there will be no feedback action offered by MNR3 in the ST-based inverter, helping to increase writing speed. The RBL is kept at VDD and RWL is forced to GND to turn off the RAT to remove the read path. The WWL is raised high to turn on the WAT to create the writing path. Depending upon whether ‘1’/‘0’ or ‘0’/‘1’ is to be written to Q/QB, the WBL is either maintained at VDD or GND.

Fig. 5
figure 5

a write ‘1’ operation and b write ‘0’ operation of the New10T SRAM cell along with their transient response

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Let us consider the case in which the ‘1’/‘0’ logic value is to be written into the ‘0’/‘1’ storing node Q/QB. Thus, a ‘1’ is applied to the WBL. The ‘1’ logic value is transferred to PQ node through the WAT. By raising the voltage level of the PQ node, the MNL1 and MNL2 are turned on, which invert the content of the QB node from ‘1’ to ‘0’ logic value. By pulling down the QB node, the MPR is turned on, which charges the Q node. Finally, a write ‘1’ operation is successfully performed, as shown in Fig. 5a. To write ‘0’ into the ‘1’ storing node Q as shown in Fig. 5b, a complementary process takes place where WBL is set to GND.

The write delay (TWA) estimates the swiftness of the SRAM cell to flip the data stored in its internal storing nodes during the write operation. Since the proposed design is a single-ended cell and writing ‘1’ process is difficult than writing ‘0’ one, we compared TWA for writing ‘1’ into the ‘0’ storing node Q of all the compared SRAM cells at different VDD values, as shown in Fig. 6. The TWA for writing ‘1’ is measured as the time required by Q node, which initially stores ‘0,’ to reach 90% of VDD right after asserting wordline [3, 18]. Due to the use of the single-ended writing structure, SRAM cells such as TG9T, SB11T, and New10T show higher TWA than those of 6T and 10T-P1 SRAM cells with differential writing structure. The conventional 6T and 10T-P1 SRAM cells show the same and least TWA among all the SRAM cells due to having a simple differential writing structure along with an NMOS write-access transistor in write paths. The SB11T SRAM cell uses a TG in its write path, which passes both strong ‘1’ and ‘0’ logic values, showing lower TWA than that of the TG9T and New10T SRAM cells. The feedback-cutting transistor used in the TG9T and New10T SRAM cells increases the TWA. This is due to the formation of two cascaded inverters in which one of them is followed by another one. These SRAM cells show the highest-TWA among the compared SRAM cells. The New10T SRAM cell exhibits 2.37X higher TWA compared with the best SRAM cell, that is conventional 6T.

Fig. 6
figure 6

TWA of the tested SRAM cells versus VDD

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3.3 Hold Static Noise Margin

In the hold mode of the New10T SRAM cell, the WWL/RWL is forced to ground to disable the write-/read-access transistor WAT/RAT. This removes the reading and writing paths. Moreover, the CSL is set to VDD to establish the feedback path of the cell core and the feedback mechanism of the ST-based inverter offered by MNR3. Both WBL and RBL are kept at high. Therefore, the cell core is fully isolated from the read/write bitline; consequently, the cell state is maintained reliably by the cell core, as shown in Fig. 7.

Fig. 7
figure 7

Hold operation of the New10T SRAM cell

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The hold stability is gauged by hold static noise margin (HSNM). The HSNM is defined as the maximum DC noise voltage at each storage node that can be tolerated without altering the status of stored data during the hold operation [18]. Figure 8a, b shows the HSNM of the various SRAM cells at VDD = 0.7 V and versus VDD, respectively. It is graphically measured as the side length of the biggest square that can be embedded inside the smallest wing of the butterfly curves during the hold operation [1]. Combining the normal inverter with the ST inverter to form the cell core of the New10T SRAM cell enhances the HSNM. SRAM cells including 6T, TG9T, 10T-P1, and SB11T use normal cross-coupled inverters pair in their cell core and, therefore, show the lower HSNM compared with the proposed design. The New10T SRAM cell offers 1.26X higher HSNM compared with the above-mentioned SRAM cell at VDD = 0.7 V.

Fig. 8
figure 8

HSNM of the various SRAM cells a at VDD = 0.7 V and b versus VDD

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3.4 Read Static Noise Margin

The read stability is evaluated by read static noise margin (RSNM). The RSNM is delineated as the maximum DC noise voltage at each storage node that can be sustained without altering the status of stored data during the read operation [8, 18]. Figure 9a shows the RSNM of the various SRAM cells at VDD = 0.7 V, and Fig. 9b plots the RSNM of those SRAM cells versus VDD. The RSNM is graphically obtained as the length of a side of the largest square that can be inserted inside the smallest wing of the butterfly curves during the read operation [1, 2]. The conventional 6T SRAM cell suffers from the read disturbance; hence, its RSNM is lower than HSNM. Other SRAM cells employ read decoupling technique in which internal data storing nodes are isolated from bitlines during the read operation, resulting in RSNM improvement. In these SRAM cells, the RSNM is almost equal to HSNM. The cell core of the proposed design constitutes a strong cross-coupled structure of the normal- and ST-based inverters. This along with the separated read path, which does not include the true storage nodes Q and QB, eliminates the read-disturbance issue; consequently, the RSNM improves. The New10T SRAM cell offers 4.65X/1.26X higher RSNM compared to the conventional 6T/TG9T SRAM cell at VDD = 0.7 V.

Fig. 9
figure 9

RSNM of the various SRAM cells a at VDD = 0.7 V and b versus VDD

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3.5 Writability Analysis

The writability of an SRAM cell is characterized by write static noise margin (WSNM). The WSNM is defined as the ability of an SRAM cell to pull-down (up) a ‘1’ (‘0’) storing node to a voltage lower (higher) than the switching threshold (Vth) of the other inverter ‘0’ (‘1’) storing node, resulting in successful flipping the state of the cell [2]. To find the WSNM value, first, the read VTC of an SRAM cell, which is obtained in the previous section, should be combined with the write VTC of that cell, and then, the side length of the smallest square that can be inscribed between and lower-half of these two VTCs provides the WSNM [5]. Figures 10 and 11a show WSNM of the various SRAM cells at VDD = 0.7 V and different VDD values, respectively. SRAM cells such as TG9T, SB11T, and New10T use a single-ended writing structure. In these SRAM cells, writing ‘1’ is difficult, and hence, a write-assist technique is required. The SB11T and TG9T/New10T SRAM cells use power-gated and feedback-cutting write-assist techniques, respectively, to eliminate the writing ‘1’ issue. With the presence of two series-connected NMOS access transistors in its write path compared to SB11T SRAM cell, the TG9T SRAM cell shows considerably lower (1.05X) WSNM. The New10T SRAM cell shows the highest WSNM (1.65X higher than 6T cell) among all the tested SRAM cells at all supply voltage values considered for comparison. This is due to the use of the write-assist mechanism along with a strong cross-coupled structure of the normal- and ST-based inverters.

Fig. 10
figure 10

WSNM of the various SRAM cells at VDD = 0.7 V. a Differential writing bitcells and b single-ended writing bitcells

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Fig. 11
figure 11

a WSNM and b WM of the various SRAM cells versus VDD

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Another metric to quantify the write-ability of an SRAM cell is the write margin (WM). Recent studies have shown that the WM technique is more appropriate than the traditional butterfly static noise margin to estimate the write-ability of an SRAM cell [2, 9]. To measure the WM, first, the desired data are applied on bitlines and then wordline (WL) is swept from zero to the power supply voltage (VDD). The WM is defined as the voltage difference between VDD and WL while flipping the internal storage nodes Q and QB [2]. Figure 11b shows the WM of the studied SRAM cells at different VDD values. Due to the same reasons, the New10T SRAM cell shows the highest WM among all the SRAM cells. The WM of the New10T SRAM cell at VDD = 0.7 V is 1.56X higher than that of the conventional 6T SRAM cell.

3.6 Dynamic Power Consumption

Dynamic power (PDyn) is defined as power consumed by an SRAM cell when it is accessed [27]. The PDyn has two main components including dynamic read power and dynamic write power. The dynamic write power consumption is the large percentage of the total dynamic power consumption due to fully discharging the bitlines capacitance during the write operation [2, 3]. Hence, we compared the dynamic power consumption of the different SRAM cells during the write operation, as shown in Fig. 12. Due to the existence of a direct relation between the switching activity factor of bitlines (\({\alpha }_{bitline}\)) and PDyn, SRAM cells with differential writing structure consume higher PDyn compared with single-ended writing bitcells. The SB11T SRAM cell shows the highest PDyn among all the tested SRAM cells due to the connection of several transistors to the same bitline, which increases overall bitline capacitance. The New10T SRAM cell offers the lowest PDyn due to its single-ended writing structure and its highest write delay. The PDyn of the proposed design is 1.64X lower than that of the conventional 6T SRAM cell at VDD = 0.7 V.

Fig. 12
figure 12

Dynamic power of the various SRAM cells versus VDD

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3.7 Leakage Power Dissipation

As technology nodes scale down to a deep submicron regime, the subthreshold leakage in embedded memory has turned into a crucial concern [12]. The leakage power (PLeak) of an SRAM cell is the main contributor to its total power in the advanced technology because a major part of the cache remains in the hold mode most of the time [2, 3]. Figure 13 shows the comparison of PLeak of the different SRAM cells at different VDD values. The SB11T and 10T-P1 SRAM cells exhibit higher PLeak than that of the conventional 6T SRAM cell due to higher bitline capacitance and higher count of bitlines, respectively. The New10T SRAM cell shows the least PLeak (1.54X lower than 6T cell). This improvement in PLeak of the New10T SRAM cell is due to the presence of stacking of transistors during both hold ‘0’ and hold ‘1’ state and its single-ended structure. The double-length pull-up transistor in the ST-based inverter further reduces PLeak.

Fig. 13
figure 13

Leakage power of the various SRAM cells versus VDD

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3.8 Monte Carlo (MC) Simulation of PVT variations

In advanced technologies, the impact of PVT variations on the various performance metrics of an SRAM cell becomes significant, especially in low-VDD domain. Therefore, it is necessary to design an SRAM cell that can overcome severe PVT variations. In this section, we perform Monte Carlo (MC) simulations with 10,000 samples to take into account the impact of severe PVT variations on the static noise margin (SNM) of the studied SRAM cells during the hold, read, and write operations. Figure 14 shows the Gaussian distribution plots of HSNM, RSNM, and WM for all the studied SRAM cells. In this comparison, the WM is used because it is more appropriate than the WSNM to show the ability of an SRAM cell during the write operation [4]. In the New10T SRAM cell, the cell core is formed by combining normal- and ST-based inverters, resulting in PVT variation mitigation. The proposed design shows 1.71X lower variability in HSNM compared with the conventional 6T SRAM cell.

Fig. 14
figure 14

Distribution plots of a HSNM, b RSNM, and c WM for different SRAM cells at VDD = 0.7 V

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It is observed from Fig. 14b, which shows the Gaussian distribution plots of RSNM, that the conventional 6T SRAM cell suffers highly from the read disturbance, showing higher RSNM variability than those of other remaining SRAM cells in which data storing nodes are decoupled from bitline(s) during the read operation. The New10T SRAM cell exhibits 4.40X lower variability in RSNM compared with the conventional 6T SRAM cell due to the same reasons for HSNM.

The Gaussian distribution plots of WM for different bitcells are shown in Fig. 14c. Due to the use of ST-based inverters and high-WM, the New10T SRAM cell overcomes PVT variations, resulting in WM variability reduction. SRAM cells including TG9T and SB11T utilize normal inverter and write-assist technique and therefore show lower variability in WM. Based on the obtained results, the New10T SRAM cell has 1.79X lesser variability in WM than that of the conventional 6T SRAM cell.

3.9 Layout Area and Comprehensive Metric

Figure 15 shows the layout of the New10T SRAM cell. The conventional 6T SRAM cell has a compact and simple structure with a minimum count of transistors, and therefore, it occupies 0.81X lesser area compared to New10T SRAM cell. The thirteenth row of Table 2 reports the SRAM cells’ area normalized to that of conventional 6T SRAM cell. It can be observed that the proposed design is the second-best SRAM cell based on layout area.

Fig. 15
figure 15

Layout of the New10T SRAM cell

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Table 2 Design metrics comparison of the various SRAM cells at VDD = 0.7 V
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Due to the existence of a trade-off among various design metrics of an SRAM cell, a comprehensive metric is required to estimate the overall quality of that SRAM cell [12]. The proposed figure of merit (FOM) defined as Eq. (1) and reported in the last row of Table 2 implies that the proposed cell is the best design among all the studied SRAM cells. Therefore, the New10T SRAM cell can be a good choice for low-power portable applications.

$$ FOM = \frac{(HSNM \times RSNM \times WM}{{\left( {\frac{\sigma }{\mu }HSNM \times \frac{\sigma }{\mu }RSNM \times \frac{\sigma }{\mu }WM} \right)}} \times \frac{1}{{\left( {T_{RA} \times T_{WA} \times P_{Dyn} \times P_{Leak} \times Area} \right)}}. $$
(1)

4 Conclusion

In this paper, a highly stable and robust 10T SRAM cell is proposed, which is appropriate for low-power portable applications. The cell core of the New10T is formed by a normal inverter with a stacked transistor and a Schmitt-trigger (ST)-based inverter. Separate bitlines are used to perform read and write operations. The read disturbance is eliminated by the proposed design due to the use of an isolated read path along with a strong cell core. Furthermore, the writing ‘1’ issue in the proposed single-ended design is removed with the aid of a feedback-cutting write-assist technique. Based on the obtained results given in Table 2 at VDD = 0.7 V, the New10T design offers the highest HSNM/RSNM/WSNM (WM). Due to the single-ended reading/writing structure, the New10T SRAM cell shows 3.92X/2.37X higher read/write delay compared with the 6T SRAM cell. The dynamic/leakage power of the proposed cell is 1.64X/1.54X lower than that of 6T SRAM cell. This improvement is achieved due to its single-ended nature and the presence of stacked transistors in its cell core. Though the proposed cell consumes a 1.24X higher area compared with the 6T SRAM cell, it shows the highest proposed FOM among all the SRAM cells, making it a good choice for low-power portable applications.