Keywords

1 Introduction

Wireless sensor network production has revolutionized our lifestyles. Sensor networks may be used for different purposes, such as military surveillance, monitoring of the environment, medical diagnosis, etc. A wireless sensor network used for medical diagnosis is defined as the body area network (Istepanian et al. 2004; Gyselinckxet al. 2005). To provide real-time input, body region networks have to do continuous health monitoring. Continuous monitoring of physiological parameters is enabled by body area networks. Compared to the physiological parameters obtained from short-term monitoring, for example, hospital stays, this continuous monitoring for long periods in the natural environment produces better results (Park et al. 2003). Miniature wireless sensor nodes with an extended operating life are needed to further expand the capabilities of the body area network. For the realization of ubiquitous sensing, the sensor nodes must have a very small form factor (Gyselinckx et al. 2005) without interfering with the object being monitored. This miniaturization results in a decrease in the energy capacity of the sensor since the battery size used to store the energy is limited. The intrusive procedure necessity (Malan et al. 2004) complicates the replacement of the embedded medical wireless sensor nodes by the battery [1, 2].

1.1 Power Reduction Techniques

Power reduction techniques are applied over circuits to reduce the power consumption of circuits with no effect on performance, speed, and other parameters.

1.1.1 Sleep Transistor Technique

The state-destructive technique disrupts both PMOS and NMOS transistors from sleep transistors to supply voltage or ground. These methods are called VDD and gated-GND. These are technological varieties. When the logic circuits are in standby mode, the sleep transistor is disabled. By uninflecting sleep transistor operation from the logical networks, the technique of sleep semiconductor significantly reduces sleep power as shown in Fig. 1a [3].

Fig. 1
figure 1

a Sleep transistor technique; b forced stack technique; c dual sleep technique

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1.1.2 Forced Stack Technique

Figure 1b demonstrates a forced stack technique. This second technique decreases the power by stacking transistors. When two or more transistors are uniformly switched OFF, the effect of stacking the semiconductor device reduces the sub-threshold leakage current [4].

1.1.3 Dual Sleep Technique

Both types of transistors are used in this technique: two PMOS (PM0 and PM1) and two NMOS (NM0 and NM1). Both PMOS and NMOS transistors are used in the header and footer. One transistor is ON in active mode, and another transistor is switched ON in OFF state mode. PMOS and NMOS are both used in standby mode to reduce power, as shown in Fig. 1c [5].

These circuits became known as high-density circuits because of their numerous transistors used and also because of the high leakage rate concerning technological developments. The input power supply was then reduced by attempting to reduce the energy consumption rate [6,7,8]. As compared with SRAM memories, they have higher percentages of portable devices with static memory because more power is spent on data stability in DRAM memory. In both static and dynamic memories, the access time is approximately the same [9,10,11].

2 Single-Bit Memory Architecture

WDC, SRAMC, and CLSA as shown in Fig. 2 [12, 13] are the single-bit cache memory architectural blocks. The description is divided into three different parts: (a) the WDC with two input pins (word enable (WE) and Bit) and two output pins (BL and BLBAR), (b) the SRAMC, which is attached to the WDC via bit lines (i.e., BL and BLBAR), and an input pin [word line (WL)] and two output pins (V1 and V2) and connected through bit lines having capacitance and resistance as a connector between them, (c) CLSA which has 4 input pins (Ysel, BLPCH, SAPCH, and SAEN) and two output pins (V3 and V4).

Fig. 2
figure 2

Schematic of single-bit cache memory architecture

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3 Write Driver Circuit

Figure 3 shows the write driver schematic developed in this work. The bit line is discharged from its high pre-load level to below the SRAMC writing margin by the WDC. The voltage required to enter the desired value in the bit line is determined by the WDC. When “WE = 1” (write enable pulled high), data from the data input pin are entered in bit lines and transferred to the corresponding memory cell through the access transistors.

Fig. 3
figure 3

Write driver circuit schematic

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To obtain the glitch-free bit lines, the buffer circuit has been positioned before the output of the WDC. It has to enter a certain value in the bit cell up to the WDC. The circuit has the purpose of charging and discharging the bit lines in the memory cell to the desired bit being written [14].

3.1 Conventional SRAM

The 6T SRAMC circuit diagram is shown in Fig. 4. SRAMC is called a static ram cell because the data could be held for a long time until the power is being provided forever. Six transistors are used in SRAMC; PM6, PM7, NM6, and NM7 are composed of the two cross-coupled CMOS inverters plus two NMOS transistors (NM8 and NM9) known as access transistors. It is known as the 6T cell. Each bit is a transistor-compatible SRAMC, which forms two cross-coupled inverters. This cell has two stable states either 0 or 1 [15, 16].

Fig. 4
figure 4

SRAM cell schematic

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3.2 Current Latch Sense Amplifier

The sense amplifier is a circuit of great importance in cache memory architecture. One of the bit line releases during reading operation while the other bit line remains at supply voltage. Due to the capacity of the large bit line, the slow discharge is small and the bit cells access the transistor. To accomplish this, a minor difference between the values of the bit line voltages [17, 18] is amplified by the SA at digital levels. Figure 5 indicates the current latch sense amplifier schematic.

Fig. 5
figure 5

Current latch sense amplifier schematic

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The circuit operation is as follows [19, 20]. On bit lines, the differential voltage is transferred to SA3 and SA4 CLSA inputs. If both SA1 and SA2 start discharge at high outputs SAEN is pulled high. These results in a higher power by NM12 compared to NM13 because of its higher Vgs. This allows the output V3 to be discharged faster than V4.

4 Analysis of Result

Figure 6 describes the output waveform of WDC, for cases arise: (a) when Bit = 0 V and WE = 0 V BL = VDD and BLBAR = VDD, (b) Bit = 0 V WE = VDD so, BL = 0 V and BLBAR = VDD/2, (c) Bit = VDD WE = 0 V so, BL = 0 V and BLBAR = VDD/2 and (d) Bit = VDD WE = VDD so, BL = VDD and BLBAR = 0 V.

Fig. 6
figure 6

Output waveform of WDC

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Figure 7 describes the both write operation and hold operation of the SRAM cell. There is a pull-up network (PM6 and PM7), pull-down network (NM6 and NM7), and access transistor (NM8 and NM9) which allows data to store and sense amplifier to read the data. Figure 8 describes the read operation of CLSA when both SAEN and WL are pulled high, during that time only the sense amplifier senses the data from the SRAM cell at bit lines and gives output at V3 and V4.

Fig. 7
figure 7

Output waveform of SRAM cell

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Fig. 8
figure 8

Output waveform of CLSA

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Table 1 describes that as increasing in value of resistance power consumption decreases as because resistance is a path stopper for current in a circuit and no effect on the area, performance, and speed whereas Table 2: describes the power reduction techniques applied over CLSA.

Table 1 Different parameter of single-bit cache memory architecture
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Table 2 Single-bit cache memory architecture analysis of different parameters with power reduction techniques applied over CLSA
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Table 3: describes the power consumption of single-bit cache memory architecture on applying power reduction techniques over SRAM cell and CLSA consume less power 111.58 µW up to 56%. All the table’s results depicted that single-bit cache memory architecture with forced stack technique over SRAM cell and CLSA consume the lowest power 11.58 µW with an increase in the number of the transistor from 35 to 39. There is always a trade-off between power consumption and area.

Table 3 Single-bit cache memory architecture analysis of different parameters with power reduction techniques applied over SRAM cell and CLSA
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5 Conclusion

In the proposed work, single-bit cache memory architecture has been implemented and it is comprised of WDC, SRAM cell, and a current latch sense amplifier. Apart from its different parameters of single-bit cache memory architecture has been analyzed at different values of resistance (R). Furthermore, power reduction techniques such as sleep transistor technique, forced stack technique, and dual seep technique are applied over SRAM cell and CLSA. Results depicted that on the increasing value of R power consumption reduce at R = 42.3 kΩ consume 26.78 µW power and a single-bit cache memory architecture having SRAM cell and CLSA with forced stack technique consume 11.58 µW. In future scope, this work can be done in form of an array.