Keywords

1 Introduction

There are several memory elements within a system in contemporary computing systems, for example, main memory, cache memory, and register data [1,2,3]. With the latest development in the very large-scale integrated circuits (VLSI) technology, high-speed STSRAM is the industry’s prime desire. Memory is the key component of a chip, and STSRAM is used as a cache memory because it is a fundamental part of memory that is important in data execution [4,5,6]. STSTRAM is a volatile memory since the information persists once the power is usable, which is essential and cannot be ignored in terms of reducing capacity in STSRAM. In an STSRAM architecture, the LSA is one of the elements of the data line. LSA is used to detect the difference in voltage at the input of the bit lines and to create a complete voltage swing at the output during the read operation [7]. Instead of having to measure or wait for the swing voltage level, the memory will simply store ‘0’ or ‘1’ to save time while reading.

The demand for mobile devices and a battery-operated embedded system is growing with greater breadth as VLSI industries grow. Cache memory design for single bit architecture is a central part of memory that plays a key role in data execution, cache occupying 60% to 70% of chip region [8]. As chip consumption increases rapidly, microprocessor velocity is then decreased. One million transistors also increase and degrade the efficiency of single-chip failure rates, so the industry is working to build a low-speed and low-power memory circuit, which keeps the development of the VLSI system informed. In current high-performance microprocessors, more than half of transistors are for cache memories, and in the future, this proportion is projected to increase [9]. STSRAM is usually the option for built-in stock because it is robust in such chips in a noisy environment. The device can use necessary memory cells by integrating them in SRAMC that are the right size for system requirements. Memories time for access and power consumption are calculated primarily by the configuration of LSA. LSA is one of the most important peripheral circuits in memory systems [10].

2 Literature Review

Year

Author

Features

Sensing delay (ns)

Supply voltage (V)

2002

A Chrysanthopoulos et al.

Conventional sense amplifier

7.1

2.5

2002

A Chrysanthopoulos et al.

Clamped bit line sense amplifier

0.35

2.5

2002

K.-S. Yeo et al.

Low-power current sense amplifier

1.04

2.0

2002

A Chrysanthopoulos et al.

Simple four transistor sense amplifier

1.85

2.5

2004

Chun-lung Hsu et al.

High-speed sense amplifier

0.51

1.8

2005

Z. H. Kong et al.

Ultralow-power

1.46

1.8

2007

Sandeep Patil et al.

Self-biased charge-transfer sense amplifier

0.723

1.8

2008

Ya-Chun Lai et al.

Latch type sense amplifier

0.33

1.8

2008

Anh-Tuan Do et al.

Fully current mode sense amplifier

0.38

1.8

2008

Do Anh-Tuan et al.

High-speed sense amplifier

0.26

1.8

2011

Anh-Tuan Do et al.

Alpha latch sense amplifier

0.566

1

2011

Anh-Tuan Do et al.

Decoupled sense amplifier

0.214

1

3 Cache Memory Design for Single Bit Architecture

In this section, cache memory design for single bit architecture has been described with their design as shown in Fig. 1. Cache memory design for single bit architecture made up of WDC, STSRAM, and LSA [11, 12].

Fig. 1
figure 1

Cache memory design for single bit STSRAM VLSA architecture schematic

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3.1 Circuit of Write Driver

Figure 2 shows the circuit diagram of WDC. Each of the bit-lines in the STSRAM write driver circuit is quickly discharged from pre-charge stages to below the STSRAM write margin [13].

Fig. 2
figure 2

Write driver circuit schematic

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The write enable (WE) signal usually activates the WDC, which uses full-swing discharge to drive the bit-line from the pre-charge level to the ground. Five PMOS (PM1, PM2, PM3, PM4, and PM5) as well as five NMOS (NM1, NM2, NM3, NM4, and NM5) are used by WDC. When allowed by WE, the input data causes one of the transistors to become PM1 or NM1 through inverters, and a strong 0 is applied by discharging BTL and BTLBAR from the pre-charge level to ground level [14].

3.2 Six Transistor Static Random Access Memory Cell

It is used for operations at low power, low voltage. Here, each bit is stored using bistable latching circuitry. Figure 3 shows the STSRAM cell schematic, the pull-up transistors are M1 and M2 (PMOS), while the driver transistors are M3 and M4 NMOS. These bit lines enhance the margin of noise. The value of measurable output voltage swings is given by differential circuitry. Logic 0 or 1 is stored as long as the power is on, but unlike DRAM cells [15, 16]; it does not need to be refreshed. In STSRAM architecture, the size of the transistors is most important for the proper operation of the transistors.

Fig. 3
figure 3

Six transistor static random access memory cell schematic

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3.3 Voltage Latch Sense Amplifier

The voltage latch sense amplifier schematics developed in this work are shown in Fig. 4. Internal nodes are pre-charged via the bit-lines in this design. The architecture of the circuit runs directly via input bit lines, based on its internal nodes [17–20].

Fig. 4
figure 4

Schematics of voltage latch sense amplifier

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Fig. 5
figure 5

WDC output waveform

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If the word line is high pulled and followed by the amplifier sensor trigger, NM12 is OFF, and PM8 and PM9 are ON. If the voltage difference in the bit-lines increases, the random bit in the internal nodes of the LSA varies accordingly in voltage. When the LSA signal SAEN is claimed, the interlinking inverters consist of PM10, NM10, PM11, and NM11 raise the voltage difference to the highest swing power [21,22,23,24,25] as shown in Fig. 5.

4 Result Analysis

Figure 5 describes the output waveform of WDC, for cases arise: (a) when Bit = 0 V and WE = 0 V BTL = VDD and BTLBAR = VDD, (b) Bit = 0 V WE = VDD so, BTL = 0 V and BTLBAR = VDD/2, (c) Bit = VDD WE = 0 V so, BTL = 0 V and BTLBAR = VDD/2 and (d) Bit = VDD WE = VDD so, BTL = VDD and BTLBAR = 0 V.

Figure 6 shows the output waveform of STSRAM which holds two operations:

Fig. 6
figure 6

STSRAM cell output waveform

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  1. 1.

    Write Operation

  2. 2.

    Hold Operation.

There are three types of transistors: (i) access transistors, (ii) pull-up transistor, and (iii) pull-down transistors. Figure 7 describes the read operation of VLSA when both SAEN = 1 and WL = 1 at that time sense amplifier works in read operation. Note: P = V2/R as this voltage is constant on varying the R and analyzing the power consumption.

Fig. 7
figure 7

Output waveform of VLSA

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Fig. 8
figure 8

Process corner simulation

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Figure 8 shows the process corner simulation of cache memory design for single bit architecture at six different corners, whereas Fig. 9 shows the Monte Carlo simulation for cache memory design for single bit architecture.

Fig. 9
figure 9

Monte carlo simulation

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Table 1 depicts that consumption of power decreases as increase in value of resistance, whereas Fig. 10 shows the comparative analysis of different parameters of cache memory design for cache memory architecture using different values of resistance of Table 1 in form of a chart.

Table 1 Analysis of different parameter of single bit SRAMC VLSA design
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Fig. 10
figure 10

Analysis of different parameter of single bit SRAMC VLSA design at different values of resistance

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5 Conclusion

In the proposed work, cache memory design for single bit architecture has been implemented, and on different values of resistance, different parameters of cache memory design for single bit architecture have been analyzed. To check the robustness of cache memory design for single bit architecture process corner simulation and Monte Carlo simulation also have been done. Furthermore, consumption of power of cache memory design for single bit architecture has been analyzed and the conclusion arises that consumption of power decreases on increasing resistance value (i.e., 14.32 µW). In the future scope, this work can be implemented in form of an array.