Online Testable Efficient Latches for Molecular QCA Based on Reversible Logic

Abstract

Quantum computer is very advanced technology in upcoming era and can capable to solve any complex problem with very fast computation power. The proposed models for quantum computation are quantum dot cellular automata (QCA). The molecular QCA has the tendency to high error rates. In case of molecular quantum dot cellular automata, the main objective of circuit design is the reduction of circuit area with wanted functional behavior. In this article, we propose the efficient design of online testable latches based on reversible logic for molecular QCA that is very much cost-effective respect to circuit area and other parameters. We use reversible gates having conservative property; i.e., capability for producing the equal number of 1s in output bits as input bits. So, conservative logic gates are subset of parity preserving reversible gate. Fault patterns of used conservative logic gate are analyzed for single stuck-at faults in molecular QCA circuit. Our proposed latches are able to examine single stuck-at fault, missing/additional QCA cell defect online, including permanent or transient fault in molecular QCA and efficient respect to circuit area. The designs of QCA layouts for various latches are presented and verified using QCA Designer and the Verilog HDL library of QCA devices is used to present HDLQ design tool.

1 Introduction

Molecular QCA is most demandable emerging nanotechnology having small shaped component, ultra low power consumption and high clock frequency [1, 2]. Molecular QCA cell can define the logic states, such as logic 0 or logic 1, by depending upon the electrons’ location in it. Due to the tendency of high error rate in nanotechnology, it is necessary to check the error frequently in the circuit. And it is possible only when the circuit has online testable capability. Defect in molecular QCA can occur in various phases, such as synthesis, deposition, and runtime; missing/additional defects take place in synthesis and deposition phase [3]. Stuck-at fault and transient fault are more likely to take place in runtime for external unwanted energy or internal cell defect.

We introduce an efficient design of online testable latches for molecular QCA. The molecular QCA has various application of reversible computation. The reversible computation is possible only if the primary elements of the system are reversible gate. A reversible gate computes the function with bijective in manner. A reversible gate is n$\times$n gate which has same number (n) of inputs and outputs with bijective mapping within input and output vectors. Landauer has proved that $k_BTln2$ Joules energy is dissipated for every bit of information loss which is possible only irreversible logic [4]. Where, $k_B$ is the Boltzmann constant and T represents the operating temperature. This energy dissipation Will not be occurred with reversible computation, firstly proposed by Bennett [5]. The previous exertion for applying reversible logic in molecular QCA is described in [6], in which reversible logic testing properties are described in a 1-D array of QCA cells.

The conservative reversible gates are used as basic component of the latches to provide online testability in the circuits and to reduce energy dissipation.

Conservative logic belongs to the logic family having a power to generate same number of 1s in the input and the output signals [7].

Definition 1: Bit conserving circuit is referred as conservative logic circuit. It must hold same number of 1s in input and output signals.

Definition 2: A circuit with is conservative in nature with having the reversibility property is known as conservative reversible logic circuit.

Definition 3: All high signals at the input lines of the conservative logic network are the cause to produce all high signals at the output lines, and all low signals at the input lines of the conservative logic network are the cause to produce all low signals at the output lines. Figure 1 shows the structure of very well-known reversible conservative Fredkin gate.

Fig. 1

Conservative reversible Fredkin gate

Here, the fault patterns for single stuck-at fault are analyzed. We get a clear idea from the fault patterns (for different type of faults) that when single fault will occur in the conservative logic gate it must mismatch the parity and specifically mismatch the number of 1s in output lines with input lines. Based on the above property we design online testable latches using conservative Fredkin gate. In existing paper, irreversible latches for molecular QCA are proposed without having online testable capability [8, 9]. Concurrently testable latches are proposed with decidedly less-cost efficient design which needs more molecular QCA cells to design [10]. So, the main contribution in this literature is to design various latches having online testable capability with cost-effective nature which needs few molecular QCA cells and minimal garbage lines.

This literature is arranged by the following way: Sect. 2 describes background work related to our work including the basics, cost metric of molecular QCA and also turn the attention to related work. Section 3 presents conservative reversible gate and online testing of molecular QCA. Various online testable reversible latches in molecular QCA framework are designed in Sect. 4. Implementation and Various simulation results of the proposed online testable latches in molecular QCA framework to verify our designs are shown in Sect. 5. Single stuck-at fault patterns are shown in tabular format and normal circuit simulation result is mentioned in graphical format to verify the designs in this section. Finally, Sect. 6 describes conclusions along with upcoming works.

2 Background

Various type of faults may occur in molecular QCA, like stuck-at fault [11], missing/additional cell defect which is more likely during synthesis and deposition phase for miss placement of the QCA cell [3], etc. It also has the tendency for permanent faults as well as transient faults caused by radiation, thermodynamic impact, and other effects, like the variation of power within excited and ground states is very small [12]. So, any type of single stuck-at fault, single cell defect (missing/additional) including permanent fault or transient fault detection are important. Our proposed designs covered all of such faults. Thus the proposed designs are significant.

Fig. 2

QCA cell: a QCA cell formation. b Bi-polar QCA cell

2.1 Basics of molecular Quantum Cellular Automata Computing

QCA cell which is nothing but coupled dot system, is the basic unit of molecular quantum dot cellular automata nanotechnology circuit. Each cell contains four dots at the vertices of the square. Among four dots two electrons can quantum mechanically tunnel in this QCA cell. Due to electrostatic repulsion, the electrons are occupying diagonal positions, which is mentioned in Fig. 2a. Positions of electron pair in the QCA cell are caused to polarize the QCA cell either in logic 0 (P $=-1$) or in logic 1(P $=+1$), is mentioned in Fig. 2b.

The four distinct periodic phases cascaded clocking is accomplished timing in QCA [4]. Figure 3a displays four distinct periodic phases are consist of switch, hold, release, and relax. Wire crossing in the molecular QCA is a remarkable achievement. The nature of the QCA cell makes wire-crossing more vulnerable. Undesirable crosstalk between wires may be introduced here. Wire-crossing determination is done either using different clock zones at different wires or using rotated QCA cells at one of the wires by coplanar approach. Considering $90 ^{\circ }$ (X cell) and $45^{\circ }$ ($+$ cell) structures form the coplanar wire crossing which is mentioned in Fig. 3b. The crossover can also be realized with multilayered wires. Instead of the coplanar strategy, multilayer strategy is more powerful [13]. Multilayer implementation of wire-crossing with same type of cells is mentioned in Fig. 3d.

Fig. 3

a Clocking. b Coplanar wire-crossing. c Wire. d Multilayer wire-crossing

Primary and the basic device of QCA computing is MV or majority voter, which is mentioned in Fig. 4. Property of majority voter is modeled as MV(A, B, C) $=$ AB $+$ BC $+$ CA, which is a function to produce output from the majority of inputs A, B, and C. All other basic functions like OR, AND can be realized with majority voter. Two-input OR or a two-input AND gate can be realized through the fixation of a input cell at MV to p $= +1$ or p $= -1$, respectively. Realization of OR gate, AND gate is shown in Fig. 5.

Fig. 4

Majority voter

Fig. 5

a OR gate. b AND gate

INVERTER is another important logic device, which can be realized with many ways in QCA computing. Pictorial representation is mentioned in Fig. 6. Signal in QCA circuit may transfer through either inverter chain (Fig. 6c) or binary wire (Fig. 3c).

Fig. 6

a Inverter [type-1]. b Inverter [type-2]. c Inverter chain [type-3]

2.2 Cost Metric

Any circuit in molecular QCA framework must be designed with some cost-effective manner, which depends on number of QCA cell, majority voter, clock cycle is used to design the QCA circuit. We should reduce the cost metric to design efficient circuit.

Molecular QCA Cell

The QCA cell is primary element of the molecular quantum dot cellular automata. The QCA cell count should be minimum for reducing the circuit area. This is the most important cost metric because the main objective to design the circuit in any framework minimizes the area.

Majority Voter

In order to design the circuit with basic gates, majority voter is important to realize AND and OR gates. Minimum number of majority voters is considered as an efficient design to reduce the circuit area.

Clock Zone

The clock zone is another important cost metric because it estimates the time delay of the circuit. Thus, to make efficient circuit design we should minimize the delay or minimize the clock zone.

2.3 Related Work

Lent et al. proposed molecular QCA firstly in 1993 [14]. The first physically implemented molecular QCA produced Al islands and tunnel junctions. The experiment is done at 10mK [15]. As the circuit in molecular QCA having tendency to high error rate, so researchers were trying to concentrate on testing and the testing of molecular QCA first addressed in 2004 [3]. Here, the QCA devices defect characterization has been demonstrated, and also described how the difference between the testing of molecular QCA and the CMOS. QCA defects were modeled at molecular level for combinational circuits in [16]. It characterized faults in respect to single additional/missing cell defect on different QCA devices (i.e., INV, fan-out, MV, L-shape wire, cross wire, etc.). The test generation for molecular QCA described in [11]. For the QCA reversible logic circuit, single additional/missing cell defects were proposed in [6]. It concludes that reversible 1-D array must be C-testable. The fault-tolerant molecular QCA designs using the modular redundancy with the shifted operands, were shown in [17]. Considering various faults and wire delay, defect is modeled and SR latch is presented. The sequential circuits in QCA is presented based on the SR latch [8, 9]. The coplanar crossing in molecular QCA was presented and proved that wires with rotated cells can be considered as thermally more stable cells in [18]. The single stuck-at fault testing for combinational circuit is presented in [19]. Testing of reversible circuits is shown in [20,21,22,23,24] but they have not test circuit in of molecular framework. Though testable latches in QCA framework for missing/additional cell defect was done in [10], but it does not target to test stuck-at fault and it is not much efficient design respect to circuit area, time delay, etc.

Latches and flip-flops are the primary ingredients of various registers. Nowadays, researchers incorporate registers also for transliteration [25] to increase the processing speed. The automated transliteration and translation [26] are booming topics for now [27, 28]. Energy efficient fault- tolerant architecture is designed for wireless sensor networks [29]. Moreover, researchers introduced testable features into the sequential circuits which makes it more interesting [30,31,32]. In future, researchers may incorporate the proposed scheme in their applications [33] to improve efficiency.

3 Conservative Reversible Gate and Online Testing of Molecular QCA

The conservative reversible gate is a unique type of parity preserving logic which belongs to conservative reversible logic family. It has capability to form same number of 1s in output signals as the input signals. We shall discuss the conservative logic with case study of Fredkin gate. If anyone is interested to design the circuit with another conservative logic gate then they can also easily make the circuit online testable. The Fredkin gate is 3 $\times$ 3 conservative gate with reversible property. $I_v =$ {A, B, C} and $O_v =$ {A, A’B$\oplus$AC, A’C$\oplus$AB} having quantum cost 5; first proposed by Fredkin and Toffoli [7]. This is mentioned in Fig. 1. As the Fredkin gate belongs to the conservative reversible logic family. So, it is capable to produce equal number of 1’s in input lines as output lines which can be cleared from behavioral analysis of the Fredkin gate which shown in Table 1. It should be noted that any type of single permanent or transient fault will cause to miss the conservative property as well as parity preserving property. Thus, depending upon the conservative property of the Fredkin gate, we can easily detect the fault online. Launder four-phase clocking scheme is most popular to design circuit in molecular QCA framework and our proposed designs are based on this clocking scheme. Figure 7 represents the Fredkin gate structure in molecular QCA.

Table 1 Behavioral study of the Fredkin gate

Fig. 7

QCA layout of Fredkin gate

The Fredkin gate is considered as basic building block of proposed latches based on the reversible logic in molecular QCA framework, having 6 FOs, 2 INVs, 6 MVs, 8 LSs, 5 CWs, and to implement it 233 QCA cells with 4 clock zone are needed.

In this work, we use Fredkin gate behalf of conservative logic gate. The Verilog library of the hardware description language notations for QCA layout is used to show all possible single stuck-at fault and single cell defect (missing/additional) in majority voters (MJs), CWs, INVs, L-shape wires (LSs), FOs. The Verilog HDL library of molecular QCA devices is used as HDLQ design tool i.e., MV, FO, L-shape wire, Cross wire (CW), INV having ability to inject the faults [34]. Design HDLQ model for the Fredkin gate is mentioned in Fig. 8.

Fig. 8

Modeling for the Fredkin gate with QCA layout. INV describes inverter in QCA, FO illustrates QCA fanout device, MV describes QCA majority voter, LS shows QCA L-shape wire, and CW illustrates QCA cross wire

Verilog HDL simulator helps to simulate the proposed design and this is successfully done for the appearance of all the possible single stuck-at faults to determine corresponding erroneous outputs. 43 fault patterns were produced through the entire test for single stuck-at 0 and 45 fault patterns for single stuck-at 1. The fault patterns for single stuck-at 0 fault is mentioned in Tables 2 and 3, fault patterns for single stuck-at 1 fault is mentioned in Tables 4 and 5. In these tables, k represents the three-bit pattern of corresponding decimal value of roman k. s0 describes bit pattern 000 (decimal 0), a1 denotes bit pattern 001 (decimal 1), and so on. From the fault pattern table, it is clear that there must be mismatch in conservative nature if there exits any stuck-at fault. Conservative gate also mismatch in parity if there exist single cell defect (missing/additional) is occurred [10]. So, the fault patterns indicate the presence of fault, if any conservative discrepancy (i.e., number of 1s in input vector is unequal to number of 1s in output vector) is found between the input and output vectors. More generally parity mismatch helps to find the faults. So, any permanent or transient faults can be detected by parity mismatch property of conservative logic gate. Finally, it can be claimed that the Fredkin gate based on molecular QCA is online testable gate for its parity preserving property.

Table 2 Stuck-At 0 fault patterns in Fredkin gate (first 22 lines)

Table 3 Stuck-At 0 fault patterns in Fredkin gate (remaining lines)

Table 4 Stuck-At 1 fault patterns in Fredkin gate (first 22 lines)

Table 5 Stuck-At 1 fault patterns in Fredkin gate (remaining lines)

4 Design of Online Testable Latches in molecular QCA Framework

In this part, we design efficient online testable latches based on minimum number of online testable conservative reversible Fredkin gate with minimal number of QCA cells, few majority voters, and significant clock zones.

Lemma

Any circuit based on online testable gates is also online testable. $\square$

Proof

Online testable capability denotes the power of fully fault coverage runtime. Here, we consider the single stuck-at fault. So, the test vector should cover all zeroes and all ones in the input lines and output lines. The fault cover achieves with either to generate all combination of outputs with some characteristic or adding extra line which defines the correctness of the circuit. Now, if the testable advantage achieves with the first characteristic then there is no problem to test each block, because it can be tested with comparing specified characteristic for every combination of input which is applied from preceding block. If the testable advantage achieves with the mentioned second characteristic then each block must generate error detection signal for each combination of provided input to that block. Finally, after getting green signals from every block it can easily confirm to have no fault in the circuit.

Lemma

Proposed designs of sequential circuit based on multilayer approach are online testable. $\square$

Proof

Multilayer based Fredkin gate in molecular QCA is online testable, proved in section III. According to Lemma 1, circuit based on Fredkin gate is online testable. As, it is sequential circuit, its input depends on output of previous state. According to conservative principle, generate output must have same number of 1’s as applied 1’s in input lines in fault-free case. Thus, after comparing equality in generated number of 1’s at output with applied number of 1’s including previous state signal to input of the Fredkin gate, and consider $\overline{Q}$ as extra line which must be opposite of Q, we can claimed that the generated signal is error free and the circuit is fault free.

4.1 D Latch (Positive Level Triggered)

Equation of the level triggered D latch (positive):

$$\begin{aligned} Q_{n+1} = (D\wedge E) \vee (\overline{E} \wedge Q_{n}) \end{aligned}$$

where, D and E are input bit and enable line, respectively. $Q_n$ and $Q_{n+1}$ are primary outputs of the present state and the next state, respectively. As per the level triggered D latch (positive) characteristic equation, it is cleared the straightaway reflection of D passes to the output signal when E is high, as $Q_{n+1} = D$. Positive level triggered D latch stays identical in its past state when the enable signal is low; as $Q_{n+1} = Q_n$. Figure 9 shows the D latch (positive level triggered). Though fan-out is restricted at reversible circuit whereas fan-out is acceptable in molecular QCA. Thus, Fig. 9 is valid for low power QCA.

Fig. 9

Positive level triggered D latch with output Q and $\overline{Q}$

As Fredkin gate has capability to detect fault online for its parity preserving characteristic, so the proposed D latch with the Fredkin gate also has the capability to detect fault online. To test the D latch, it is necessary to considered $Q_{n}$, E and D signals for input vector and G1, G2, $Q_n$ as output vector; if parity mismatch is found within input and output vectors then it can be claimed that there is fault in the circuit. For testing the D latch (positive level triggered) with output Q and $\overline{Q}$, we only need to check same criteria and we should check additional $\overline{Q}$ bit which must be inverse of Q line if there exists no fault.

4.2 D Latch (Negative Level Triggered)

It will directly transfer the input signal D to Q line, when value of E is low; else estate will remain unchanged as before. The negative level triggered D latch can be modeled as,

$$\begin{aligned} Q_{n+1} = (D\wedge \overline{E}) \vee (E \wedge Q_{n}) \end{aligned}$$

From the characterize equation, it is clear that D latch (negative level triggered) is mapped to Fredkin gate because of its MUXing capability, is mentioned in Fig. 10.

Fig. 10

Negative level triggered D latch

The proposed negative level triggered D latch also has capability to detect fault online. For testing, it is necessary to consider $Q_{n}$, E, and D signals for input vector and G1, G2, and Q signals as output vector. If parity mismatch is found within input and output vectors, then it can be claim that there is fault in the circuit because of its parity preserving property. For testing the D latch (negative level triggered) with output Q and $\overline{Q}$, only need to check same criteria and we should check additional $\overline{Q}$ bit which must inverse of Q bit for no fault.

Fig. 11

Proposed design of T latch based on Fredkin gate

4.3 T Latch

In this section, we design online testable T latch in molecular QCA framework. T latch is explained bellow:

$$\begin{aligned} Q_{n+1} = (T \oplus Q_n) E+ \overline{E}Q_n \end{aligned}$$

According to characterize equation of T latch, it is mapped to the conservative Fredkin gate. We design the online testable T latch with two Fredkin gates only. Our proposed design of online testable T latch with output lines Q and $\overline{Q}$ is mentioned in Fig. 11. To test the T latch online, it is necessary to consider $Q_{n}, \overline{Q}_{n}$, T, and E signals as input vector and G1, G2, G3, $Q_{n+1}$, and $\overline{Q}_{n+1}$ signals as output vector. Now if there is any mismatch in parity between the input and output vectors then this will be considered as faulty circuit.

4.4 JK Latch

In this section, online testable JK latch in QCA framework with two Fredkin gate is presented. The JK latch can be described as,

$$\begin{aligned} Q_{n+1} = (J \overline{Q}_n + \overline{K}Q_n)E +\overline{E}Q_n \end{aligned}$$

From the characterize equation, it is clear that the JK latch can be realized using D latch or SR latch, but by this methodology circuit complexity will high, so alternative circuit diagram for JK latch is mentioned in Fig. 12.

Fig. 12

JK latch based on Fredkin gate

The proposed JK latch based on the Fredkin gate also has capability to detect fault online. To test the JK latch, we should considered J, $\overline{K}$, E, and $Q_{n}$ signals as input vector and G1, G2, G3, $Q_{n+1}$ signals as output vector; if parity mismatch is found within input and output vectors, then it can be claimed that there is fault in the JK latch. For testing the JK latch with output Q and $\overline{Q}$, only need to check same criteria and we should check additional $\overline{Q}$ bit which must opposite of Q bit in fault-free case.

4.5 SR Latch

In this section, we propose the design of online testable SR latch in molecular QCA framework based on Fredkin gate. The characteristic equation of SR latch can be established as,

$$\begin{aligned} Q_{n+1}=(S + \overline{R}Q_n) E + \overline{E} Q_n \end{aligned}$$

The characteristic equation can be mapped to D latch (positive level triggered) as $D E + \overline{E} Q_n$, where $D = (S + \overline{R}Q_n)$, and both of the equations can be realized using Fredkin gate. Our architecture for the testable SR latch is mentioned in Fig. 13.

Fig. 13

SR latch based on Fredkin gate

Proposed SR latch based on the conservative Fredkin gate also have capability to detect fault online. To test the SR latch, we should consider all input bits including $Q_n$ as input vector, and G1, G2, G3, G4, G5, G6, Q as output vector. If parity mismatch is found within input and output vectors, then it can be claimed to have fault in the SR latch. For testing the SR latch with output Q and $\overline{Q}$, only need to check same criteria and we should check additional $\overline{Q}$ bit which must opposite of Q bit in fault-free case.

5 Implementation to Functionally Verify The Proposed Multilayer Latches in Molecular QCA Framework

Verification of every design is done by using the QCADesigner version 2.0.3 [35]. Following parameters are used for the bistable approximation, cell size $=$ 18 nm, radius of effect $=$ 41 nm, convergence tolerance $=$ 0.001000, number of samples $=$ 182 800, clock amplitude factor $=$ 2.000, clock high $=$ 9.8 $e^{-22}$, clock low $=$ 3.8 $e^{-23}$, relative permittivity $=$ 12.9, maximum iterations per sample $=$ 1000, and layer separation $=$ 11.5000 nm. In the QCA layouts, each multilayer Fredkin gate will produce output by one clock cycle delay since Fredkin gate is designed with four clock zones, as shown in Fig. 7. The simulated waveform of the multilayer conservative Fredkin gate is mentioned in Fig. 14 by which it verifies the functionality with one delay of the circuit. The applied inputs to multilayer Fredkin gate at clock zone 0 and the produced outputs from Fredkin gate at clock zone 4. The simulation result is exactly same as truth table of the Fredkin gate. It verifies the correctness of the proposed multilayer implementation of Fredkin gate. The important fact is that all the designs are practical as well as usable, since it was verified using the QCADesigner simulator that generated signals are proper without degradation. To perform correctly, all signals should appear simultaneously at the majority gate [36]. All designs follow this characteristic.

Fig. 14

Simulated results of multilayer Fredkin gate

5.1 Multilayer QCA Layout and Simulation of the Proposed Latches

All the latches are implemented with proposed multilayer Fredkin gate. The QCA layout of the triple layer D latch (positive level triggered) is mentioned in Fig. 15 and it is verified using QCADesiger version 2.0.3 which is same as expected truth table. To better understanding of conservative property, in Fig. 15 garbage outputs are managed with proper clock zone. G1 and G2 represent the garbage output. To verify the design, the simulated results of the proposed triple layer D latch (positive level triggered) are mentioned in Fig. 16. Here, arrows are used to verify the functionality of the proposed triple layer D latch (positive level triggered). Arrow A, B, and C show that when E is high then D will be reflected in $Q_{n+1}$; like arrow A and arrow C indicate that when E $=$ 1 and D $=$ 0 then $Q_n =$ 0. And since E $=$ 0 in the next cycle, $Q_{n+1}$ will maintain its previous value as 0 (mentioned with lines D and F), Arrow B indicate that when E $=$ 1 and D $=$ 1 then Q $=$ 1. And since E $=$ 0 in the next cycle, $Q_{n+1}$ will maintain its previous value of $Q_n$ as 1 (mentioned with lines E). To design the triple layer D latch (positive level triggered), 292 QCA cells, 0.44 $\upmu \mathrm{m}^2$ area and four clock zones are needed. All the generated output will be delayed by one clock cycle as Fredkin gate has one clock cycle delay. The Table 6 which is compact form of Fig. 16, summaries the working functionality of proposed triple layer D latch (positive level triggered).

Fig. 15

Grid representation of proposed triple layer D latch (positive level triggered)

Fig. 16

Simulated output of the triple layer D latch (positive level triggered)

Figure 17 shows multilayer representation of negative level triggered latch which is just opposite of positive level triggered latch. According to the characterize equation of negative level triggered latch, when E is low then D will be reflected in output $Q_{n+1}$ and when E is high then the output $Q_{n+1}$ will remain same as $Q_n$. To better understanding of conservative property, in Fig. 17 garbage outputs are managed with proper clock zone. G1 and G2 represent the garbage output. To verify the design, the simulated results of the proposed D latch (negative level triggered) are mentioned in Fig. 18. The trip of the arrows A and C indicate that when E $=$ 0 and D $=$ 0 then $Q_n =$ 0. Since enable (E) $=$ 1 in the next cycle, $Q_{n+1}$ will maintain its previous value as 0 (mentioned with lines D and F), The trip of the arrow B indicates that when both enable and the input line D are low then Q is based on previous state (i.e., high). And since E $=$ 1 in the next cycle, $Q_{n+1}$ will maintain its previous value of $Q_n$ as 1 (mentioned with lines E). To design the triple layer D latch (negative level triggered), 272 QCA cells, 0.40 $\upmu \mathrm{m}^2$ area and four clock zones are needed. All generated outputs are delayed by a clock cycle. Table 7 which is compact form of Fig. 18, summaries the working functionality of proposed triple layer D latch (positive level triggered).

Table 6 Truth table of the D latch (positive level triggered)

Fig. 17

Grid representation of proposed triple layer D latch (negative level triggered) with output Q based on multilayer Fredkin gate

Fig. 18

Simulated results of triple layer D latch (negative level triggered)

Figure 19 presents the top view representation of QCA layout and Fig. 20 show the simulation results of the triple layer T latch. To design the triple layer T latch, 628 QCA cells, 0.92 $\upmu \mathrm{m}^2$ area and eight clock zones are needed. Thus, after two clock cycles the correct output is generated. Table 8, summaries the working functionality of proposed triple layer T latch. The trip of arrow A represents toggling of $Q_n$ at $Q_{n+1}$ as when E $=1$, T $=1$, and $Q_n=$ 1 then $Q_{n+1}=$ 0. The Trip of the arrow B represents when E $=$ 0, T $=$ 0, and $Q_n=$ 1, then $Q_{n+1}=$ 1. The trip of the arrow C represents when E $=1$, T $=0$, and $Q_n=$ 0, then $Q_{n+1}=$ 0.

Table 7 Truth table of the D latch (negative level triggered)

Fig. 19

Top view QCA layout of proposed triple layer T latch with output Q based on multilayer Fredkin gate

Fig. 20

Simulated results of triple layer T latch

Table 8 Truth table of the T latch

Top view of the triple layer JK latch is represented in Fig. 21. The simulated results are shown in Fig. 22. To design the triple layer JK latch, 780 QCA cells, 1.50 $\upmu \mathrm{m}^2$ area and eight clock zones are needed, as two Fredkin gates are cascaded in series. Thus, the correct output will be generated after delay of two clock cycles. Table 9 which is compact form of Fig. 22, summaries the working functionality of proposed triple layer JK latch. The trip of arrow A represents when E $=$ 1, J $=$ 0, K $=$ 1, and $Q_n=$ 0, then $Q_{n+1}=$ 0. The trip of arrow B represents when E $=$ 1, J $=$ 1, K $=$ 0 and $Q_n=$ 0 then $Q_{n+1}=$ 1. The trip of arrow C represents when E $=$ 1, J $=$ 1, K $=$ 1, and $Q_n=$ 1 then $Q_{n+1}=$ 0. The trip of arrow D represents when E $=$ 1, J $=$ 0, K $=$ 0, and $Q_n=$ 0 then $Q_{n+1}=$ 0. The trip of arrow E represents when E $=$ 0, J $=$ 1, K $=$ 0, and $Q_n=$ 0, then $Q_{n+1}=$ 0.

Fig. 21

Top view QCA layout of proposed triple layer JK latch with output Q using multilayer Fredkin gate

Fig. 22

Simulated results of triple layer JK latch

Top view of QCA layout of the triple layer SR latch are presented in Fig. 23. The simulated results are shown in Fig. 24. To design the triple layer SR latch, 981 QCA cells, 2.17 $\upmu \mathrm{m}^2$ area and twelve clock zones are needed, as three Fredkin gates are cascaded in series. Thus, the correct output will be generated after delay of three clock cycles. Table 10 which is compact form of Fig. 24, summaries the working functionality of proposed triple layer SR latch. The trip of arrow A represents when E $=$ 1, S $=$ 1, R $=$ 0 and $Q_n=$ 1, then $Q_{n+1}=$ 1. The trip of arrow B represents when E $=$ 1, S $=$ 0, R $=$ 1and $Q_n=$ 1 then $Q_{n+1}=$ 0. The trip of arrow C represents when E $=$ 0, S $=$ 1, R $=$ 1and $Q_n=$ 1 then $Q_{n+1}=$ 1. The trip of arrow D represents when E $=$ 1, S $=$ 0, R $=$ 0, and $Q_n=$ 1, then $Q_{n+1}=$ 1.

Table 9 Truth table of the JK latch

Fig. 23

Top view QCA layout of proposed triple layer SR latch with output Q based on multilayer Fredkin gate

Fig. 24

Simulated results of triple layer SR latch

Our multilayer latches are significant than the state-of-the-art latches in molecular QCA concerning with delays, Fredkin gates count, and the used number of QCA cells. A clock cycle delay is needed for each Fredkin gate in critical path. Comparison analysis of proposed multilayer latches in molecular QCA with existing one is mentioned in Table 11.

6 Conclusions and Future Work

We propose online testable latches for molecular QCA using conservative logic (i.e., multilayer Fredkin gate). The proposed online testing approach concerning with parity preserving characteristics of the multilayer Fredkin gate without increasing the area of the circuit. It is beneficial for permanent fault as well as transient fault which can be detected by parity mismatch between inputs and outputs. $\overline{Q}$ may not be considered depending upon the prior information about circuit design, where $\overline{Q}$ is introduced separately using NOT gate. For that case $\overline{Q}$ will be tested using knowledge of Q, as $\overline{Q}$ must be opposite of Q in fault-free case. The online testable designs for various multilayer latches, QCA layouts, and their simulation results are presented. The proposed methodology is applicable for the online detection of the single cell defect (missing/additional) model, single stuck-at fault model, or unidirectional faults. The proposed methodology is not appropriate to detect the bidirectional multiple faults, say expecting fault free output vector is {1110}, and due to bidirectional faults generated output vector is {1101} where parity of the input vector and output vector is same, thus fault is not detected. The input signals can be regenerated at output lines due to the reversible property. Thus, input vector and output vector will not only preserve the parity, it must be exactly same. This characteristic can be implemented with our proposed approach to resolve the pitfall (detection of bidirectional multiple faults) of our proposed methodology in future, and also our proposed methodology can be implemented to design testable memory in molecular QCA framework. Finally, we can conclude that our proposed multilayer latches are implementation of online testable sequential circuit in molecular QCA framework with multilayer approach which is efficient respect to the area, delay, etc.

Table 10 Truth table of the SR latch

Table 11 Comparison analysis of proposed multilayer latches