Abstract
This paper qualitatively explores the relations between two kinds of side-channel leakages, i.e., the fault sensitivity (FS) and the power consumption. The FS is a relatively new active side-channel leakage, while the power consumption is one of the earliest researched passive side-channel leakage. These two side-channels are closely related with regard to both the security evaluation and the countermeasure proposal. This paper experimentally answers the following important issues such as the relationship between these two side-channels, whether they share the same leakage function and whether they can be protected by the same countermeasure. Based on two FPGA AES implementations without countermeasures, we first confirm a high correlation between the power consumption and the FS. Then, we construct the leakage profiles for the FS and the power consumption to explain the detailed relations between them. We also confirm a successful key recovery using the FS profile as the leakage model for power consumption. Based on these discoveries, we believe that FSA can be used as an evaluation tool to find the first-order leakage with less data-complexity, and it is more reasonable to achieve the countermeasures against FSA and power analysis from different design levels.
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References
DPA contest website, http://www.dpacontest.org/home/
Brier, E., Clavier, C., Olivier, F.: Correlation Power Analysis with a Leakage Model. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 16–29. Springer, Heidelberg (2004)
Chari, S., Rao, J.R., Rohatgi, P.: Template attacks. In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 13–28. Springer, Heidelberg (2003)
Endo, S., Li, Y., Homma, N., Sakiyama, K., Ohta, K., Aoki, T.: An efficient countermeasure against fault sensitivity analysis using configurable delay blocks. In: Bertoni, G., Gierlichs, B. (eds.) FDTC, pp. 95–102. IEEE (2012)
Endo, S., Sugawara, T., Homma, N., Aoki, T., Satoh, A.: An on-chip glitchy-clock generator for testing fault injection attacks. Journal of Cryptographic Engineering 1(4), 265–270 (2011)
Gandolfi, K., Mourtel, C., Olivier, F.: Electromagnetic Analysis: Concrete Results. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 251–261. Springer, Heidelberg (2001)
Gierlichs, B., Batina, L., Tuyls, P., Preneel, B.: Mutual Information Analysis. In: Oswald, E., Rohatgi, P. (eds.) CHES 2008. LNCS, vol. 5154, pp. 426–442. Springer, Heidelberg (2008)
Kocher, P.C.: Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems. In: Koblitz, N. (ed.) CRYPTO 1996. LNCS, vol. 1109, pp. 104–113. Springer, Heidelberg (1996)
Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)
Li, Y., Nakatsu, D., Li, Q., Ohta, K., Sakiyama, K.: Clockwise collision analysis – overlooked side-channel leakage inside your measurements. Cryptology ePrint Archive, Report 2011/579 (2011), http://eprint.iacr.org/
Li, Y., Ohta, K., Sakiyama, K.: Revisit fault sensitivity analysis on WDDL-AES. In: HOST, pp. 148–153. IEEE Computer Society (2011)
Li, Y., Ohta, K., Sakiyama, K.: New Fault-Based Side-Channel Attack Using Fault Sensitivity. IEEE Transactions on Information Forensics and Security 7(1), 88–97 (2012)
Li, Y., Ohta, K., Sakiyama, K.: Toward effective countermeasures against an improved fault sensitivity analysis. IEICE Transactions 95-A(1), 234–241 (2012)
Li, Y., Sakiyama, K., Gomisawa, S., Fukunaga, T., Takahashi, J., Ohta, K.: Fault sensitivity analysis. In: Mangard, S., Standaert, F.-X. (eds.) CHES 2010. LNCS, vol. 6225, pp. 320–334. Springer, Heidelberg (2010)
Mangard, S., Oswald, E., Popp, T.: Power analysis attacks - revealing the secrets of smart cards. Springer (2007)
Moradi, A., Mischke, O., Paar, C., Li, Y., Ohta, K., Sakiyama, K.: On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting. In: Preneel, B., Takagi, T. (eds.) CHES 2011. LNCS, vol. 6917, pp. 292–311. Springer, Heidelberg (2011)
Morioka, S., Satoh, A.: An Optimized S-Box Circuit Architecture for Low Power AES Design. In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 172–186. Springer, Heidelberg (2003)
National Institute of Advanced Industrial Science and Technology (AIST), Research Center for Information Security (RCIS). Side-channel Attack Standard Evaluation Board (SASEBO), http://staff.aist.go.jp/akashi.satoh/SASEBO/en/index.html
Nikova, S., Rechberger, C., Rijmen, V.: Threshold Implementations Against Side-Channel Attacks and Glitches. In: Ning, P., Qing, S., Li, N. (eds.) ICICS 2006. LNCS, vol. 4307, pp. 529–545. Springer, Heidelberg (2006)
Research Center for Information Security (RCIS) of National Institute of Advanced Industrial Science and Technology. SASEBO project overview
Saeki, M., Suzuki, D., Shimizu, K., Satoh, A.: A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques. In: Clavier, C., Gaj, K. (eds.) CHES 2009. LNCS, vol. 5747, pp. 189–204. Springer, Heidelberg (2009)
Schindler, W., Lemke, K., Paar, C.: A Stochastic Model for Differential Side Channel Cryptanalysis. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 30–46. Springer, Heidelberg (2005)
Standaert, F.-X., Archambeau, C.: Using Subspace-Based Template Attacks to Compare and Combine Power and Electromagnetic Information Leakages. In: Oswald, E., Rohatgi, P. (eds.) CHES 2008. LNCS, vol. 5154, pp. 411–425. Springer, Heidelberg (2008)
Standaert, F.-X., Malkin, T., Yung, M.: A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks. In: Joux, A. (ed.) EUROCRYPT 2009. LNCS, vol. 5479, pp. 443–461. Springer, Heidelberg (2009)
Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA ResistantASIC or FPGA Implementation. In: DATE, pp. 246–251. IEEE Computer Society (2004)
Veyrat-Charvillon, N., Standaert, F.-X.: Mutual information analysis: How, when and why? In: Clavier, C., Gaj, K. (eds.) CHES 2009. LNCS, vol. 5747, pp. 429–443. Springer, Heidelberg (2009)
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Li, Y. et al. (2013). Exploring the Relations between Fault Sensitivity and Power Consumption. In: Prouff, E. (eds) Constructive Side-Channel Analysis and Secure Design. COSADE 2013. Lecture Notes in Computer Science, vol 7864. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-40026-1_9
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DOI: https://doi.org/10.1007/978-3-642-40026-1_9
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