Automatic Synthesis of Analog Integrated Circuits Including Efficient Yield Optimization

Abstract

In this chapter, the authors show the main aspects and implications of automatic sizing, including yield. Different strategies for accelerating performance estimation and design space search are addressed. The analog sizing problem is converted into a nonlinear optimization problem, and the design space is explored using metaheuristics based on genetic algorithms. Circuit performance is estimated by electrical simulations, and the generated optimal solution includes yield prediction as a design constraint. The method was applied for the automatic design of a 12-free-variables two-stage amplifier. The resulting sized circuit presented 100 % yield within a 99 % confidence interval, while achieving all the performance specifications in a reasonable processing time. The authors implemented an efficient yield-oriented sizing tool which generates robust solutions, thus increasing the number of first-time-right analog integrated circuit designs.

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

1 Introduction

Analog integrated circuit (IC) design presents different characteristics from its digital counterparts in terms of number of devices, design methodologies, and design automation.

As digital electronic systems are modeled using hardware description languages (HDLs), digital design processes are largely removed from technology considerations and from actual physics of the devices. Digital IC design typically focuses on logical correctness, maximization of circuit density, placement, and routing of circuits. The highly automated process produces variable, fab-independent netlists and easily generated layouts that are usually “right the first time.”

Analog/mixed-signal designs, on the contrary, are notorious for requiring more than just one prototypation cycle. They typically include a wide variety of primitive devices, such as digital MOS and mid- and high-voltage MOS and bipolar junction transistors (BJT), as well as a host of passive elements that include capacitors, resistors, inductors, varactors, and diodes. These devices are often required to operate under unfriendly environments, where they have to cope with high-temperature differences, high voltages, switching noise, and interference from neighboring elements. Analog circuits are also much more sensitive to noise than digital circuits, which can severely affect their performance.

Unlike digital designs, in which only a few device parameters, such as threshold voltage, leakage, and saturation currents, need to be considered, analog/mixed-signal design must cope with much more complex specifications. It is more concerned with the physics of devices. Parameters such as voltage gain, matching, power dissipation, and output resistance, for example, depend on voltage levels, device dimensions, and process parameters. Each device in the analog world must, therefore, be carefully characterized and modeled across a very large parameter space to allow for a reliable circuit design. This process usually leads to fab-specific designs that typically require more than one iteration to get the mask set right [14].

The success for first-time-right analog design in a traditional design flow can be summarized in three parts. The first is the experience of the design team. It can be acquired with a library of tried and tested design topologies and well-characterized devices, allowing a correct estimation of process variations. The second is the availability of good design kits and device models, providing an accurate characterization of transistor behavior in different operation points. Furthermore, a wide range of statistical models must be made available, including worst-case models, statistical corner models, and Monte Carlo mismatch models, making it possible for circuit design sizing and design centering techniques to achieve high-yielding and robust designs. The third is a good planning for optimizing the time necessary for a full design cycle, from initial specification to a functional prototype. A tight time-to-market, in general, plays a crucial role in the definition of the design schedule. In this context, a mandatory strategy for first-time-right silicon in analog design is the automation of critical design stages such as transistor sizing.

Automatic synthesis of analog integrated circuits is a very hard task due to the complex relationship between technology process parameters, device dimensions, and design specifications. The design of analog building blocks requires circuit parameters to be sized such that design specifications are met or even optimized. An efficient search in the design space is mandatory when hard specifications must be accomplished, mainly for low-voltage and low-power design. The exploration of all transistor operation regions is also fundamental for the search for an optimized circuit [18].

As devices shrink with the fabrication technology evolution, the impact of process variations on analog design becomes significant and can lead to circuit performance degradation and yield falling below specification [1, 20, 35]. Gate oxide thickness, for example, approaches a few angstroms in state-of-the art technologies. Although $V_{\text{DD}}$ scales to sub 1 V supply voltage headroom, threshold voltage does not scale in the same proportion due to leakage. Less headroom means more sensitivity to threshold voltage variation. This issue has led to the inclusion of yield prediction as a fundamental step in the analog design process. However, this prediction—estimated by Monte Carlo analysis—might demand high computational effort if included at each iteration of an optimization procedure [36].

With Monte Carlo simulation, one can find out how the distribution in circuit response relates to the specification. The aspects of yield considered here are the percentage of devices, which meet the specification and the design centering with respect to the specification.

Another important aspect is avoiding over-design, when the circuit characteristics are within specification but with a wide margin, which could be at the expense of area or power and ultimately, cost. Although not recommended, this strategy is still in use by most of the analog design teams because of the low level of design automation.

A typical design process is iterative, first for finding a solution which meets the nominal specification, and then moving on to a solution that meets yield and economic constraints, including the effects of variations in device characteristics. It helps to understand the relationship of the design parameters to the circuit response and the relationships of the different types of circuit response. However, it is a slow process, since it depends on the direct influence of the human designer.

The inclusion of yield prediction in the automatic circuit sizing procedure allows for a realistic modeling which contributes for a first-time-right design. The problem is that it often presents high complexity due to the long simulation time in the optimization process. Several hours is often required to optimize a typical-sized circuit.

In this work, we demonstrate the main aspects and implications of automatic sizing including yield. Different strategies for accelerating performance estimation are addressed.

In Sect. 2.2, we show the different strategies for automatic analog circuit sizing, while in Sect. 2.3 we show how it can be approached as an optimization problem. In Sect. 2.4, we present a tool for circuit sizing using optimization and considering yield. Then, in Sect. 2.5, we discuss the results of the automatic design of a Miller OTA using the tool. Finally, we draw conclusions in Sect. 2.6.

2 Strategies for Automatic Analog Integrated Circuit Sizing

In the analog design flow, the definition of transistor sizes, device values, and bias voltages and currents is called the sizing procedure. It can be implemented, in general, by two approaches: knowledge-based sizing or optimization-based sizing.

In the knowledge-based approach, the circuit sizing is performed based on the experience of the design team. This method uses analytic design equations that relate circuit performance to device characteristics. Although it is a good approach for older technologies, it is not suitable for designs in modern fabrication technologies, since the modeling of short-channel effects turns the design equations extremely complex and simplification leads to values far from the actual circuit response. Also, it is difficult to explore transistor operation regions other than strong inversion. An example of knowledge-based sizing tool is Procedural Analog Design (PAD) tool [33].

The optimization-based approach transforms the design procedure in a general optimization problem. The circuit performance is modeled in a cost function, and the design space is explored automatically by an optimization heuristic in the search for optimized solutions. According to Barros et al. [5], the optimization method is dependent on the design optimization model, which can be classified in equation based, simulation based, or learning based.

The equation-based method uses simplified equations originated from large- and small-signal analysis of the circuit topology. It allows for a fast estimation of circuit performance, but lacks in accuracy. The application of this method has been demonstrated in the literature, mainly with the use of geometric programming [15, 23]. The circuit performance is modeled by posynomial equations, which guarantee the finding of an optimal solution in a fast computational time. However, this modeling implies simplifications that compromise accuracy, since performance equations are not posynomials.

Simulation-based methods use electrical simulators such as SPICE to estimate circuit performance. This performance estimation method is purely numerical and tends to consume a large computational time, since several iterations are necessary to resolve the convergence algorithm implemented by SPICE. However, this method gives a very accurate performance estimation. Electrical simulation allows the calculation of all design specifications, in both time and frequency domains. Another advantage is that circuit variability and sensitivity can be estimated by corner models or Monte Carlo simulation.

The tool proposed by Phelps et al. [29] uses simulated annealing heuristic to explore a multi-objective cost function using Cadence Spectre simulator for performance estimation. The exploration of the design space using multi-objective genetic optimization is presented by De Smedt and Gielen [8], in which the calculation of the hypersurface of Pareto-optimal design points explores the trade-off between competing objectives.

Learning-based methods provide fast performance evaluation and good accuracy. It is obtained by using techniques such as support vector machines [5] and neural fuzzy networks [3]. The models are trained from electrical simulations. The drawbacks are the high effort necessary to train the models with the desired accuracy—a huge amount of simulation data is necessary—and the low configurability, since a simple modification in the circuit topology makes the trained model no more suitable for the application.

Figure 2.1 shows the execution scheme of an analog optimization-based tool with simulation-based performance evaluation. The tool takes as input the circuit topology, design specifications, and technology parameters. The optimization core generates solutions for the optimization problem according to the implemented optimization technique. For each iteration, it is necessary to evaluate the quality of the generated solution. It is quantified by a cost function, which gives an indication of the performance of the generated solution with respect to the desired specifications. The performance is estimated by SPICE simulation of a set of test benches in which design specifications can be extracted.

Fig. 2.1

General optimization-based design flow

2.1 Sources of Process Parameter Variability

Submicrometer integrated circuit technologies present high incidence of variability in the fabrication process. These variations affect the performance of ICs, both analog and digital. In digital circuits, the effects are directly perceived in the propagation time of the digital signal. In analog circuits, process variations affect the operation point of the individual transistors and cause mismatch that can lead to loosing circuit functionality [10].

According to Orshansky et al. [27], the variations in the IC fabrication process can be classified in three categories: front end, back end, and variations caused by the environment. Front-end variations are caused by the first steps of device fabrication, such as ion implantation, oxidation, polysilicon deposition, and others. In these stages, random variations occur in the transistor gate sizes ($W$ and $L$), threshold voltage ($V_{\text{TH}}$), silicon oxide thickness ($T_{\text{ox}}$), among others.

Back-end variations are characterized by the process variations caused in the metallization step of the fabrication process. The width of metal lines and interconnection vias, at different metal levels, are affected by random variations. At the same time, passive devices—such as capacitors and inductors—present variations around the nominal values, because they are implemented, in general, by metal lines.

The environment variations refer to the differences between the nominal and real operation conditions of the IC. We can cite temperature and supply voltage variations as example. These variations are systematic and can be treated at design level in order to attenuate their effects.

Figure 2.2 illustrates three of the main parameter variation sources present in an IC fabrication process. A random fluctuation of dopants occurs due to the difficulty in controlling the exact quantity and energy of the ion implantation in small devices. Some ions are located at undesired regions, and the concentration presents nonuniform patterns. At the same time, there is a random variation in the effective channel length and width, making it slightly different from the drawn dimensions. Devices with large gate length are less sensitive to process imperfections. Polysilicon width does not produce large variations in $W$, since this dimension is defined by the diffusion region, which, in general, has a large area [10]. Finally, the gate oxide thickness $T_{\text{ox}}$ presents a random variation gradient along the wafer area.

Fig. 2.2

Representation of the main variation sources in the integrated circuit fabrication process: random doping fluctuation, effective gate dimensions, and gate oxide roughness

According to Orshansky et al. [27], front-end variations are very relevant for an analog design. In order to exemplify the influence of a variation in the fabrication process over an integrated circuit, consider the threshold voltage $V_{\text{TH}}$. For large channel transistors with uniform doping [34], it can be estimated by

$$ V_{\text{TH}} = V_{\text{TH0}} + \gamma (\sqrt {2|\phi_{F} | + V_{\text{SB}} } - \sqrt {2|\phi_{F} |} ), $$

where $V_{\text{TH0}}$ is the threshold voltage for a long-channel device with source-bulk voltage equal to zero, $\phi_{F}$ is the Fermi level, and $\gamma$ is obtained by

$$ \gamma = \frac{{\sqrt {2q{\epsilon}_{Si} N_{\text{sub}} } }}{{C_{\text{ox}} }}. $$

Here, $q$ is the fundamental charge of an electron, $\epsilon_{Si}$ is the silicon permittivity, $N_{\text{sub}}$ is the density of electrons in the substrate, and $C_{\text{ox}}$ is the silicon oxide capacitance.

In this context, we can verify that a variation in the number of dopants in the substrate ($N_{\text{sub}}$) has a great effect in the threshold voltage. The same occurs with a variation in $C_{\text{ox}}$, which is dependent on the gate oxide thickness $T_{\text{ox}}$:

$$ C_{\text{ox}} = \frac{{\epsilon_{\text{ox}} }}{{T_{\text{ox}} }}. $$

Although well controlled, the gate oxide thickness can present relevant variations over different regions of the wafer.

The standard deviation of $V_{\text{TH}}$ can be estimated by Orshansky et al. [27] as follows:

$$ \sigma_{{V_{\text{TH}} }} = 3.19 \cdot 10^{ - 8} \frac{{T_{\text{ox}} N_{\text{sub}}^{0.4} }}{{\sqrt {L_{\text{eff}} W_{\text{eff}} } }}. $$

We can verify that, besides $T_{\text{ox}}$ and $N_{\text{sub}}$, the variation of $V_{\text{TH}}$ is related to the inverse square root of the effective gate area. Small devices are, therefore, more sensitive to process variations.

2.2 Estimating Circuit Yield

Yield is the ratio of accepted ICs over the total number of fabricated ICs. If the yield is significantly less than 100 %, this implies a financial loss to the IC manufacturer. Therefore, it is important to calculate and maximize the manufacturing yield already during the design stage [12]. This is called design for manufacturability, which implies techniques for yield estimation and yield optimization.

Failures that show up when the IC is in use in a product in the field are even more expensive, for instance when the IC is used under extreme operating conditions such as high temperatures. To try to avoid this, the design has to be made as robust as possible. This is called design for robustness or design for quality, which implies techniques for variability minimization and design centering.

Some works have been done in the analog automatic synthesis theme considering design for manufacturability. The strategy for calculating the yield-aware specification Pareto front is explored by Mueller-Gritschneder and Graeb [25]. Other approaches propose the use of simplified sampling techniques for yield estimation in order to reduce computational time [6, 13, 22]. The use of response surface method (RSM) for circuit performance modeled as quadratic functions of the process parameters is also reported [31]. All of them, however, face challenges in accuracy, compromising the search for the optimized circuit.

The problem is how to estimate yield with accuracy in a reasonable processing time. Monte Carlo is the standard technique for statistical simulation of circuits and for yield estimation during the design phase. The reason for this is that Monte Carlo is applicable to arbitrary circuits, arbitrary statistical models, and all performance metrics of interest, while allowing arbitrary accuracy. On the other hand, circuit size, nonlinearity, simulation time, and required accuracy often conspire to make Monte Carlo analysis expensive and slow. A single Monte Carlo run can cost a few thousand SPICE simulations, and higher accuracy requirements demand longer runs.

A detailed analysis of traditional pseudo-random Monte Carlo sampling, Latin hypercube sampling (LHS), and quasi-Monte Carlo (QMC) techniques is done by Singhee and Rutenbar [32]. The goal is to reduce the number of sample points while keeping the accuracy of the yield prediction. For high-dimensional problems, QMC presents advantages in terms of simulation speed, giving 2× to 8× speedup over conventional Monte Carlo for roughly 1 % accuracy levels.

3 Problem Formulation

The problem of analog integrated circuit sizing is modeled as an optimization problem by translating the circuit performance specifications to a cost function dependent on the transistor dimensions, capacitances, resistances, and bias voltages and currents (design free parameters). This cost function fully defines the performance space, which can be explored by an optimization heuristic for a minimum (or maximum) point. The optimized solution is contained in this point.

Consider a set of circuit performance functions (design specifications) ${\mathbf{X}}({\mathbf{p}},{\mathbf{q}}) = \{ S_{1} ,S_{2} , \ldots ,S_{k} \}$, which depends on a set of design parameter values ${\mathbf{p}}$ and on a set of technology parameter values ${\mathbf{q}}$. $S$ is an individual specification, and $k$ is the number of design specifications. Performance functions for an operational amplifier can be the low-voltage gain ($A_{v0}$), gain–bandwidth product (GBW), slew rate (SR), dissipated power ($P_{\text{diss}}$), etc. Design parameters are the free variables the designer can handle in order to design the circuit, such as gate dimensions (length $L$ and width $W$), reference currents, and capacitor values. Technology parameters include electrical MOS model parameters (such as oxide thickness $T_{\text{ox}}$ and threshold voltage of the long-channel device at zero substrate bias $V_{\text{TH0}}$), supply voltages, and operation temperature range.

The acceptance of a circuit by a specification test can be expressed as follows:

$$ {\mathbf{X}}({\mathbf{p}},{\mathbf{q}}) \in {\varvec{\Phi}}\text{.} $$

${\varvec{\Phi}}$ is the region of acceptable performance specifications in the performance space. The acceptance region ${\varvec{\Psi}}$ in the design parameter space is defined by

$$ {\mathbf{X}}({\mathbf{p}},{\mathbf{q}}) \in {\varvec{\Phi}} \to {\mathbf{p}} \in {\varvec{\Psi}}. $$

A manufactured circuit will be considered acceptable if all of its actual performances fall within acceptable limits, i.e., if $S_{i}^{L} \le S_{i} \le S_{i}^{U}$, where the indexes $L$ and $U$ correspond to lower and upper specification limits, respectively.

The parameter values ${\mathbf{q}}$ vary statistically around a nominal value, caused by unavoidable process fluctuations in manufacturing, with a joint probability density function (JPDF) $g({\mathbf{p}},{\mathbf{q}})$.

Two different types of parameter variation are present in a semiconductor fabrication process: global (interdie) and local (intradie) variation. Global variation of the electrical parameters is induced by process fluctuations in manufacturing, which affect all devices in a circuit in the same way. It is independent of length $L$ and width $W$.

Local variation induces differences between identically designed devices caused by edge roughness, doping variation, boundary effects, etc. In this case, the variation of $L$ depends on the width of the device. Other parameters such as sheet resistance, channel dopant concentration, mobility, and gate oxide thickness are inversely dependent on the gate area ($W \cdot L$), since the parameters average over a greater distance or area [10]. Mismatch is dominated by local variation and affects the electrical behavior of input differential pairs and current mirrors, even for well-designed layouts.

The manufacturing yield $Y$ of a circuit can be formulated by the number of accepted circuits that pass the specification test over the total number of considered circuits:

$$ Y = {\text{Prob}}({\mathbf{X}}({\mathbf{p}},{\mathbf{q}}) \in {\varvec{\Phi}}). $$

The manufacturing yield can be estimated by repeating circuit electrical simulation and performance specification evaluation. This is done by Monte Carlo analysis, which simulates the variation of the electrical parameters that affect all devices in a circuit. In order to simulate global variation, the process parameters are randomly selected in each simulation run and globally assigned to all device instances in a design. For local variation simulation, every instance of a device that contains matching-relevant parameters receives an individual random value around a typical mean.

There are some design techniques typically used to improve yield in analog circuits [7]. These techniques can be implemented—in combination or not—in three design stages: topology selection, transistor sizing, and physical synthesis [24]. The focus of this chapter is restricted to yield maximization at the transistor sizing stage.

In our approach, yield maximization is performed by determining a set of nominal values of the design parameters, ${\mathbf{p}}$, that maximizes the probability of the random performances lying within ${\varvec{\Phi}}$ [4]. However, there is not an explicit for estimating $g({\mathbf{p}},{\mathbf{q}})$. The yield optimization problem can be formulated in the space of independent statistical disturbances. The region of acceptability in the disturbance space contains all possible combinations of disturbances that can occur in the manufacturing of a circuit, which, for specific nominal parameter values, do not result in unacceptable performance. Yield optimization is, therefore, performed by modifying the acceptability region in a way that increases the coverage of a fixed probability distribution [9].

This yield can be calculated in both the device parameter space and the circuit performance space. This calculation, however, is complicated by the fact that, in either space, one of the two elements is not known explicitly: the statistical fluctuations are known in the device parameter space but not in the circuit performance space, whereas the acceptability region is known in the performance space but not in the parameter space [12]. Monte Carlo simulation, combined with an optimization procedure, is the most effective way to estimate acceptability region in the performance space.

3.1 Transistor Sizing as an Optimization Problem

The proposed approach for optimization of circuit performance explores the yield prediction as a design objective in an automatic sizing procedure. It is a nonlinear programming problem and requires the formulation of a single performance function (cost) to minimize subject to a set of inequality constraints, as in the following standard form [26]:

$$ \begin{aligned} & \mathop {\text{minimize}}\limits_{{{\mathbf{p}},{\mathbf{q}}}} \quad F_{m} ({\mathbf{p}},{\mathbf{q}}),\quad i = 1, \ldots ,M \\ & {\text{subjectto}}\quad C_{n} ({\mathbf{p}},{\mathbf{q}}) \le C_{n(ref)} ,\quad n = 1, \ldots ,N \\ \end{aligned} $$

where $M$ is the total number of $F_{m}$ specifications to optimize, and $N$ is the number of $C_{n}$ constrained performance functions. Here, ${\mathbf{X}}$ can be rewritten as a set of design objectives and design constraints:

$$ {\mathbf{X}}({\mathbf{p}},{\mathbf{q}}) = \{ F_{1} , \ldots ,F_{M} ,C_{1} , \ldots ,C_{N} \} . $$

$C_{n} ({\mathbf{p}},{\mathbf{q}})$ is a function that is dependent on the specification type: minimum required value ($C_{ \hbox{min} } ({\mathbf{p}},{\mathbf{q}})$) or maximum required value ($C_{ \hbox{max} } ({\mathbf{p}},{\mathbf{q}})$) [5].

These functions are shown in Fig. 2.3, where $a$ is the maximum or minimum required value, and $b$ is the bound value between acceptable and unacceptable performance values.

Fig. 2.3

Design constraint performance metrics: a minimum required value specifications and b maximum required value specifications

Acceptable but non-feasible performance values are the points between $a$ and $b$. They return intermediate values for the constraint functions in order to allow the exploration of disconnected feasible design space regions. These functions return additional cost for the cost function if the performance is outside the desired range. Otherwise, the additional cost is zero.

The constrained problem can be transformed into an unconstrained minimization problem using the penalty function approach:

$$ f_{c} ({\mathbf{p}},{\mathbf{q}}) = \sum\limits_{m = 1}^{M} {w_{m} \cdot \hat{F}_{m} ({\mathbf{p}},{\mathbf{q}})} + \sum\limits_{n = 1}^{N} {v_{n} \cdot \hat{C}_{n} ({\mathbf{p}},{\mathbf{q}})} . $$

(2.1)

Here, $w_{m}$ and $v_{n}$ are weights that indicate the relative importance of design objectives and design constraints, respectively. $\hat{F}$ and $\hat{C}$ are normalized design objective and design constraint functions, in order to keep all sum factors in the same order of magnitude.

Yield prediction can be easily included as a design objective in the cost function by adding a new term $\hat{Y}({\mathbf{p}},{\mathbf{q}},{\boldsymbol{\epsilon}}_{{\mathbf{q}}} )$ in the penalty function:

$$ f_{c}^{Y} ({\mathbf{p}},{\mathbf{q}},\epsilon_{{\mathbf{q}}} ) = \sum\limits_{m = 1}^{M} {w_{m} \cdot \hat{F}_{m} ({\mathbf{p}},{\mathbf{q}})} + \sum\limits_{n = 1}^{N} {v_{n} \cdot \hat{C}_{n} ({\mathbf{p}},{\mathbf{q}}) + \hat{Y}({\mathbf{p}},{\mathbf{q}},{\boldsymbol{\epsilon}}_{{\mathbf{q}}} )}. $$

(2.2)

This new term is dependent on the variability vector of technology parameters ${\mathbf{q}}$ given by ${\boldsymbol{\epsilon}}_{{\mathbf{q}}}$.

We define the characteristic function of ${\varvec{\Phi}}$ as

$$ I_{{\varvec{\Phi}}} ({\mathbf{X}}) = \left\{ {\begin{array}{*{20}l} 1 \hfill & {{\text{if}}\,{\mathbf{X}} \in {\varvec{\Phi}}} \hfill \\ 0 \hfill & {{\text{if}}\,{\mathbf{X}} \notin {\varvec{\Phi}}} \hfill \\ \end{array} } \right. $$

which is 1 for pass and 0 for fail. This is also known as the indicator function.

We can now define the circuit yield as the probability of a circuit instance lying in the acceptance region:

$$ Y = \int_{{\Re^{*} }} I_{{\varvec{\Phi}}} ({\mathbf{X}})g({\mathbf{X}})d{\mathbf{X}}. $$

There are other ways of calculating the yield, such as the use of process capability indexes ($Cpk$). The key idea is normalizing the distance to the feasible boundary by the standard deviation ($\sigma$) of its performance distribution to consider different process sensitivity. The application of these indexes, however, is out of the scope of this work.

In this work, the cost function is estimated by electrical simulations performed by Synopsys HSpice^®. The high computational cost of Monte Carlo simulations is diminished by performing circuit statistical analysis only for a subset of design solutions in the optimization process, as detailed in the next section.

3.2 Monte Carlo in the Optimization Flow

According to Eq. 2.2, we need to estimate circuit yield for the calculation of the cost function in the optimization flow. However, it is computationally costly if done by Monte Carlo simulation. On the other hand, if yield prediction is not considered, the optimization algorithm tends to find optimal solutions close to the border of the performance space. At these points, a small variation in the process parameters makes the performance specifications fall outside the acceptable region. Thus, a strategy for dealing with this problem must be included in the optimization process. It is called design centering.

There are two approaches for improving processing time considering Monte Carlo simulations: to reduce the number of iterations in which Monte Carlo simulations are necessary; and to reduce the number of runs in a Monte Carlo simulation. Both strategies are essential for improving the processing time during the search for an optimal design solution.

3.2.1 Reducing the Number of Monte Carlos Simulations

It is possible to reduce the number of iterations in which the calculation of $Y$ is necessary by analyzing the influence of this term over the entire cost function of Eq. 2.2. Figure 2.4 illustrates this strategy. Consider first the cost function in Eq. 2.1, which does not include yield. If the current solution is not a best solution candidate, i.e., if it is already a worst solution even without the calculation of $Y$, this solution can be discarded and Monte Carlo simulation is not necessary. As $f_{c}^{Y} ({\mathbf{X}})$ is unknown before the Monte Carlo simulation, the test for best solution candidate is done by the calculation of $f_{c} ({\mathbf{X}})$. Monte Carlo simulation is executed only when $f_{c} ({\mathbf{X}}) < \hbox{min} (f_{c}^{Y} ({\mathbf{X}}))$—where $\hbox{min} (f_{c}^{Y} ({\mathbf{X}}))$ is the current best solution.

Fig. 2.4

Optimization flow including yield prediction only for best solution candidates

At the start of the optimization process, the current best solution is frequently updated. However, the update frequency tends to reduce along iterations. Consequently, the number of iterations in which Monte Carlo simulation is necessary also reduces. Computational time is spared, since useless Monte Carlo simulations are avoided.

3.2.2 Reducing the Number of Runs in a Monte Carlo Simulation

The reduction in the number of runs in a Monte Carlo simulation can be implemented with the calculation of the number of samples ($n$) necessary to achieve a desired confidence level in the yield estimation.

The expected value of a random variable $p$ is $\mu = E(p)$. If we generate values $p_{1} , \ldots ,p_{n}$ independently and randomly from the distribution $p$, we can estimate $\mu$ as

$$ \hat{\mu } = \frac{1}{n}\sum\limits_{i = 1}^{n} {p_{i} } . $$

One of the great strengths of the Monte Carlo method is that the sample values themselves can be used to get a rough idea of the error $\hat{\mu }_{n} - \mu$. The average squared error in Monte Carlo sampling is $\sigma^{2} /n$. The most commonly used estimation of standard deviation $\sigma^{2}$ is

$$ \sigma^{2} = \frac{1}{n}\sum\limits_{i = 1}^{n} {(p_{i} - \hat{\mu }_{n} )^{2} } . $$

Monte Carlo sampling typically uses large values of $n$ for guaranteeing that this estimation is a good approximation to the actual $\sigma^{2}$.

A variance estimate $\sigma^{2}$ tells us that the error is on the order of $\sigma /\sqrt n$. We know that $\hat{\mu }_{n}$ has mean $\mu$ and we can estimate its variance by $\sigma^{2} /n$.

From the central limit theorem (CLT), we also know that $\hat{\mu }_{n} - \mu$ has approximately a normal distribution with mean $0$ and variance $\sigma^{2} /n$. The CLT can be used to get approximate confidence intervals for $\mu$. For 95 % confidence interval,

$$ \mu_{95\,\% } = \hat{\mu }_{n} \pm 1.96\frac{\sigma }{\sqrt n }. $$

For $99\,\%$ confidence interval,

$$ \mu_{99\,\% } = \hat{\mu }_{n} \pm 2.58\frac{\sigma }{\sqrt n }. $$

(2.3)

In a general way,

$$ \mu_{c\,\% } = \hat{\mu }_{n} \pm\Phi ^{ - 1} (1 - \alpha /2)\frac{\sigma }{\sqrt n }, $$

where $\alpha = 1 - c/100$ and $\Phi ( \cdot )^{ - 1}$ is the inverse cumulative distribution function (ICDF) of $N(0,1)$, the standard normal distribution. It is not available in closed form, and computation requires careful use of numerical procedures. It is also called “probit function,” an acronym for “probability unit function.” The probit function can be calculated as

$$ {\text{probit}}(p) = \sqrt 2 \cdot er\,f^{ - 1} (2p - 1). $$

In Matlab, the erfinv function is available for $er\,f^{ - 1}$ (inverse error function).

The steps for determining the number of Monte Carlo runs that matches a 99 % confidence interval for a determined specification are the following:

The correct choice of $n_{0}$ is fundamental for correctly estimating $n_{i + 1}$, since the confidence of $\sigma$ is dependent on $n$. With some simulations, we can infer that $n_{0} = 50$ is a good choice. Figure 2.5 shows the simulation of Eq. 2.3 for different values of $n$ for estimating the low-voltage gain of a Miller OTA. One can note that the graph stabilizes for $n = 50$, indicating a maximum number of samples ($n_{i + 1}$) equal to 400.

Fig. 2.5

Example of the maximum number of Monte Carlo runs calculated with Eq. 2.3. The circuit is a Miller amplifier, and the specification being measured is low-voltage gain. A good choice for $n_{0}$ is 50, the value where the graph stabilizes around 400

4 The UCAF Tool

UCAF is a CAD tool we developed for the automatic design of analog basic blocks including yield optimization. The tool sizes an integrated circuit by modeling it as an optimization problem and exploring efficiently the design space searching for optimal solutions. The main design flow of this tool is the same shown in Fig. 2.1. This general design flow is implemented in Matlab, and Synopsys HSpice is used for performance estimation.

The implementation of UCAF is made using modular functions to solve a generic analog IC design. These modular functions are shown in Fig. 2.6. Modularity allows a high degree of configurability, since each function can be substituted by a similar one without loosing functionality. For example, the optimization algorithm can be changed independently of the remaining functions. The tool is configured with the aid of an specific script as the input interface. Also, a graphical interface guides the user through the basic configurations. The output interface presents the generated solutions.

Fig. 2.6

UCAF structure

The “Core” module is the main function, which creates and organizes a new design, creates design folders, sets the modular functions, writes the simulation file, and performs other important tasks.

The function “Manufacturing Technology” implements the interface between the design and the fabrication technology. It reads and configures the parameters of simulation models from the design kit provided by the foundry.

Each new analog block inserted in the tool is saved in a cell library. This task is performed by the “Topology Library” function. These cells can be reused for different design specifications.

The “Optimization” function is responsible for the optimization algorithm that will guide the design space exploration. This function will be detailed further in Sect. 2.4.2.

The “Cost Function” implements Eq. 2.1 and is responsible for representing the design as an unconstrained minimization problem. In order to evaluate the cost function, it is necessary to estimate the values of the circuit specifications. Thus, the UCAF tool has the “Electrical Simulation” and “Specifications” functions. These functions are analyzed with more details in Sect. 2.4.3.

4.1 A Simplified Design Example

The design flow of the UCAF tool can be illustrated by the sizing of a simple active load differential amplifier circuit, as shown in Fig. 2.7. It is composed of four transistors and a tail current ($I_{\text{ref}}$). In order to simplify the design, we assume all transistors have the same size and $I_{\text{ref}}$ is fixed at 10 μA. This is not of practical use, but reduces the design problem to only two variables: the transistors channel width ($W$) and length ($L$). It also allows the visualization of the design space and provides an intuitive understanding of the optimization procedure.

Fig. 2.7

Active load differential amplifier

Table 2.1 summarizes the circuit performance specifications. The design objective is to minimize the gate area ($W \cdot L$). The cost function is calculated by

$$ f_{c} ({\mathbf{X}}) = \frac{1}{{{\text{Area}}_{ref} }} \cdot {\text{Area}}({\mathbf{X}}) + \sum\limits_{n = 1}^{N} C({\mathbf{X}}), $$

(2.4)

where ${\mathbf{X}}$ is the vector of free variables (${\mathbf{X}} = [WL]$), ${\text{Area}}_{\text{ref}}$ is the weighting parameter of the gate area, and $C_{n} ({\mathbf{X}})$ represents the constraint performance metric for the required specifications. $\sum C({\mathbf{X}})$ is calculated by

$$ \begin{aligned} \sum {C_{n} ({\mathbf{X}})} & = \,C_{ \hbox{min} } (A_{v} ({\mathbf{X}}),A_{{v{\text{ref}}}} ) + C_{ \hbox{min} } ({\text{PM}}({\mathbf{X}}),{\text{PM}}_{\text{ref}} ) \\ & \quad + C_{ \hbox{min} } ({\text{GBW}}({\mathbf{X}}),{\text{GBW}}_{ref} ) + C_{ \hbox{min} } ({\text{ICMR}}^{ + } ({\mathbf{X}}),{\text{ICMR}}_{\text{ref}}^{ + } ), \\ \end{aligned} $$

where $C_{ \hbox{min} }$ and $C_{ \hbox{max} }$ are the constraint performance functions shown in Fig. 2.3.

Table 2.1 Required specifications for the differential amplifier of Fig. 2.7

Assuming $W$ can vary between 0.22 and 10 μm and $L$ between 0.2 and 1 μm in steps of 0.05 μm, the optimization problem has 3120 possible solutions. We exhaustively calculated all 3120 solutions by electrical simulation. The resulting design space is shown in Fig. 2.8, where one can see the high nonlinearity of the cost function with respect to the design free variables. The optimization method searches the design space in order to find the value of $W$ and of $L$ that make the cost function have the lowest value. The optimal solution is reached at the point W = 1.62 μm and L = 0.54 μm, with a cost value of $0.11958$.

Fig. 2.8

Resulting design space composed by 3120 possible solutions for the differential amplifier of Fig. 2.7

The yield of each solution is evaluated by Monte Carlo simulations with 200 samples. The yield design space is shown in Fig. 2.9. It is possible to see that the design space is abruptly deformed at the region where the yield moves from 100 to 0 %. The optimal solution not considering yield represents, in practice, an yield of 51.8 %, indicating that the solution is located in a performance region very sensitive to process variations.

Fig. 2.9

Yield design space estimated by Monte Carlo simulation

Using Eq. 2.2, the design spaces of Figs. 2.8 and 2.9 can be joined to result in a design space including yield prediction, shown in Fig. 2.10. The optimal solution is now at W = 1.82 μm and L = 0.56 μm, with a cost value of $0.13658$ and yield of 99.8 %. The optimal point moved just slightly, but enough for considerably increasing the yield. The difference between this optimal value and the optimal value without yield is ΔW = 0.02 μm and ΔL = 0.02 μm.

Fig. 2.10

Design space considering yield prediction

4.2 Optimization

This is the main function of the UCAF tool, because it is responsible for exploring the design space. Here we opted for using genetic algorithms (GA), available in the Matlab Genetic Algorithm Optimization Toolbox (GAOT) [17].

The GA optimization approach is based on the biology theories of evolution and genetics. It is a non-deterministic meta-heuristic and can be used for optimizing nonlinear functions [11].

A specialized vocabulary is used for better reflecting the biological approach. A solution is called an “individual,” and since GA work with a number of solutions simultaneously, this set of solutions is called “population.” The iterations of the optimization process are called “generations,” and the cost function is referred as the “fitness” function.

In each generation, the individuals of the current population are crossed, generating new individuals that share characteristics from both parents (“crossover”) and that may suffer “mutation.” Each individual is represented as a chromosome, which in turn represents the optimization variables and their values.

Figure 2.11 shows the flowchart for optimizing the circuit size using GA. The GA core receives three inputs: the configuration parameters, the design specifications, and the technology parameters. The first step is creating an initial set of solutions, which is randomly performed by an initialization function. Each solution is then evaluated according to the fitness (cost) function, given by Eq. 2.4, but replicated here for convenience (recall that circuit specifications are estimated via electric simulations):

$$ f_{c} ({\mathbf{X}}) = \frac{1}{{{\text{Area}}_{\text{ref}} }} \cdot {\text{Area}}({\mathbf{X}}) + \sum\limits_{n = 1}^{N} C({\mathbf{X}}). $$

Fig. 2.11

Genetic algorithm flowchart for circuit sizing

Afterward, a subset of the solutions is chosen based on a selection function. The GAOT accepts the following selection functions: roulette wheel, normalized geometric rank selection, and tournament selection. The roulette wheel function first gives a normalized probability for each solution based on its fitness and then builds a roulette based on these probabilities. A random number is generated, and the solution with this number is selected. That way, the better the fitness, the higher the chance of being selected.

The selection by ranking orders the solutions based on their fitness and assigns a selection probability to each position. As with the roulette function, a solution is randomly chosen according to the probabilities. The difference here is that the probability of selection of a solution does not directly depend on its fitness, but only on its rank.

The third selection function chooses a number of solutions uniformly at random and keeps only the best solution. New tournaments are drawn, and the best overall solution is kept.

After selecting a subset of solutions, the next step in Fig. 2.11 is to perform crossover and mutation over the solutions. These operations are responsible for the state space search process of GA, since they generate new solutions. The crossover operation takes two solutions (chromosomes), splits them at some random point, and then combines one part from each chromosome, generating two new chromosomes. The mutate operation takes a single chromosome, selects a random point, and then inverts its value. Various functions for crossover and mutation are described in Houck et al. [16].

The new population is tested and, if the stop condition is satisfied, the circuit is sized and the process finishes. If it is not satisfied, a new generation (iteration) is performed. A maximum number of generations or a minimum cost function difference can be used as stop conditions.

4.3 Circuit Characterization

The optimization procedure has an interface with an external electrical simulator to estimate the circuit performance. For each specification, it is necessary to simulate a circuit test bench, performing AC, DC, or transient analysis. The current version of UCAF tool has some circuit standard test benches to measure the specifications of operational amplifiers [2, 30]. These test benches are shown in Fig. 2.12.

Fig. 2.12

Implemented test benches for measuring the performance of operational amplifiers. a AC open loop. b ICMR. c Output swing. d Slew rate. e CMRR. f PSRR

An AC analysis is performed for measuring the low-frequency gain ($A_{v0}$), the gain–bandwidth product (GBW), and the phase margin (PM). The configuration is shown in Fig. 2.12a. The results of this simulation can be plotted as a Bode diagram. From the gain curve, $A_{v0}$ and GBW specifications are extracted. In the same way, the phase margin is obtained in the phase curve, as shown in Fig. 2.13. In UCAF, this extraction is performed by the “Specification” modular function.

Fig. 2.13

Bode diagram used to extract low-frequency gain ($A_{v0}$), gain–bandwidth product (GBW), and phase margin (PM)

To obtain the input common-mode range (ICMR), the amplifier is connected in unity gain configuration, as shown in Fig. 2.12b. In this simulation, the input voltage is varied from a minimum to a maximum level through a DC analysis. Positive and negative values are obtained from simulation output when the gain is linear.

Figure 2.12c shows a circuit with a voltage gain of −10. This circuit is used for measuring the output swing (OS) with a DC analysis of input voltage sweep. As the gain is $- 10$, the output level of saturation is obtained. The difference between the minimum and maximum output levels is the OS specification.

The response speed of an amplifier (Slew Rate) is measured with the same configuration as ICMR. The goal of this simulation is the transient analysis of a step response of the circuit through the verification of the raise or fall behavior of the output voltage level, as illustrated in Fig. 2.12d.

The common-mode rejection ratio (CMRR) is given by the ratio of the common voltage ($V_{\text{cm}}$) by the generated output voltage. This specification represents the rejection amount of the input common-mode voltage due to the non-idealities of the amplifier. To measure this specification, an AC analysis is executed using the configuration shown in Fig. 2.12e, varying the operation frequency of the common-mode voltage source.

Like the CMRR, the power supply rejection ratio (PSRR) indicates the amplifier rejection capacity with respect to the noise coming from the power supply of the circuit. The circuit used to measure the PSRR is shown in Fig. 2.12f. The noise comes from the $V_{\text{DD}}$ and from the $V_{\text{SS}}$ power supplies, resulting in positive (PSRR⁺) and negative (PSRR⁻) rejection ratio, respectively. An AC analysis is executed to sweep the frequency of the voltage sources, simulating the noise coming from the power supplies. It is important to notice that these two simulations are performed separately.

With a multi-core computer architecture, the electrical simulation task can be carried out in parallel in different cores, since each specification has an independent test bench. The UCAF implementation is capable of using all cores simultaneously to simulate the circuit, resulting in a relevant reduction in the overall processing time.

5 Automatic Design of a Two-Stage Amplifier

To illustrate the application of the optimization procedure described above, we performed the automatic design of a two-stage CMOS Miller operational transconductance amplifier (OTA). The schematics of this amplifier is shown in Fig. 2.14. It is composed of an input differential amplifier as first amplification stage and by an inverter amplifier in the second stage. A compensation capacitor ($C_{c}$) is connected between stages for stability purposes [2].

Fig. 2.14

Schematics of a two-stage Miller amplifier

This design has the following user specifications as input constraints: low-frequency gain (Avo), gain–bandwidth product (GBW), phase margin (PM), slew rate (SR), common-mode input range (ICMR), and output swing (OS). The current mirrors and the differential pair result in the following matched transistors: $M_{1} = M_{2}$, $M_{3} = M_{4}$ and $M_{5} = M_{8}$. Designing this circuit requires calculating all CMOS gate sizes ($W$ and $L$), the bias current source ($I_{B}$), and the compensation capacitor ($C_{c}$), resulting in the following 12 free variables: $W_{1}$, $L_{1}$, $W_{3}$, $L_{3}$, $W_{5}$, $L_{5}$, $W_{6}$, $L_{6}$, $W_{7}$, $L_{7}$, $I_{B}$, and $C_{c}$.

The target fabrication technology is XFAB 0.18 μm, which defines the minimal values of transistor sizes: L _min = 0.18 μm and W _min = 0.22 μm, with a grid ($\lambda$) of 0.01 μm. The variable bounds are shown in Table 2.2. The design space has $12$ dimensions and $2.76 \times 10^{40}$ possible solutions, and thus, cannot be exhaustively explored with current ordinary computational resources.

Table 2.2 Upper and lower bounds for the free values in the design of a Miller OTA

The UCAF tool was set to use genetic algorithms with 100 binary individuals, simple mutation, simple crossover, and roulette wheel selection function. The stop criterion is the execution of 1000 generations, and the initial solution is randomly generated. The cost function has power dissipation and gate area as design objectives, and the remaining user specifications are the constraints. The required values of the specifications are shown in the second column of Table 2.3.

Table 2.3 Design specifications and results for the Miller amplifier

The tool was executed in an Intel i7 processor with 8 GB of main memory. Three different configurations were executed. The performance results are shown in the third to fifth columns of Table 2.3, and device sizes are presented in Table 2.4.

Table 2.4 Generated solutions for the Miller amplifier designs

The Automatic Design 1 was performed by UCAF without yield analysis in the optimization procedure. This execution spent 43.55 min, and the final result satisfied all constraints. The resulting power and area are equal to 25.82 μW and 16.88 μm², respectively. Comparing with the designs presented by Jafari et al. [19] and Liu et al. [21] for the same circuit, the values obtained by UCAF achieve a considerable reduction in area and dissipated power.

To estimate yield of Automatic Design 1, we executed a Monte Carlo simulation with 2000 samples. The resultant yield was 25.62 %, which is a very low productivity index since approximately 3 of 4 of the fabricated circuits will not satisfy the required specifications. This low yield was expected, because we did not consider it in the optimization problem. The generated solution is very close to the border of the performance space and is very sensitive to random fabrication process variations in this region. Even a small variation causes the solution to move out of the acceptable performance space. For example, the slew rate specification is proportional to the bias current $I_{B}$:

$$ {\text{SR}} = \frac{{I_{B} }}{{C_{c} }}. $$

At the same time, power dissipation depends on $I_{B}$:

$$ P_{\text{diss}} = (V_{\text{DD}} - V_{\text{SS}} ) \cdot (2 \cdot I_{B} + I_{7} ). $$

The optimization algorithm tries to satisfy the minimum SR constraint with the smallest possible $I_{B}$. This implies in reducing SR to the minimum value, moving the solution point close to the border of the performance space. When not considering yield prediction during the optimization procedure, all analog IC automatic design tools tend to generate solutions with very low yield.

The other two configurations shown in Table 2.3 include yield prediction in the optimization flow. The Automatic Design 2 was performed using MC simulation for yield prediction for best solution candidates. As formulated in Sect. 2.3, this strategy is used to reduce the number of Monte Carlo simulations. The number of MC samples was fixed in 400. The generated solution satisfied all design constraints with 92.11 % of yield. The optimization process consumed 239.05 min, which is 5.5 times slower than the process without considering yield. However, the final yield increased to a practical value.

The Automatic Design 3 was executed with the same previous configuration, but using the central limit theorem with 99 % confidence interval for determining the number of MC samples in each iteration. The resulting solution showed 100 % of predicted yield in 139.58 min of execution. With less processing time, this configuration allowed a better exploration of the design space, leading to a solution point with 100 % of yield.

The relevant increase in circuit yield in the Automatic Designs 2 and 3 is given at the expense of gate area and power dissipation. This agrees with the Pelgrom’s law [28], since the variation in the circuit performance is inversely proportional to the square root of the gate area. Another characteristic of the yield optimization results is that the distances between constraint values and reached specifications are increased. This guarantees that specifications fall inside the performance space even concerning the variations in the fabrication process.

6 Conclusion

The automatic design of a two-stage Miller amplifier including yield prediction in the optimization flow generated a robust solution with 100 % of yield within a 99 % confidence interval. All performance specifications were met, and gate area and power dissipation were minimized.

The UCAF tool uses genetic algorithms for efficiently searching the design space and produces reliable solutions, since the performance is estimated by means of electrical simulation. The tool executes Monte Carlo simulations for yield prediction, providing a realistic estimation of the performance sensitivity with respect to fabrication process variations. The computational time is reduced by executing Monte Carlo simulation only for best solution candidates and by calculating the minimum number of MC samples for a given theoretical confidence interval.

We implemented an efficient yield-oriented sizing tool that generates robust solutions, contributing for the increase in the number of first-time-right analog integrated circuit designs.

The technique described in this work addresses the optimization of a single basic analog block (a subsystem of a large analog circuit). When maximizing the yield of the whole circuit, losses might be caused by unmatched interconnections and parasitic effects might appear when integrating subsystems on the top level. Nevertheless, it is necessary to optimize the yield of each subsystem in order to achieve a maximized yield in the whole circuit.

One of the drawbacks of our approach is dealing with large circuits composed by several design variables. The computational cost rapidly increases with the number of design variables, since the design space to be explored grows exponentially. A practical strategy is to divide a large circuit into smaller parts and then size each subcircuit at a time using our proposed methodology. After that, mixed-mode simulation could be considered as an alternative to increase simulation speed for these circuits.