Abstract
In this paper a novel coarse-grained architecture virtualization for Field Programmable Gate Arrays (FPGA) is presented which can be used as basis for run-time dynamic hardware multithreading. The architecture uses on-chip networking to interconnect routers and computational elements providing a flexible and highly configurable structure. Quadratic routers are reducing total router count while ensuring short communication paths and minimal resource overhead.
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Metzner, M., Lizarraga, J.A., Bobda, C. (2015). Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays. In: Sano, K., Soudris, D., Hübner, M., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2015. Lecture Notes in Computer Science(), vol 9040. Springer, Cham. https://doi.org/10.1007/978-3-319-16214-0_14
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DOI: https://doi.org/10.1007/978-3-319-16214-0_14
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