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1 Introduction

For 40 years, microelectronics has been following the Moore’s law, stating that the density and speed of integrated circuits would double every 18 months. However, this trend is presently getting out of breath, because of incoming insurmountable physical limits. Due to decreasing devices size, leakage current is becoming the main contributor to power dissipation of CMOS. Indeed, the increased density and reduction in die size lead to heat dissipation and reliability issues. Moreover, the dynamic power keeps on growing up with both clock frequency and global capacitance while the power supply is not scaled down accordingly. Several solutions are investigated to try to push forward these limits at technology, circuit or architecture levels. The “more than Moore” concept consists in using new devices beside or in replacement of standard CMOS transistors. For instance, the use of non-volatile devices is seen as a promising solution to reduce power consumption, improve reliability and offer new functionalities. Several technologies are intensively investigated like Phase Change Random Access Memory (PCRAM), Ferroelectric RAM (FeRAM), RedoxRAM (ReRAM) and Magnetic RAM (MRAM). In its 2010 report, ITRS identified RedoxRAM and STT-MRAM as the two most promising technologies for embedded memories at technology nodes below 16 nm. The combination of non-volatility, fast access time and endurance in MRAM technology paves the path toward a universal memory. Although an expanding attention is given to two-terminal Magnetic Tunnel Junctions (MTJ) with writing based on Spin-Transfer Torque (STT) switching as the potential candidate for future memories, it suffers from weaknesses. Indeed, two main shortcomings are still limiting the reliability and endurance of STT-MRAMs: i) The high current density required for writing can occasionally damage the MTJ barrier, specially for switching on the nanosecond time scale ii) It remains a challenge to fulfill a reliable reading without ever causing switching for very advanced technology nodes, since writing and reading operations share the same path, through the junction. Indeed, the smaller the MTJ the lower the writing current without having the possibility to reduce the reading current to maintain a reliable sensing. Three-terminal MTJ with writing based on Spin-Orbit Torque (SOT) approach revitalizes the hope of an ultimate RAM. It represents a pioneering way to triumph over current two-terminal MTJ’s limitations by separating the reading and the writing paths, completely avoiding tunnel barrier damaging and read disturb issues.

2 MTJs Written by Spin Orbit Torque

Recently, a new effect was discovered, leading to original devices with three terminals. This effect is called Spin Orbit Torque (SOT), a generic term encompassing in reality different possible mechanisms originating from the bulk of the material and the interfaces between the different layers. These mechanisms issued from the spin orbit interaction are often named the Rashba effect and the Spin Hall Effect (SHE) [1–4] for the contribution of respectively the interfaces and the bulk. However this denomination is often a shortcut since the contribution from interfaces and bulk are intricated. SOT allows switching the magnetization of a magnetic Storage Layer (SL) by passing a current in the plane of the conductive contact line underneath the MTS, instead of through the MTJ itself (Fig. 1). This allows separating the reading and writing paths with great benefits: firstly, since no large writing current is passing through the tunnel barrier damaging it, the endurance can be truly infinite. Secondly, risks of accidental writing during reading are drastically reduced. Moreover, the switching duration using this scheme can be very fast, typically some hundreds of picoseconds experimentally demonstrated, providing the injection of relatively large current densities. Compared to STT [5, 6] the fast SOT-switching is deterministic and does not show any precessional behavior [7]. Today, the current density is higher than for STT (typically 5 ⋅ 107 A/cm2), but since it flows through a very thin line (typically 5 nm), the resulting writing current can be very small. Moreover, since the writing time can be very short, the resulting energy becomes very interesting. The main limitation of this technology compared to STT is apparently the area density because of the additional terminal. However, this picture is not so simple considering a complete memory since i) transistors can be shared ii) the area of MRAM is often limited by the size of the addressing transistors more than that of the single magnetic cell. However, since the writing current decreases proportionally to the lateral dimension of the device and not with its surface, the scalability is weaker than for STT writing, but remains much better than for magnetic field writing. An important feature of the device is the thermal stability of the device which is ensured down to 20 nm.

Fig. 1
figure 1

(a) Schematic of the three-terminal SOT device and the two independent paths for (b) write and (c) read operations. In-plane current injection through the write line (writing stripe) induces the perpendicular switching of the storage layer

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Another specificity of this writing scheme is that a small static longitudinal magnetic field is required to avoid stochastic switching: without it, for a given direction of the writing current, the magnetization can switch randomly in either P (Parallel) or AP (Anti Parallel) configuration. Adding this longitudinal magnetic field makes the switching deterministic, with a direction of the current writing the P state and the opposite direction the AP state. This field can be generated by the stray field of an in-plane magnetized layer, integrated to the pilar stack, acting like a permanent magnet, with no additional power consumption. This particularity can be even turned into an advantage. Indeed, if the direction of the magnetic field is switched, the operation of the device is inverted: the direction of the current previously used to write a logic “0” will write a logic “1” and vice-versa (Fig. 2). It can be useful for reconfigurable computing. In this case, the magnetization of the layer generating the magnetic field could be chosen using a current line to control it like in original Field Induced Magnetic Switching (FIMS) writing schemes. The corresponding power consumption would then depend on the reconfiguration frequency.

Fig. 2
figure 2

Switching dependence on the external longitudinal applied field Ha and current direction

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Although this technology is at very early stage development, these properties make it particularly interesting for high speed applications that do not require very high densities but high endurance. Typically, it can be suitable for low-cache levels replacement in processors, which is not possible with classical STT. Since this technology solves some of the major issues of STT, a lot of academic organisms and industrial companies are intensively working on it and we have good confidence that it can have a predominant place in the future of spintronics, for a lot of applications.

3 Applications of SOT-RAM

3.1 Introduction in the Memory Hierarchy of Processors

As seen in the previous chapters, a lot of studies have been recently carried out to introduce STT-RAM in the memory hierarchy of processors. Indeed, it is the only technology that offers an intrinsic non-volatility together with a speed suitable for use as a working memory and a quasi-infinite endurance. Adding non-volatility in the memory hierarchy has a lot of advantages, in particular the ability to ease the power gating techniques, which consist in cutting off the power supply of unused blocks to drastically reduce the leakage. Indeed, having a local non-volatility allows directly cutting off the power supply without having to save the content of the memory in distant non-volatile or very low-leakage storage devices. The first and more obvious approach consists in directly replacing the parts of the memory hierarchy whose operating speed is compatible with those of STT-RAM (DRAM main memory, or L2 cache level). Going deeper into the memory hierarchy seems difficult since STT-RAM cannot compete with fast SRAM in terms of writing speed. However, some works have shown that the better density of MRAM allows having a larger L1 cache capacity, which can compensate the loss of speed for some applications [8]. This approach requires rethinking the architecture of processors and memory hierarchy and is adapted only to some specific applications. Other works propose the use of a hybrid SRAM/MRAM memory. Several architectures have been proposed, allowing using the memory as a standard SRAM in operation, but with the capability of backing-up the content in MTJs and restore it at any moment. This allows bringing non-volatility in low levels of cache, but with a loss in terms of density.

Since SOT-MRAM have a writing speed approaching that of SRAM, it is possible to consider directly replacing L1 cache by SOT-RAM. The result would be the introduction of non-volatility in L1 cache, without penalty in terms of speed. Moreover, thanks to its density which remains much better than the one of SRAM, larger caches could be used, resulting in probable performance improvement.

3.2 Non-volatile Flip-Flops, Normally-Off/Instant-On Computing and Memory-in-Logic

The architecture of latches and Flip-Flops (FF), distributed memory containing the active data of the logic part of the circuit, is very similar to that of SRAM. It is thus possible to introduce non-volatility in the logic itself, in the same way that SRAM can be made non-volatile [9–11]. It is particularly interesting since it allows freezing the state of the processor or any digital/mixed signal IC, and restart in the same state. It allows developing new paradigms like normally-off/instant-on computing [12], in which the circuit is off by default and power supplied only when required. It can be switched-off instantaneously and restarted in the same state. This still reduces the power consumption but also improves the reliability. It is possible for instance to implement a checkpoint for rollback operation in processors, to restore the system state with a snapshot taken in the past. Thanks to its high speed, low-energy writing and infinite endurance, SOT-MRAM could allow saving the context more often, even possibly at each clock edge, without significant energy overhead or performance loss and thus still improving the reliability.

Although the intrinsic non-volatility of MTJs naturally encourages using them as memory elements, it also offers the possibility to intrinsically mix logic and memory to shorten and multiply the communication between them, leading to a new paradigm in logic architectures. This concept, called “logic-in-memory” has been proposed in [13]. Examples of circuits based on Current Mode Logic (CML) have been proposed and implemented in silicon demonstrators giving encouraging results [14]. For this purpose, the SOT-MRAM has another advantage thanks to its third terminal offering an additional degree of freedom and the possibility to reverse its behavior by changing the direction of the longitudinal magnetic field.

4 Design Tools and Environment for the Design of Hybrid CMOS/SOT-RAM Components

4.1 Compact Electrical Model of SOT-MTJ

As the semiconductor industry is progressively going toward “hybrid CMOS” Integrated Circuits (ICs), compact model development has become a cornerstone in the circuit/system design and verification tool flow.

Recently, a compact model of the SOT-MRAM has been proposed by Spintec [15]. The most significant physical phenomena involved in the writing (SOT) and the reading (TMR) are taken into account and realistic parameters, obtained from characterization of single SOT-MRAM cells [16] were used to calibrate the model. This model is written in Verilog-A language and based on physical equations modeling the behavior of the device. The dynamics of the magnetization is described, based on the Landau-Lifshitz-Gilbert (LLG) equation [17], including additional SOT terms [1–4, 16, 18]. The dependence of the resistance upon the magnetic configuration (Tunnel Magneto-Resistance or TMR, relative resistance variation of the stack between Parallel and Anti-Parallel resistance states) and the applied voltage is described using Julière’s model [19] and Simmons’ model [20]. Moreover, for an improved accuracy, we have integrated the dynamic conductance given by the Brinkman model [21] and we take into consideration the dependence of TMR upon bias voltage. In this model, all the physical quantities, such as the magnetization components (mx, my, mz) are represented by voltages. Figure 3 shows a physical view and a block diagram of the model, with two modules, one dedicated to the computation of the dynamics of the magnetization and the other dedicated to the TMR.

Fig. 3
figure 3

Modeling strategy of the three-terminal SOT-MRAM. (a) Physical view of the SOT-MRAM (cross section). (b) Block diagram of the compact model

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Figure 4 shows a simulation result using SPECTRE electrical simulator from Cadence. It illustrates the operation of the device, by showing the dynamics of the mz component of the magnetization for different values of the writing current density Japp. In this particular case, the magnetization of the two magnetic layers constituting the MTJ is oriented perpendicularly to the layers. The value of mz is then 1 for P state and −1 for AP state. Intermediate values correspond to transient behavior during the switching process. The duration of the writing pulse is 3 ns. We see that during the current pulse application the magnetization aligns in the plane of the layers (mz = 0). Once the magnetization is stabilized, the current is removed and the magnetization switches in its final state according to the direction of the current. For Japp = 1012 A/m2, the SOT is not strong enough to initiate the switching and the MTJ remains in its P state. For Japp = 2 ⋅ 1012 A/m2, the 3 ns pulse is not long enough for the magnetization to stabilize and the MTJ switches back to its initial P state. For higher values of Japp, switching occurs, with a duration decreasing with the increase of the current density, allowing a trade-off between speed and power consumption, depending on the targeted application. In the same way, increasing the pulse duration allows improving the reliability of the switching. We see that for high current density values (4 ⋅ 1012 A/m2 for instance), the switching time can be less than 1 ns. In Fig. 5, the influence of the longitudinal magnetic field on the switching is illustrated. Without it, the switching is stochastic. When the field is applied, the switching becomes deterministic, with a switching time duration decreasing with the increase of the magnitude of the field. This model was successfully validated by comparison of the results with micromagnetic simulations.

Fig. 4
figure 4

Simulation of the dynamics of the perpendicular magnetization mz of a SOT-MRAM as a function of the injected current

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Fig. 5
figure 5

Study of the dynamic behavior of the perpendicular magnetization mz according to the value of the external applied field Ha: (a) Ha = 0, random switching and (b) Ha < 0, proper switching

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4.2 Ultra-fast SOT-MRAM Based Non-volatile Flip-Flop

In order to illustrate the potential of SOT-MRAM, we describe here a Non-Volatile Flip-Flop (NVFF) architecture based on this technology (Fig. 6), developed at Spintec [22]. It is composed of a master latch made non-volatile using a pair of SOT-MRAMs (Fig. 6b) connected to a standard slave latch (Fig. 6c). The operation is managed by a non-overlapping two-phase clock signal generator (ck1, ck2). Four transistors are used to generate a bidirectional current flowing in the writing lines of the SOT-MRAMs devices in series. The direction of the current is determined by the input data D. The current is generated during the first phase clock ck1. During the second phase clock ck2, the master latch reads the data of the SOT-MRAMs and transfers it to the output Q. This operation is illustrated in Fig. 7, showing a simulation of the NVFF using the compact model presented in the previous section. In this work, the technology node is 40 nm, for both CMOS and SOT-MRAM. In these conditions, the writing current is 60 μA, comparable to perpendicular STT-MRAM. However as seen in inserts, the switching time is only 250 ps, four times faster than STT, dividing the energy by four.

Fig. 6
figure 6

SOT-MRAM based NVMFF (a) symbol, (b) master register architecture, (c) slave register, (d) writing circuit

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Fig. 7
figure 7

SOT-MRAM based NVMFF simulation results (a) write and read operations (b) perpendicular magnetization mz behavior of the SOT-MRAM during a 1 ns current pulse to switch from AP (mz = −1) to P (mz = 1) (c) SOT-MRAM witching with only a 250 ps pulse (exactly after oscillations stabilization)

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The operation of this NVFF fundamentally differs from those presented so far [9–11]: the magnetic part is written at every clock cycle contrary to the previous cases, where the data was backed up in the magnetic part only when required, on demand. This is made possible because of the high writing speed and low-power consumption of the SOT technology. It means that with such a device, the power supply can be cut-off at any moment, without further action and restarted in the same state. This opens the door to the concept of “normally-off” or “instant-on” circuits [12]. This Flip-Flop can be used as a primitive cell into the ASIC design library allowing the design of non-volatile, high speed and low-power digital circuits [23, 24].

4.3 System Level Integration

To evaluate the benefits that can be expected from integrating MRAM and in particular SOT-MRAM in the different levels of processors hierarchy, it is necessary to carry-out system level simulations, using processor simulators, like Gem5 or simple scalar (Fig. 8). These tools take as inputs the architecture of the processor, including the memory hierarchy and the models of the memory blocks. It allows running an application and evaluating the performance in terms of CPU time, number of cycles, memory transactions (read/write, cache hit/miss…). The models of the memory can be provided by characterization of an existing memory (by test or simulation) or using a memory simulator, like NVSIM tool (specific for non-volatile resistive memories). This work is currently carried out for MRAM in general [8] and for SOT-MRAM in particular, giving encouraging preliminary results [25].

Fig. 8
figure 8

System level design flow to evaluate the performance of processors embedding MRAM

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5 Conclusion

The advent of new MRAM generations has led to a keen interest in the microelectronics world for this technology as a possible solution to push forward the limits of microelectronics. Several tools are developed to allow exploring new circuits and system architectures using MRAM devices. As seen in this chapter, both STT-MRAM and SOT-MRAM technologies have their own strengths and limits and is thus suitable for a given set of applications. A wide field of investigation is open covering technology developments to improve the existing devices, discover new ones, and design of innovative circuits and systems. Two paths must be followed in parallel: identifying relevant target applications for each technology and adapting the system architectures to gain maximum benefit.

The performance of the most recent technologies and in particular SOT-MRAM, in terms of speed and power consumption which could compete with SRAM, paves the way towards a true revolution in the memory hierarchy. It allows dreaming of a new paradigm consisting in introducing non-volatility at all levels of this memory hierarchy and possibly writing the data in the MTJs at every clock cycle, opening the door to real normally-off/instant-on circuits.