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Dataflow Models of Computation for Programming Heterogeneous Multicores

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Handbook of Computer Architecture

Abstract

The hardware complexity of modern integrated circuits keeps increasing at a steady pace. Heterogeneous Multi-Processor Systems-on-Chips (MPSoCs) integrate general-purpose processing elements, domain-specific processors, dedicated hardware accelerators, reconfigurable logic, as well as complex memory hierarchies and interconnect. While offering unprecedented computational power and energy efficiency, MPSoCs are notoriously difficult to program. This chapter presents Models of Computation (MoCs) as an appealing alternative to traditional programming methodologies to harness the full capacities of modern MPSoCs. By raising the level of abstraction, MoCs make it possible to specify complex systems with little knowledge of the target architecture. The properties of MoCs make it possible for tools to automatically generate efficient implementations for heterogeneous MPSoCs, relieving developers from time-consuming manual exploration. This chapter focuses on a specific MoC family called dataflow MoCs. Dataflow MoCs represent systems as graphs of computational entities and communication channels. This graph-based system specification enables intuitive description of parallelism and supports many analysis and optimization techniques for deriving safe and highly efficient implementations on MPSoCs.

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References

  • Alur R, Courcoubetis C, Dill D (1990) Model-checking for real-time systems. In: [1990] Proceedings. Fifth annual IEEE symposium on logic in computer science. IEEE, pp 414–425

    Google Scholar 

  • Arrestier F, Desnos K, Juarez E, Menard D (2019) Numerical representation of directed acyclic graphs for efficient dataflow embedded resource allocation. ACM Trans Embed Comput Syst 18(5s). ISSN: 1539-9087. https://doi.org/10.1145/3358225

  • Bebelis V, Fradet P, Girault A, Lavigueur B (2013) BPDF: a statically analyzable dataflow model with integer and boolean parameters. In: 2013 proceedings of the international conference on embedded software (EMSOFT). IEEE, pp 1–10

    Google Scholar 

  • Bhattacharya B, Bhattacharyya SS (2001) Parameterized dataflow modeling for DSP systems. IEEE Trans Sig Process 49(10):2408–2421

    Article  MathSciNet  MATH  Google Scholar 

  • Bhattacharyya SS, Brebner G, Janneck JW, Eker J, Von Platen C, Mattavelli M, Raulet M (2009) OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems. ACM SIGARCH Comput Archit News 36(5):29–35

    Article  Google Scholar 

  • Bilsen G, Engels M, Lauwereins R, Peperstraete J (1996) Cycle-static dataflow. IEEE Trans Sig Process 44(2):397–408

    Article  Google Scholar 

  • Biscondi E, Flanagan T, Fruth F, Lin Z, Moerman F (2012) Maxi-mizing multicore efficiency with navigator runtime, White Paper. www.ti.com/lit/wp/spry190/spry190.pdf

    Google Scholar 

  • Bouakaz A, Talpin J-P, Vitek J (2012) Affine data-flow graphs for the synthesis of hard real-time applications. In: 2012 12th international conference on application of concurrency to system design. IEEE, pp 183–192

    Google Scholar 

  • Brunet SC (2015) Analysis and optimization of dynamic dataflow programs. PhD thesis, Ecole Polytechnique Federale de Lausanne (EPFL)

    Google Scholar 

  • Brunet SC, Alberti C, Mattavelli M, Janneck J (2013) Turnus: a unified dataflow design space exploration framework for heterogeneous parallel systems. In: 2013 conference on design and architectures for signal and image processing (DASIP), pp 47–54

    Google Scholar 

  • Buck JT (1993) Scheduling dynamic dataflow graphs with bounded memory using the token flow model. PhD thesis, EECS Department, University of California, Berkeley. http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2429.html

  • Castrillon J, Leupers R (2014) Programming heterogeneous MPSoCs: tool flows to close the software productivity gap. Springer, p 258. ISBN: 978-3-319-00675-8. https://doi.org/10.1007/978-3-319-00675-8

    Book  Google Scholar 

  • Castrillon J, Velásquez R, Stulova A, Sheng W, Ceng J et al (2010) Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. In: Proceedings of the conference on design, automation and test in Europe DATE’10. European Design and Automation Association, Dresden, pp 753–758. ISBN: 978-3-9810801-6-2. http://dl.acm.org/citation.cfm?id=1870926.1871107

    Chapter  Google Scholar 

  • Castrillon J, Schürmans S, Stulova A, Sheng W, Kempf T et al (2011) Component-based waveform development: the nucleus tool flow for efficient and portable software defined radio. Analog Integr Circuits Sig Process 69(2–3):173–190. ISSN: 0925-1030. https://doi.org/10.1007/s10470-011-9670-1

  • Castrillon J, Tretter A, Leupers R, Ascheid G (2012) Communication-aware mapping of KPN applications onto heterogeneous MPSoCs. In: Proceedings of the 49th annual design automation conference DAC’12. ACM, San Francisco, pp 1266–1271. ISBN: 978-1-4503-1199-1. https://doi.org/10.1145/2228360.2228597

    Chapter  Google Scholar 

  • Castrillon J, Leupers R, Ascheid G (2013) MAPS: mapping concurrent dataflow applications to heterogeneous MPSoCs. IEEE Trans Ind Inform 9(1):527–545. ISSN: 1551-3203. https://doi.org/10.1109/TII.2011.2173941

  • Castrillon J, Lieber M, Klüppelholz S, Völp M, Asmussen N et al (2018) A hardware/software stack for heterogeneous systems. IEEE Trans Multi-Scale Comput Syst 4(3):243–259. ISSN: 2332-7766. https://doi.org/10.1109/TMSCS.2017.2771750. http://ieeexplore.ieee.org/document/8103042/

  • C/DA Design Automation (2020) IEEE standard for software-hardware interface for multi- many-core. In: IEEE Std 2804-2019, pp 1–84. https://doi.org/10.1109/IEEESTD.2020.8985663. https://standards.ieee.org/standard/28042019.html

  • Ceng J, Castrillon J, Sheng W, Scharwächter H, Leupers R et al (2008) MAPS: an integrated framework for MPSoC application parallelization. In: Proceedings of the 45th annual design automation conference DAC’08. ACM, Anaheim, pp 754–759. ISBN: 978-1-60558-115-6. https://doi.org/10.1145/1391469.1391663

    Chapter  Google Scholar 

  • Ceng J, Sheng W, Castrillon J, Stulova A, Leupers R, Ascheid G, Meyr H (2009) A high-level virtual platform for early MPSoC software development. In: Proceedings of the 7th IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS’09). ACM, Grenoble, pp 11–20. ISBN: 978-1-60558-628-1. http://doi.org/10.1145/1629435.1629438

    Chapter  Google Scholar 

  • Church A (1985) The calculi of lambda-conversion, vol 6. Princeton University Press, Princeton

    Book  MATH  Google Scholar 

  • Dardaillon M, Marquet K, Risset T, Martin J, Charles H-P (2016) A new compilation flow for software-defined radio applications on hetero-geneous MPSoCs. ACM Trans Archit Code Optim (TACO) 13(2):1–25

    Article  Google Scholar 

  • de Dinechin BD (2013) Dataflow language compilation for a single chip massively parallel processor. In: 2013 IEEE 6th international workshop on multi-/many-core computing systems (MuCoCoS). IEEE. pp 1–1

    Google Scholar 

  • de Dinechin BD (2015) Kalray MPPA®: massively parallel processor array: revisiting DSP acceleration with the Kalray MPPA manycore processor. In: 2015 IEEE hot chips 27 symposium (HCS). IEEE, pp 1–27

    Google Scholar 

  • Dennis JB (1974) First version of a data flow procedure language. In: Robinet B (ed) Programming symposium. Springer, Berlin/Heidelberg, pp 362–376. ISBN: 978-3-540-37819-8

    Chapter  Google Scholar 

  • Deroui H, Desnos K, Nezan J-F, Munier-Kordon A (2017) Relaxed subgraph execution model for the throughput evaluation of IBSDF graphs. In: 2017 international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS). IEEE, pp 213–220

    Google Scholar 

  • Desnos K, Pelcat M, Nezan J-F, Bhattacharyya SS, Aridhi S (2013) Pimm: parameterized and interfaced dataflow meta-model for mpsocs runtime reconfiguration. In: 2013 international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS). IEEE, pp 41–48

    Google Scholar 

  • Desnos K, Pelcat M, Nezan J-F, Aridhi S (2015) Memory analysis and optimized allocation of dataflow applications on shared-memory MPSoCs. J Sig Process Syst 80(1):19–37

    Article  Google Scholar 

  • Desnos K, Pelcat M, Nezan J-F, Aridhi S (2016) Distributed memory allocation technique for synchronous dataflow graphs. In: 2016 IEEE international workshop on signal processing systems (SiPS). IEEE, pp 45–50

    Google Scholar 

  • Dick R (2008) Embedded Systems Synthesis Benchmark Suite (e3s). http://ziyang.eecs.umich.edu/%5C~%7B%7Ddickrp/e3s/

  • Ecker W, Müller W, Dömer R (2009) Hardware-dependent software. Springer, Dordrecht, pp 1–13

    Google Scholar 

  • Eker J, Janneck J (2003) CAL language report Technical report, ERL Technical Memo UCB/ERL, Springer Netherlands

    Google Scholar 

  • Erbas C, Cerav-Erbas S, Pimentel AD (2006) Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design. IEEE Trans Evol Comput 10(3):358–374

    Article  Google Scholar 

  • Eusse JF, Williams C, Leupers R (2014) CoEx: a novel profiling-based algorithm/architecture co-exploration for ASIP design. ACM Trans Reconfig Technol Syst. https://doi.org/10.1109/ReCoSoC.2013.6581520

  • Fettweis G, Dörpinghaus M, Castrillon J, Kumar A, Baier C et al (2019) Architecture and advanced electronics pathways towards highly adaptive energy-efficient computing. Proc IEEE 107(1):204–231. ISSN: 0018-9219. https://doi.org/10.1109/JPROC20182874895. https://ieeexplore.ieee.org/document/8565890

  • Fradet P, Girault A, Krishnaswamy R, Nicollin X, Shafiei A (2018) RDF: Reconfigurable Dataflow (extended version), Technical report INRIA Grenoble-Rhône- Alpes

    Google Scholar 

  • Gao L, Huang J, Ceng J, Leupers R, Ascheid G, Meyr H (2009) TotalProf: a fast and accurate retargetable source code profiler. In: CODES+ISSS’09: proceedings of the 7th IEEE/ACM international conference on hardware/software codesign and system synthesis. ACM, Grenoble, pp 305–314. ISBN: 978-1-60558-628-1. https://doi.org/10.1145/1629435.1629477

    Chapter  Google Scholar 

  • Georgiou K, Kerrison S, Chamski Z, Eder K (2017) Energy transparency for deeply embedded programs. ACM Trans Archit Code Optim (TACO) 14(1):1–26

    Article  Google Scholar 

  • Gerstlauer A, Haubelt C, Pimentel AD, Stefanov TP, Gajski DD, Teich J (2009) Electronic system-level synthesis methodologies. IEEE Trans Comput-Aided Des Integr Circuits Syst 28(10):1517–1530

    Article  Google Scholar 

  • Ghasemi A, Cataldo R, Diguet J-P, Martin KJM (2021) On cache limits for dataflow applications and related efficient memory management strategies. In: Workshop on design and architectures for signal and image processing, 14th edn., pp 68–76

    Google Scholar 

  • Gleim U, Levy M (2013) MTAPI: parallel programming for embedded multicore systems. In: The multicore association

    Google Scholar 

  • Glover F (1989) Tabu search—part I. ORSA J Comput 1(3):190–206

    Article  MATH  Google Scholar 

  • Goens A, Khasanov R, Castrillon J, Polstra S, Pi-mentel A (2016) Why comparing system-level MPSoC mapping approaches is difficult: a case study. In: Proceedings of the IEEE 10th international symposium on embedded multicore/many-core systems-on-chip (MCSoC-16), Ecole Centrale de Lyon, Lyon, pp 281–288. https://doi.org/10.1109/MCSoC.2016.48

    Google Scholar 

  • Goens A, Khasanov R, Hähnel M, Smejkal T, Härtig H, Castrillon J (2017a) TETRiS: a multi-application run-time system for predictable execution of static mappings. In: Proceedings of the 20th international workshop on software and compilers for embedded systems (SCOPES’17). ACM, Sankt Goar, pp 11–20. ISBN: 978-1-4503-5039-6. https://doi.org/10.1145/3078659.3078663

    Chapter  Google Scholar 

  • Goens A, Siccha S, Castrillon J (2017b) Symmetry in software synthesis. ACM Trans Archit Code Optim (TACO) 14(2):20:1–20:26. ISSN: 1544-3566. https://doi.org/10.1145/3095747

  • Goubier T, Sirdey R, Louise S, David V (2011) ΣC: a programming model and language for embedded manycores. In: International conference on algorithms and architectures for parallel processing Springer, pp 385–394

    Google Scholar 

  • Hascoët J, Desnos K, Nezan J-F, de Dinechin BD (2017) Hierarchical dataflow model for efficient programming of clustered manycore processors. In: 2017 IEEE 28th international conference on application-specific systems, architectures and processors (ASAP). IEEE, pp 137–142

    Google Scholar 

  • Hautala I, Boutellier J, Nyländen T, Silvén O (2018) Toward efficient execution of RVC-CAL dataflow programs on multicore platforms. J Sig Process Syst 90:1507–1517. ISSN: 1939-8018. https://doi.org/10.1007/s11265018-1339-x

  • Heulot J, Boutellier J, Pelcat M, Nezan J-F, Aridhi S (2013) Applying the adaptive hybrid flow-shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processors. In: 2013 NASA/ESA conference on adaptive hardware and systems (AHS-2013). IEEE, pp 123–129

    Google Scholar 

  • Heulot J, Pelcat M, Desnos K, Nezan J-F, Aridhi S (2014) Spider: a synchronous parameterized and interfaced dataflow-based RTOS for multicore DSPs. In: 2014 6th European embedded design in education and research conference (EDERC). IEEE, pp 167–171

    Google Scholar 

  • Heulot J, Pelcat M, Nezan J, Oliva Y, Aridhi S, Bhattacharyya SS (2014) Just-in-time scheduling techniques for multicore signal processing systems. In: 2014 IEEE global conference on signal and information processing (GlobalSIP), pp 25–29. https://doi.org/10.1109/GlobalSIP.2014.7032071

  • Holmbacka S, Nogues E, Pelcat M, Lafond S, Lilius J (2014) Energy efficiency and performance management of parallel dataflow applications. In: Proceedings of the 2014 conference on design and architectures for signal and image processing. IEEE, pp 1–8

    Google Scholar 

  • Honorat A, Desnos K, Dardaillon M, Nezan J-F (2020) A fast heuristic to pipeline SDF graphs. In: Orailoglu A, Jung M, Reichenbach M (eds) Embedded computer systems: architectures, modeling, and simulation. Springer International Publishing, Cham, pp 139–151. ISBN: 978-3-030-60939-9

    Chapter  Google Scholar 

  • Huang K, Haid W, Bacivarov I, Keller M, Thiele L (2012) Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications. In: ACM Trans Embed Comput Syst (TECS)

    Google Scholar 

  • Jantsch A (2003) Modeling embedded systems and SoC’s: concurrency and time in models of computation. Elsevier, Morgan Kaufmann, San Francisco

    Google Scholar 

  • Kahn G (1974) The semantics of a simple language for parallel programming. Inf Process 74:471–475

    MathSciNet  MATH  Google Scholar 

  • Kahn G, MacQueen D (1976) Coroutines and networks of parallel processes

    Google Scholar 

  • Kalray Inc (2020) Kalray MPPA3 Coolidge Anouncement. https://www.kalrayinc.com/release-of-third-generation-mppa-processor-coolidge/

  • Keinert J, Haubelt C, Teich J (2005) Windowed synchronous data flow. Depart Comput Sci 12:28–49

    Google Scholar 

  • Kelly JL, Lochbaum C, Vyssotsky VA (1961) A block diagram compiler. Bell Syst Tech J 40(3):669–678

    Article  Google Scholar 

  • Khasanov R, Castrillon J (2020) Energy-efficient runtime resource management for adaptable multi-application mapping. In: Proceedings of the 2020 design, automation and test in Europe conference (DATE). DATE’20. EDA Consortium, Grenoble

    Google Scholar 

  • Khasanov R, Robledo J, Menard C, Goens A, Castrillon J (2021) Domain-specific hybrid mapping for energy-efficient baseband processing in wireless networks. ACM Trans Embed Comput Syst (TECS), special issue of the 2021 international conference on compilers, architecture, and synthesis of embedded systems (CASES) 20(5s). ISSN: 1539-9087. https://doi.org/10.1145/3476991

  • Kienhuis B, Deprettere EF, Van der Wolf P, Vissers K (2001) A methodology to design programmable embedded systems. In: International workshop on embedded computer systems. Springer, pp 18–37

    MATH  Google Scholar 

  • Kirkpatrick S, Gelatt CD, Vecchi MP (1983) Optimization by simulated annealing. Science 220(4598):671–680

    Article  MathSciNet  MATH  Google Scholar 

  • Klikpo EC, Khatib J, Munier-Kordon A (2016) Modeling multi-periodic simulink systems by synchronous dataflow graphs. In: 2016 IEEE real-time and embedded technology and applications symposium (RTAS). IEEE, pp 1–10

    Google Scholar 

  • Koliogeorgi K, Voss N, Fytraki S, Xydis S, Gaydadjiev G, Soudris D (2019) Dataflow acceleration of smith-waterman with traceback for high throughput next generation sequencing. In: 2019 29th international conference on field programmable logic and applications (FPL). IEEE, pp 74–80

    Google Scholar 

  • Kwok Y-K, Ahmad I (1999) Static scheduling algorithms for allocating directed task graphs to multiprocessors. ACM Comput Surv 31(4):406–471. ISSN: 0360-0300. http://doi.org/10.1145/344588.344618

  • Lee EA (2006) The problem with threads. Computer 39(5):33–4

    Article  Google Scholar 

  • Lee EA, Ha S (1989) Scheduling strategies for multiprocessor real-time DSP. In: 1989 IEEE global telecommunications conference and exhibition ‘communications technology for the 1990s and beyond’. IEEE, pp 1279–1283

    Google Scholar 

  • Lee EA, Messerschmitt DG (1987) Synchronous data flow. Proc IEEE 75(9):1235–1245

    Article  Google Scholar 

  • Lee EA, Messerschmitt DG (1987) Static scheduling of synchronous data flow programs for digital signal processing. IEEE Trans Comput 100(1):24–35

    Article  Google Scholar 

  • Lee EA, Parks TM (1995) Dataflow process networks. Proc IEEE 83(5):773–801

    Article  Google Scholar 

  • Lee EA, Seshia SA (2016) Introduction to embedded systems: a cyber-physical systems approach. MIT Press, Cambridge, MA

    MATH  Google Scholar 

  • Leroy X (2009) Formal verification of a realistic compiler. Commun ACM 52(7):107–115

    Article  Google Scholar 

  • Lesparre Y, Munier-Kordon A, Delosme J (2016) Evaluation of synchronous dataflow graph mappings onto distributed memory architectures. In: 2016 Euromicro conference on digital system design (DSD), pp 146–153. https://doi.org/10.1109/DSD.2016.52

  • Leupers R, Castrillon J (2010) MPSoC programming using the MAPS compiler. In: Proceedings of the design automation conference (ASP-DAC), 2010 15th Asia and South Pacific, pp 897–902. https://doi.org/10.1109/ASPDAC.2010.5419677

  • Leupers R, Aguilar MA, Eusse JF, Castrillon J, Sheng W (2017) MAPS: a software development environment for embedded multicore applications. In: Ha S, Teich J (eds) Handbook of hardware/software codesign. Springer, Dordrecht, pp 1–33. ISBN: 978-94-017-7358-4. https://doi.org/10.1007/978-94-017-7358-4_2-1

    Google Scholar 

  • Lin S, Wang L-H, Vosoughi A, Cavallaro JR, Juntti M et al (2015) Parameterized sets of dataflow modes and their application to implementation of cognitive radio systems. J Sig Process Syst 80(1):3–18

    Article  Google Scholar 

  • Lohstroh M, Romero ÍÍ, Goens A, Derler P, Castrillon J, Lee EA, Sangiovanni-Vincentelli A (2020) Reactors: a deterministic model for composable reactive systems. In: Chamberlain R, Grimheden ME, Taha W (eds) Cyber physical systems. Model-based design – proceedings of the 9th workshop on design, modeling and evaluation of cyber physical systems (CyPhy 2019) and the workshop on embedded and cyber-physical systems education (WESE 2019). Springer International Publishing, New York City, pp 59–85. ISBN: 978-3-030-41131-2. https://doi.org/10.1007/978-3-030-41131-2_4

  • Madronal D, Arrestier F, Sancho J, Morvan A, Lazcano R et al (2019) Papify: automatic instrumentation and monitoring of dynamic dataflow applications based on papi. IEEE Access 7:111801–111812

    Article  Google Scholar 

  • Manolache S, Eles P, Peng Z (2008) Task mapping and priority assignment for soft real-time applications under deadline miss ratio constraints. ACM Trans Embed Comput Syst (TECS) 7(2):1–35

    Article  Google Scholar 

  • Marwedel P, Bacivarov I, Lee C, Teich J, Thiele L et al (2011) Mapping of applications to MPSoCs. In: Proceedings of the 9th international conference on hardware/software codesign and system synthesis (CODES+ ISSS),Springer, New York, NY, pp 109–118

    Google Scholar 

  • Menard C, Goens A, Lohstroh M, Castrillon J (2020) Achieving determinism in adaptive AUTOSAR. In: Proceedings of the 2020 design, automation and test in Europe conference (DATE), DATE’20. EDA Consortium, Grenoble

    Google Scholar 

  • Menard C, Goens A, Hempel G, Khasanov R, Robledo J, Teweleitt F, Castrillon J (2021) Mocasin—rapid prototyping of rapid prototyping tools: a framework for exploring new approaches in mapping software to heterogeneous multi-cores. In: DroneSE and RAPIDO 2021, system engineering for constrained embedded systems RAPIDO’21. Virtual event. https://doi.org/10.1145/3444950.344728

  • Mendis C, Renda A, Amarasinghe S, Carbin M (2019) Ithemal: accurate, portable and fast basic block throughput estimation using deep neural networks. In: International conference on machine learning. PMLR, pp 4505–4515

    Google Scholar 

  • Meneses-Viveros A, Paredes-López M, Hernández-Rubio E, Gitler I (2021) Energy consumption model in multicore architectures with variable frequency. J Supercomput 77:2458–2485

    Article  Google Scholar 

  • Neuendorffer S, Lee EA (2004) Hierarchical reconfiguration of dataflow models. In: MEMOCODE. https://doi.org/10.1109/MEMCOD.2004.1459852

    Book  Google Scholar 

  • Orsila H, Kangas T, Salminen E, Hämäläinen TD, Hännikäi-nen M (2007) Automated memory-aware application distribution for multi-processor system-on-chips. J Syst Arch 53(11):795–815

    Article  Google Scholar 

  • Pelcat M, Menuet P, Aridhi S, Nezan J-F (2009) Scalable compile-time scheduler for multi-core architectures. In: 2009 design, automation & test in Europe conference & exhibition. IEEE, pp 1552–1555

    Google Scholar 

  • Pelcat M, Nezan JF, Piat J, Croizer J, Aridhi S (2009) A system-level architecture model for rapid prototyping of heterogeneous multicore embedded systems. In: Conference on design and architectures for signal and image processing (DASIP) 2009, Nice, 8pp. https://hal.archives-ouvertes.fr/hal00429397

  • Pelcat M, Desnos K, Heulot J, Guy C, Nezan J-F, Aridhi S (2014) Preesm: a dataflow-based rapid prototyping framework for simplifying multicore DSP programming. In: 2014 6th European embedded design in education and research conference (EDERC). IEEE, pp 36–40

    Google Scholar 

  • Pelcat M, Desnos K, Maggiani L, Liu Y, Heulot J, Nezan J, Bhattacharyya SS (2016) Models of architecture: reproducible efficiency evaluation for signal processing systems. In: 2016 IEEE international workshop on signal processing systems (SiPS), pp 121–126. https://doi.org/10.1109/SiPS.2016.29

  • Pelcat M, Mercat A, Desnos K, Maggiani L, Liu Y et al (2018) Reproducible evaluation of system efficiency with a model of architecture: from theory to practice. IEEE Trans Comput-Aided Des Integr Circuits Syst 37(10):2050–2063. https://doi.org/10.1109/TCAD.2017.2774822

    Article  Google Scholar 

  • Pellegrini A, Stephens N, Bruce M, Ishii Y, Pusdesris J et al (2020) The arm neoverse N1 platform: building blocks for the next-gen cloud-to-edge in-frastructure SoC. IEEE Micro 40(2):53–62

    Article  Google Scholar 

  • Piat J, Bhattacharyya SS, Raulet M (2009) Interface-based hierarchy for synchronous data-flow graphs. In: 2009 IEEE workshop on signal processing systems, pp 145–150. https://doi.org/10.1109/SIPS.2009.5336240

  • Pimentel AD, Erbas C, Polstra S (2006) A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Trans Comput 55(2):99–112. ISSN: 0018-9340. https://doi.org/10.1109/TC.2006.16

  • Pino JL, Bhattacharyya SS, Lee EA (1996) A hierarchical multiprocessor scheduling system for DSP applications. In: Conference record of the twenty-ninth asilomar conference on signals, systems and computers, vol 1. IEEE, pp 122–126

    Google Scholar 

  • Piscitelli R, Pimentel AD (2011) A high-level power model for mpsoc on FPGA. In: 2011 IEEE international symposium on parallel and distributed processing workshops and Phd forum. IEEE, pp 128–135

    Google Scholar 

  • Ptolemaeus C (ed) (2014) System design, modeling, and simulation using ptolemy II. Ptolemy.org. http://ptolemy.org/books/Systems

  • Quan W, Pimentel AD (2015) A hybrid task mapping algorithm for heterogeneous MPSoCs. ACM Trans Embed Comput Syst (TECS) 14(1):14

    Google Scholar 

  • Rogers P, Fellow A (2013) Heterogeneous system architecture overview. In: Hot chips symposium, pp 1–41

    Google Scholar 

  • Schuermans S, Leupers R (2019) Power estimation on electronic system level using linear power models. Springer, Cham

    Book  Google Scholar 

  • Schwarzer T, Weichslgartner A, Glaß M, Wildermann S, Brand P, Teich J (2017) Symmetry-eliminating design space exploration for hybrid application mapping on many-core architectures. IEEE Trans Comput-Aided Des Integr Circuits Syst 37(2):297–310

    Article  Google Scholar 

  • Sérot J (2020) HoCL: high level specification of dataflow graphs. In: Proceedings of the 32nd international symposium on implementation and application of functional languages (IFL 2020) University of Kent, pp 244–253. https://www.cs.kent.ac.uk/events/2020/ifl20/ifl2020draftproceedings.pdf

  • Singh AK, Kumar A, Srikanthan T (2011) A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs. In: 2011 proceedings of the 14th international conference on compilers, architectures and synthesis for embedded systems (CASES). IEEE, pp 175–184

    Google Scholar 

  • Stemmer R, Vu H-D, Grüttner K, Le Nours S, Nebel W, Pillement S (2020) Towards probabilistic timing analysis for SDFGs on tile based heterogeneous MPSoCs

    Google Scholar 

  • Stuijk S, Geilen M, Theelen B, Basten T (2011) Scenario-aware dataflow: modeling, analysis and implementation of dynamic applications. In: 2011 international conference on embedded computer systems: architectures, modeling and simulation. IEEE, pp 404–411

    Google Scholar 

  • Synopsys Signal Processing WorkSystem (SPW) (2013) The Fastest Path from Innovation to Implementation of Digital Signal Processing Systems. http://www.eigen.in/pdf/SPW.pdf

  • Synopsys System Studio (2010) https://news.synopsys.com/index.php?s=20295&item=123136

  • Teich J, Henkel J, Herkersdorf A, Schmitt-Landsiedel D, Schröder-Preikschat W, Snelting G (2011) Invasive computing: an overview. In: Multiprocessor system-on-chip. Springer, New York, NY, pp 241–268

    Chapter  Google Scholar 

  • The Multicore Association, Inc (2015) Software-hardware interface for multi-many-core (SHIM) specification, V1.0. The Multicore Association, Inc

    Google Scholar 

  • Thiele L, Chakraborty S, Naedele M (2000) Real-time calculus for scheduling hard real-time systems. In: 2000 IEEE international symposium on circuits and systems (ISCAS), vol 4. IEEE, pp 101–104

    Google Scholar 

  • Thiele L, Bacivarov I, Haid W, Huang K (2007) Mapping applications to tiled multiprocessor embedded systems. In: ACSD’07: proceedings of the seventh international conference on application of concurrency to system design. IEEE Computer Society, Washington, DC, pp 29–40. ISBN: 0-7695-2902-X. https://doi.org/10.1109/ACSD.2007.53

    Chapter  Google Scholar 

  • Tretter A (2018) On efficient data exchange in multicore architectures. PhD thesis. ETH Zurich, 206pp. https://www.research-collection.ethz.ch/handle/20.500.11850/309314

  • Van Stralen P, Pimentel AD (2010) A high-level microprocessor power modeling technique based on event signatures. J Sig Process Syst 60(2):239–250

    Article  Google Scholar 

  • Van Stralen P, Pimentel AD (2010) A trace-based scenario database for high-level simulation of multimedia MPSoCs. In: 2010 international conference on embedded computer systems: architectures, modeling and simulation. IEEE, pp 11–19

    Google Scholar 

  • Weichslgartner A, Wildermann S, Gangadharan D, Glaß M, Teich J (2018) A design-time/run-time application mapping methodology for predictable execution time in MPSoCs. ACM Trans Embed Comput Syst (TECS) 17(5):89

    Google Scholar 

  • Wilhelm R, Engblom J, Ermedahl A, Holsti N, Thesing S et al (2008) The worst-case execution-time problem—overview of methods and survey of tools. ACM Trans Embed Comput Syst 7(3):1–53. ISSN: 1539-9087. https://doi.org/10.1145/1347375.1347389

  • Yviquel H, Lorence A, Jerbi K, Cocherel G, Sanchez A, Raulet M (2013) Orcc: Multi-media development made easy. In: Proceedings of the 21st ACM international conference on multimedia MM’13. ACM, Barcelona, pp 863–866. ISBN: 978-1-4503-2404-5. https://doi.org/10.1145/2502081.2502231

    Chapter  Google Scholar 

  • Yviquel H, Sanchez A, Mickaël R, Casseau E (2017) Multi-core runtime for dynamic dataflow video decoders, Technical Report. IETR/INSA Rennes, IRISA, Inria Rennes. https://hal.archives-ouvertes.fr/hal-01503378

    Google Scholar 

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Acknowledgements

This work was funded in part by the German Federal Ministry of Education and Research (BMBF) through the E4C project (16ME0426K), by the BMBF project 6G-life hub (16KISK001K), by the German Research Foundation (DFG) through TraceSymm (366764507), by the Studienstiftung des Deutschen Volkes, by the CERBERO (Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments) Horizon 2020 Project, by the European Union Commission under Grant 732105, and by the French Agence Nationale de la Recherche under grant ANR-20-CE46-0001 (DARK-ERA project).

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Authors and Affiliations

  1. Chair for Compiler Construction, TU Dresden, Dresden, Germany

    Jeronimo Castrillon & Christian Menard

  2. Univ Rennes, INSA Rennes, CNRS, IETR-UMR6164, Rennes, France

    Karol Desnos

  3. School of Informatics, The University of Edinburgh, Edinburgh, UK

    Andrés Goens

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  1. Jeronimo Castrillon
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  2. Karol Desnos
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  3. Andrés Goens
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  4. Christian Menard
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Correspondence to Jeronimo Castrillon .

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Editors and Affiliations

  1. Sch of Computer Science & Engineering, Nanyang Technological University, Singapore, Singapore

    Anupam Chattopadhyay

Section Editor information

  1. Chair for Compiler Construction, TU Dresden, Dresden, Germany

    Jeronimo Castrillon

  2. Pleasanton, CA, USA

    Grant Martin M.Math

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Castrillon, J., Desnos, K., Goens, A., Menard, C. (2023). Dataflow Models of Computation for Programming Heterogeneous Multicores. In: Chattopadhyay, A. (eds) Handbook of Computer Architecture. Springer, Singapore. https://doi.org/10.1007/978-981-15-6401-7_45-2

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  • DOI: https://doi.org/10.1007/978-981-15-6401-7_45-2

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    Dataflow Models of Computation for Programming Heterogeneous Multicores
    Published:
    28 September 2023

    DOI: https://doi.org/10.1007/978-981-15-6401-7_45-2

  2. Original

    Dataflow Models of Computation for Programming Heterogeneous Multicores
    Published:
    28 January 2022

    DOI: https://doi.org/10.1007/978-981-15-6401-7_45-1

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