1 Introduction

To adapt to load power increases and to meet the needs of vessel propulsion, the DC voltage of the vessel integrated power system (IPS) will be upgraded to a higher voltage level in the future. Due to limitations imposed by the circuit topology and power device voltage-proof capability, the existing three-level topology cannot be applied to the higher voltage level if the power devices are not connected in series [1].

In recent years, many types of medium–high voltage converter topologies have been developed. However, they are not suitable for vessel propulsion systems due to various shortcomings. The diode-clamped multilevel converter requires many clamping diodes, which makes the capacitor voltage difficult to balance. The flying-capacitor multilevel converter needs a lot of clamping capacitors, which leads to an increase in the system cost and volume. The cascaded H-bridge converter requires a lot of independent DC power supplies or phase-shifting transformers. Thus, it becomes bulky and cannot easily fulfil energy feedback. Modular multilevel converters have attracted a great deal of attention in recent years. The overall structure of these systems is flexible and simple. However, the capacitor voltage of the submodule tends to fluctuate sharply at low frequencies. At present, there is no perfect solution. Therefore, its application is limited to vessel propulsion [2]. In 2005, Swiss scholars presented the topology of a five-level active-neutral-point-clamped-converter (5L-ANPC). Due to its advantages of being supplied by the DC bus and performing energy feedback easily, the 5L-ANPC topology has become a research hotspot in terms of medium–high voltage variable frequency speed regulation [3].

A medium–high voltage multi-phase motor with open windings can meet the requirements of large capacity, high reliability, and high torque density of vessel electric propulsion systems. A multi-phase multilevel H-bridge topology inverter that matches the motor has become an optimal option for the large-capacity propulsion systems in vessels due to its simple main circuit, good frequency-doubling effect, and high fault-tolerant capability [4]. Depending on the demand for propulsion power by a large vessel, the propulsion motor adopts the multi-phase and multi-channel open winding scheme, and the inverter can adopt a multi-phase H-bridge topology scheme based on the 5L-ANPC [5].

A great deal of research has been carried out on the 5L-ANPC inverter. In [6,7,8,9], carrier pulse width modulation methods have been used to control the 5L-ANPC inverter. These methods are simple. However, there is a coupling in the control of the neutral-point potential (NPP) and the floating capacitor voltage (FCV). When carrier PWM is applied to the 5L-ANPC H-bridge topology to double the equivalent switching frequency, the difference in the carrier phase between the right and left arms of the H-bridge is 180°, which leads to a difference between the peak and valley of the triangular carrier wave of the other arm as well as the sampling moment of the modulation wave. At this time, a narrow pulse is apt to appear, which threatens the operation of the device. In [10,11,12], SHE-PWM was used to control the 5L-ANPC. However, the calculation complexity makes it impossible to control the system in real-time. In [13], the space vector modulation algorithm was used to control a three-phase 5L-ANPC to balance the NPP and the FCV. However, due to the low switching frequency of the 5L-ANPC H-bridge inverter, this algorithm leads to large fluctuations in the capacitor voltage. Therefore, this algorithm is not applicable to the 5L-ANPC H-bridge inverter. In [14], a hybrid SVPWM modulation algorithm was proposed to reduce the control complexity when compared with the conventional 5L-SVPWM. However, it is not suitable for the 5L-ANPC H-bridge inverter. In [15], to reduce the calculation amount, an optimal model predictive control (O-MPC) method was proposed to control a 5L-ANPC converter. However, the 5L-ANPC H-bridge inverter has more output levels, which results in a larger calculation amount. This method is not suitable for the 5L-ANPC H-bridge inverter. In [16], a model predictive control was proposed to eliminate common-mode voltages (CMVs) of a three-phase 5L-ANPC converter. However, the 5L-ANPC H-bridge inverter is different from the three-phase 5L-ANPC. Thus, the method is not suitable for the 5L-ANPC H-bridge inverter. In [17,18,19], based on a detailed analysis of the traditional single-phase multilevel algorithm, the process of the single-phase SVPWM algorithm was simplified. However, this is only applicable to the multi-level topology of the two-level H-bridge cascading topology. It is not applicable to the 5L-ANPC H-bridge topology due to switching state constraints. In [20], the SVPWM algorithm was optimized on the principle of minimizing the switching times for the single-phase neutral-point clamped cascaded H-bridge inverter. However, the 5L-ANPC H-bridge inverter has more coupling floating capacitors. However, the algorithm cannot be directly used for the 5L-ANPC H-bridge inverter.

With the 5L-ANPC H-bridge inverter as an object of study, this paper proposes a space vector modulation algorithm to solve the problems of the narrow pulse in the carrier phase-shift modulation, and the coupling in the control of the NPP and the FCV. It also discusses how to select the switching vectors and how to balance the NPP and the FCV.

The remainder of this paper is organized as follows. Section 2 discusses the basic principle of the 5L-ANPC H-bridge inverter and the definitions of voltage vector and switching vector. Section 3 presents the composition of voltage vectors, the selection of switching vectors, and the control of the NPP and the FCV. Section 4 explains the algorithm. Section 5 describes real-time simulation experiments. Finally, Sect. 6 gives some conclusions.

2 5L-ANPC H-bridge inverter

A 5L-ANPC H-bridge inverter is shown in Fig. 1a. The inverter consists of two 5L-ANPC bridge arms sharing a DC bus. Both of the bridge arms are connected to one phase winding of the motor (the resistance inductance load is equivalent). For the sake of simplicity, one bridge arm is taken as an example, as shown in Fig. 1b. Suppose 4E is the DC bus voltage and NP is the neutral point of the DC supporting capacitors Cd1 and Cd2. Under ideal conditions, the voltages of Cd1 and Cd2 should be kept equal to 2E, and the voltage of Cfx(x = a,b) should be stabilized at E. It follows that the neutral-point current iNP from the NP is positive, the output current ix from the bridge is positive, the floating capacitor current iCfx from the positive pole of the floating capacitor is positive, Vxo is the output voltage, and the load current iout = ia = − ib.

Fig. 1
figure 1

Topology of a 5L-ANPC H-bridge inverter: a H-bridge; b bridge arm

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For the switches Sx1 − Sx12, 0 indicates ‘off” and 1 indicates ‘on’. Sx1, Sx3, SX5, Sx11 and Sx2, Sx4, Sx6, Sx12 are connected in series, respectively. The switching states of Sx3, Sx4, Sx6, and Sx5 are the same; the switching states of Sx1, Sx2, Sx11, and Sx12 are complementary to that of Sx5; the switching states of Sx9 and Sx8 are complementary, and the switching states of Sx10 and Sx7 are complementary. Therefore, the switching states of all the switches of the bridge arm are determined by those of Sx5, Sx7, and Sx8. Under normal operating conditions, the bridge arm has eight types of switching states, as shown in Table 1. If the NP is taken as the zero-potential reference, the five output levels corresponding to the bridge arm are: + 2E, + E, 0, − E, and − 2E.

Table 1 Switching states of 5L-ANPC bridge arms
Full size table

The switching variables Sao and Sbo are defined as the output voltage states of each bridge arm. The output voltage can be expressed as:

$$ \left\{ {\begin{array}{*{20}c} {V_{{{\text{ao}}}} = S_{{{\text{ao}}}} \cdot E} \\ {V_{{{\text{bo}}}} = S_{{{\text{bo}}}} \cdot E} \\ \end{array} } \right. $$
(1)

where Sxo = − 2, Sxo = − 1, Sxo = 0, Sxo = 1, and Sxo = 2, which represent (V0), (V1,V2), (V3,V4), (V5,V6), and (V7), respectively.

It can be seen from Fig. 2 that in different combinations (such as 04), the two elements from left to right represent the switching states of the bridge arms a and b, respectively. The voltage levels (− 2E, − E, 0, E, and 2E) are numbered as 0, 1, 2, 3, and 4, respectively. According to the above definition, 25 output voltage states of the inverter are shown in Fig. 2, which are known as the space voltage vector.

Fig. 2
figure 2

Space voltage vector diagram of a 5L-ANPC H-bridge inverter

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The voltage vector of the inverter is defined as:

$$ {\varvec{V}} = {{\varvec{V}}_{{{\text{ao}}}}} + {{\varvec{V}}_{{{\text{bo}}}}} \cdot e^{{j\pi }} $$
(2)

The maximum output voltage of the inverter is + 4E and the minimum output voltage is − 4E. The inverter can output a total of nine levels.

The switching vector xy is used to represent the switching states of the bridge arms a and b, which are Vx and Vy (x,y = 0,1,…,7), as shown in Table 2.

Table 2 Relationships between switching and voltage vectors
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Some of the switching vectors that do not meet certain conditions are eliminated according to the following principles:

  1. 1)

    The common-mode voltage of the H-bridge is defined as Vcom = (Vao + Vbo)/2. Vcom is as small as possible. The common-mode voltages of all the switching vectors are shown in Table 3. Any switching vector whose common-mode voltage is greater than E/2 is excluded.

  2. 2)

    The switchings between the switching vectors should be easy to perform. Undesirable output voltage jumps should be avoided during the switching process, and the switching times should be minimized. According to the state of the switches connected in series, V0–V7 are divided into two groups: G1{V0, V1, V2, V3} and G2{V4, V5, V6, V7}. According to these two groups, all of the switching process can be divided into two types. The first type is the switching process between G1 and G2. At this time, all of the switches connected in series and some of the non-series switches are required to act. The second type is the switching process within G1 or G2. At this time, there is only some non-series switches are required to act, and the switching loss is obviously lower. From an analysis of the switching process, it is known that when the switching states of two bridge arms belong to G1 or G2 at the same time, it is more possible for the first switching process to appear. Therefore, eight switching vectors such as G1G1 and G2G2 need to be eliminated. In addition, the first switching process only appears when the modulation wave crosses zero.

Table 3 Common-mode voltages of switching vectors
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The expected output voltage is defined as V*(n). Like three-phase SVPWM, the fundamental voltage vectors are selected according to the interval where V*(n) is located. The voltage space is divided into eight linear modulation intervals by nine fundamental voltage vectors. As shown in Fig. 3, V−4, V−3, V−2, V−1, V0, V1, V2, V3, and V4 represent − 4E, − 3E, − 2E, − E, 0, E, 2E, 3E, and 4E, respectively.

Fig. 3
figure 3

Voltage space vector divisions

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Twenty-eight effective switching vectors are listed in Table 4. V4 and V−4 correspond to only one vector. V0 corresponds to two vectors. The remaining voltage vectors correspond to four vectors.

Table 4 Effective switching vectors of a 5L-ANPC H-bridge inverter
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3 SVPWM algorithm

3.1 Composition principle of V*(n)

For the sake of a simplified analysis, V*(n) is composed of two fundamental voltage vectors.

As shown in Fig. 4, the red line indicates V*(n) < 0 and the blue line indicates V*(n) > 0. The horizontal axis is the time axis, which is divided into several control cycles. The vertical axis represents the output voltage, and Ts is the control cycle. Two adjacent fundamental voltage vectors Vlow and Vhigh can be used to compose V*(n), whose action times are T1 and T2 in turn.

Fig. 4
figure 4

Composition of two fundamental voltage vectors

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Vlow and Vhigh are defined as:

$$ \left\{ {\begin{array}{*{20}c} {V_{{{\text{low}}}} (n) = \left\{ {\begin{array}{*{20}c} {\begin{array}{*{20}c} {{\text{floor}}(V^{*} (n))} \\ {{\text{ceil}}(V^{*} (n))} \\ \end{array} } & {\begin{array}{*{20}c} {V^{*} (n) \ge 0} \\ {V^{*} (n) < 0} \\ \end{array} } \\ \end{array} } \right.} \\ {V_{{{\text{high}}}} (n) = \left\{ {\begin{array}{*{20}c} {\begin{array}{*{20}c} {{\text{ceil}}(V^{*} (n))} \\ {{\text{floor}}(V^{*} (n))} \\ \end{array} } & {\begin{array}{*{20}c} {V^{*} (n) \ge 0} \\ {V^{*} (n) < 0} \\ \end{array} } \\ \end{array} } \right.} \\ \end{array} } \right. $$
(3)

where floor is the round down function, and ceil is the round up function.

According to the ‘Volt-Second’, T1 and T2 can be calculated as follows:

$$ \left\{ {\begin{array}{*{20}c} {T_{{1}} = \left| {\frac{{V^{*} (n) - V_{{{\text{low}}}} (n)}}{{V_{{{\text{high}}}} (n) - V_{{{\text{low}}}} (n)}}} \right|T_{{\text{s}}} } \\ {T_{{2}} = \left| {\frac{{V^{*} (n) - V_{{{\text{high}}}} (n)}}{{V_{{{\text{low}}}} (n) - V_{{{\text{high}}}} (n)}}} \right|T_{{\text{s}}} } \\ \end{array} } \right. $$
(4)

The range of V*(n) is − 4E ≤ V*(n) ≤ 4E. Generally, V*(n) is composed of two fundamental voltage vectors. However, when V*(n) is equal to one of {− 4E, − 3E, − 2E, − E, 0, E, 2E, 3E, 4E}, there is no need to use two fundamental voltage vectors to compose V*(n). Only the fundamental voltage vector equal to V*(n) is used, and its action time is Ts, as shown in Fig. 5.

Fig. 5
figure 5

Single voltage vector diagram

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3.2 Balanced control of the NPP and the FCV

During the operation of the inverter, many non-ideal effects cause the capacitor voltage to deviate from its set value.

By assigning different action times to the switch vectors, NPP can be controlled. When Ts is much smaller than the fundamental period, the neutral-point current can be regarded as constant in a control cycle. At this time, the additional average neutral-point current required in a control cycle can be calculated according to the NPP deviation as follows:

$$ \overline{i}_{{{\text{NP}}}}^{{}} { = } - C_{{\text{d}}} \Delta u_{{{\text{cd}}}} {/}T = - C_{{\text{d}}} \frac{{(u_{{{\text{cd1}}}} - u_{{{\text{cd2}}}} )}}{{T_{{\text{s}}} }} $$
(5)

where Δucd is the deviation of the NPP, and Cd is the capacitance of the DC capacitors.

The control algorithm of the FCV is similar to that of the NPP. Its calculation is as follows:

$$ \overline{i}_{{{\text{cfx}}}}^{{}} { = }C_{{\text{f}}} \Delta u_{{{\text{cfx}}}} {/}T_{{\text{s}}} = C_{{\text{f}}} \frac{{(u_{{{\text{cfx}}}} - u_{{{\text{dc}}}} /4)}}{{T_{{\text{s}}} }} $$
(6)

where Δucfx is the voltage deviation of the FCV, Cf is the capacitance of the floating capacitor, and ucfx is the voltage of the floating capacitor.

3.3 Composition of the switching vectors

3.3.1 V*(n) is composed of two voltage vectors

V*(n) is composed of Vhigh and Vlow. Suppose Vhigh is composed of switching vectors Si (i = 1,2…,m). Their action time is thi (i = 1,2…,m). Suppose Vlow is composed of switching vectors Sj (j = 1,2…,n). Their action time is tlj(i = 1,2…,n).

$$ \left\{ \begin{gathered} \sum\limits_{i = 1}^{m} {t_{{{\text{h}}i}} } = T_{2} \hfill \\ \sum\limits_{i = 1}^{n} {t_{{{\text{l}}i}} } = T_{1} \hfill \\ \end{gathered} \right. $$
(7)

For each interval, the sequence of the switching vectors of V*(n) is analyzed below.

  1. (1)

    V*(n) in interval 1, 4, 5, or 8

For example, when V*(n) is located in interval 8, Vlow and Vhigh correspond to V3 and V4, respectively. Vhigh corresponds to switching vector 70 and its action time is T2. Vlow corresponds to switching vectors 50, 71, 60, and 72, and their action times are t1, t3, t5, and t7, which satisfy t1 + t3 + t5 + t7 = T1.

According to the control method of the NPP and the FCV, the equation for t1, t3, t5, and t7 is as follows:

$$ \left\{ \begin{gathered} t_{1} + t_{3} + t_{5} + t_{7} = T_{1} \hfill \\ i_{{\text{a}}} t_{1} - i_{{\text{a}}} t_{7} = - (u_{{{\text{cd1}}}} - u_{{{\text{cd2}}}} )C_{{\text{d}}} \hfill \\ - i_{{\text{a}}} t_{5} + i_{{\text{a}}} t_{1} = (u_{{{\text{cfa}}}} - u_{{{\text{dc}}}} /4)C_{{\text{f}}} \hfill \\ - i_{{\text{a}}} t_{3} + i_{{\text{a}}} t_{7} = (u_{{{\text{cfb}}}} - u_{{{\text{dc}}}} /4)C_{{\text{f}}} \hfill \\ \end{gathered} \right. $$
(8)

For simplicity:

$$ \left\{ \begin{gathered} T_{1} = t_{{\text{A}}} \hfill \\ - (u_{{{\text{cd1}}}} - u_{{{\text{cd2}}}} )C_{{\text{d}}} /i_{{\text{a}}} = t_{{\text{C}}} \hfill \\ (u_{{{\text{cfa}}}} - u_{{{\text{dc}}}} /4)C_{{\text{f}}} /i_{{\text{a}}} = t_{{\text{D}}} \hfill \\ (u_{{{\text{cfb}}}} - u_{{{\text{dc}}}} /4)C_{{\text{f}}} /i_{{\text{a}}} = t_{{\text{E}}} \hfill \\ \end{gathered} \right. $$
(9)

There are four variables t1, t3, t5, and t7 in Eq. (8), which are written as a vector equation with vector X as an unknown element:

$$ \user2{AX = b} $$
(10)

where:

$$ {\varvec{A}}{ = } \left[ {\begin{array}{*{20}c} 1 & 1 & 1 & 1 \\ 1 & 0 & 0 & { - 1} \\ 1 & 0 & { - 1} & 0 \\ 0 & { - 1} & 0 & 1 \\ \end{array} } \right]\user2{, X} = \left[ {\begin{array}{*{20}c} {t_{1} } \\ {t_{3} } \\ {t_{5} } \\ {t_{7} } \\ \end{array} } \right]\user2{, b} = \left[ {\begin{array}{*{20}c} {t_{{\text{A}}} } \\ {t_{{\text{C}}} } \\ {t_{{\text{D}}} } \\ {t_{{\text{E}}} } \\ \end{array} } \right] $$
(11)

It is found that the rank of matrix A and the augmented matrix A|b satisfy R(A) = R(A|b). Equation (10) has a unique solution, which is:

$$ \left\{ \begin{gathered} t_{1} = (t_{{\text{A}}} + 2t_{{\text{C}}} + t_{{\text{D}}} + t_{{\text{E}}} )/4 \hfill \\ t_{3} = (t_{{\text{A}}} - 2t_{{\text{C}}} + t_{{\text{D}}} - 3t_{{\text{E}}} )/4 \hfill \\ t_{5} = (t_{{\text{A}}} + 2t_{{\text{C}}} - 3t_{{\text{D}}} + t_{{\text{E}}} )/4 \hfill \\ t_{7} = (t_{{\text{A}}} - 2t_{{\text{C}}} + t_{{\text{D}}} + t_{{\text{E}}} )/4 \hfill \\ \end{gathered} \right. $$
(12)

If three or fewer switching vectors corresponding to Vlow are used, then R(A) < R(A|b). There is no solution to the vector equation, which indicates that the decoupling cannot be controlled. In order to control the decoupling, four switching vectors 50, 71, 60, and 72 must be involved in Vlow.

According to the action time of the switching vectors corresponding to Vlow and Vhigh, it is possible to derive the sequence of the switching vectors, as shown in Fig. 6. Among them, the first switching vector agrees with the last, where their action time is t1/2. Thus, it is possible to connect with the next control cycle. Switching vector 70 is divided into four pulses by 60, 50, 71, and 72. The action time of each switching vector is ti(i = 1,2,3,…,8). To make the action times of the switching vectors uniform, let t2 = t4 = t6 = t8 = tB/4. In this control cycle, the series switches of the inverter do not act, and the non-series switches turn on and off only once.

Fig. 6
figure 6

Switching vectors when V*(n) is in interval 8

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When V*(n) is located in interval 1, 4 or 5, the solution for the action time of switching vectors is similar.

  1. (2)

    V*(n) in interval 2, 3, 6, or 7

When V*(n) is located in interval 7, Vlow and Vhigh correspond to V2 and V3, respectively. Vlow corresponds to the switching vectors 52, 62, 61, and 51, and their action times are t1, t3, t5, and t7, respectively. This satisfies the formula t1 + t3 + t5 + t7 = T1. Vhigh corresponds to the switching vectors 72, 60, 71, and 50, and their action times are t2, t4, t6, and t8, respectively. This satisfies the formula t2 + t4 + t6 + t8 = T2.

According to the control method of the NPP and the FCV Eq. (13) can be obtained as follows:

$$ \left\{ \begin{gathered} t_{1} + t_{3} + t_{5} + t_{7} = t_{{\text{A}}} \hfill \\ t_{2} + t_{4} + t_{6} + t_{8} = t_{{\text{B}}} \hfill \\ - t_{3} + t_{7} + t_{8} - t_{2} = t_{{\text{C}}} \hfill \\ - t_{3} - t_{4} - t_{5} + t_{7} + t_{8} + t_{1} = t_{{\text{D}}} \hfill \\ t_{3} - t_{5} - t_{6} - t_{7} + t_{1} + t_{2} = t_{{\text{E}}} \hfill \\ \end{gathered} \right. $$
(13)

Equation (13) is turned into a vector equation with vector Y as an unknown element.

$$ \user2{CY = d} $$
(14)

where:

$$ \left\{ \begin{gathered} {\varvec{C}}{ = }\left[ {\begin{array}{*{20}l} 1 \hfill & 0 \hfill & 1 \hfill & 0 \hfill & 1 \hfill & 0 \hfill & 1 \hfill & 0 \hfill \\ 0 \hfill & 1 \hfill & 0 \hfill & 1 \hfill & 0 \hfill & 1 \hfill & 0 \hfill & 1 \hfill \\ 0 \hfill & {{ - }1} \hfill & {{ - }1} \hfill & 0 \hfill & 0 \hfill & 0 \hfill & 1 \hfill & 1 \hfill \\ 1 \hfill & 0 \hfill & {{ - }1} \hfill & {{ - }1} \hfill & {{ - }1} \hfill & 0 \hfill & 1 \hfill & 1 \hfill \\ 1 \hfill & 1 \hfill & 1 \hfill & 0 \hfill & {{ - }1} \hfill & {{ - }1} \hfill & {{ - }1} \hfill & 0 \hfill \\ \end{array} } \right] \hfill \\ {\varvec{Y}} = \left[ {\begin{array}{*{20}c} {t_{1} } \\ {t_{2} } \\ {t_{3} } \\ \begin{gathered} t_{4} \hfill \\ t_{5} \hfill \\ t_{6} \hfill \\ t_{7} \hfill \\ t_{8} \hfill \\ \end{gathered} \\ \end{array} } \right]\user2{,d} = \left[ {\begin{array}{*{20}c} \begin{gathered} t_{{\text{A}}} \hfill \\ t_{{\text{B}}} \hfill \\ \end{gathered} \\ {t_{{\text{C}}} } \\ {t_{{\text{D}}} } \\ {t_{{\text{E}}} } \\ \end{array} } \right] \hfill \\ \end{gathered} \right. $$
(15)

It can be found that R(C) = R(C|d) < 8. There are infinite solutions for Eq. (14). A group of solutions is as follows:

$$ \left\{ \begin{gathered} t_{1} = (t_{{\text{A}}} + 2t_{{\text{C}}} + t_{{\text{D}}} + t_{{\text{E}}} )/4 \hfill \\ t_{2} = (t_{{\text{B}}} - 2t_{{\text{C}}} + t_{{\text{D}}} - t_{{\text{E}}} )/4 \hfill \\ t_{3} = (t_{{\text{A}}} - 2t_{{\text{C}}} - t_{{\text{D}}} + t_{{\text{E}}} )/4 \hfill \\ t_{4} = (t_{{\text{B}}} + 2t_{{\text{C}}} - t_{{\text{D}}} + t_{{\text{E}}} )/4 \hfill \\ t_{5} = (t_{{\text{A}}} + 2t_{{\text{C}}} - t_{{\text{D}}} - t_{{\text{E}}} )/4 \hfill \\ t_{6} = (t_{{\text{B}}} - 2t_{{\text{C}}} + t_{{\text{D}}} - t_{{\text{E}}} )/4 \hfill \\ t_{7} = (t_{{\text{A}}} - 2t_{{\text{C}}} + t_{{\text{D}}} - t_{{\text{E}}} )/4 \hfill \\ t_{8} = (t_{{\text{B}}} + 2t_{{\text{C}}} - t_{{\text{D}}} + t_{{\text{E}}} )/4 \hfill \\ \end{gathered} \right. $$
(16)

In Eq. (16), the absolute values of the coefficients of tC are all 1/2, and those of tD and tE are all 1/4. This means that the action time of the switching vectors can be applied to more working conditions. It should be noted that this group of solutions cannot make the NPP or the FCV up to the maximum regulation capability under any working condition. However, it can ensure that the action time of each switching vector is uniform in a control cycle. The series arrangements of switching vectors 52, 72, and 62; 62, 60, and 61; 61, 71, and 51; and 51, 50, and 52 aim to reduce the switching times. Figure 7 shows the sequence of the switching vectors.

Fig. 7
figure 7

Switching vector sequences of V*(n) in interval 7

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When V*(n) is located in interval 2, 3, or 6, the solution for the action times of switching vectors is almost the same.

3.3.2 V*(n) consisting of a single voltage vector

For the sake of simplicity, when V*(n) consists of a single fundamental voltage vector, the selection of the switching vectors refers to the following three cases.

When V*(n) = V4, the action time of switching vector 70 is Ts, as shown in Fig. 8.

Fig. 8
figure 8

Switching vector diagram when V*(n) = V4

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When V*(n) = V−4, the situation is similar.

When V*(n) = V3, the action time can be considered to be t2 = t4 = t6 = t8 = 0 in interval 8, while the others remain unchanged. At this time, the NPP and the FCV can be decoupled, as shown in Fig. 9.

Fig. 9
figure 9

Switching vector diagram when V*(n) = V3

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When V*(n) = V−3, the situation is similar.

When V*(n) = V2, the action times of the switching vectors can be regarded as t2 = t4 = t6 = t8 = 0 and t1 = t3 = t5 = t7 = Ts/4 in interval 7, while the rest remain unchanged. At this time, the variables cannot be decoupled. However, during this control cycle, the average neutral-point current and the average floating capacitor current are 0. This does not result in deterioration in the NPP or the FCV as shown in Fig. 10.

Fig. 10
figure 10

Switching vector diagram when V*(n) = V2

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When V*(n) = V1, V0, V−1, or V−2, the situation is similar.

The sequence and action time of switching vectors in each interval are shown in the Appendix.

3.3.3 Analysis of the switching times

Interval 8 is taken as an example to analyze the actions of the switches. The sequence of the switching vectors in interval 8 is shown in Fig. 6. The switching process of the switching states of bridge arm a is V5 → V7 → V6 → V7 → V5. The switching process of the switching states of bridge arm b is V0 → V1 → V0 → V2 → V0. The non-series switches only turn on and turn off once in a control cycle, as shown in Table 5.

Table 5 Switching process in interval 8
Full size table

The switching times of the non-series switches when V*(n) is in the other intervals are similar. In the conventional phase-shifted pulse width modulation, the non-series switches turn on and off once in a control cycle. In addition, the series switches only act when the modulation wave crosses zero both in the proposed modulation and in the conventional phase-shifted pulse width modulation. Thus, the losses of the proposed modulation and conventional phase-shifted pulse width modulation are almost the same.

4 Algorithm flow

The procedures of the proposed 5L-ANPC H-bridge inverter SVPWM include.

Determine the interval in which V*(n) is located.

Calculate the action time of the fundamental voltage vectors that are combined into V*(n).

Determine the switching vectors and their output sequence in a control cycle based on the constraints of the switching vectors and the minimum common-mode voltage.

Calculate the action time of each switching vector according to the action time of the fundamental voltage vectors and the deviation in the NPP and the FCV. If the calculated action time is less than the minimum pulse width, the maximum of |tC|, |tD|, and |tE| is divided by 2 for recalculation. If the calculated results still cannot meet the minimum pulse width limit, repeat the above process.

Send the generated pulses to the inverter according to the sequence and action time of the switching vectors in a control cycle.

5 HIL verification

To verify the SVPWM of the 5L-ANPC H-bridge inverter proposed in this paper, a HIL real-time simulation experiment of the system has been carried out. The parameters for the real-time simulation experiment are listed in Table 6.

Table 6 HIL real-time simulation experimental parameters
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In terms of the proposed technique, an offline simulation may not fully reveal all of the features. In addition, the design of a system prototype and hardware experiments are expensive and time-consuming due to their high-power and high-voltage ratings. Therefore, the hardware-in-the-loop method provides an effective method for verifying the control strategy and converter performance due to its low cost, low risk, high flexibility, and fast implementation [21]. A 5L-ANPC H-bridge inverter HIL real-time simulation system was built in the laboratory. It includes a master controller, a slave controller, an analog output interface card, a digital input interface card, a simulator, and a host computer for monitoring.

Verification of the proposed control algorithm is based on the platform in Fig. 11. The master controller receives feedback analog signals from the real-time simulator via the analog output interface card. Then, it sends the reference signals to the slave controller. After that, PWM signals are produced in the slave controller. These PWM pulses are received by the model simulated in the real-time digital simulator (RTDS) via the digital input interface card. With the 5L-ANPC H-bridge model running in the RTDS at a time step of 5 μs, the system voltage and current are measured and transmitted through the A/D conversion interface card to the slave controller and the host computer. Real-time simulation experiment waveforms are shown in Figs. 12, 13, 14, 15, 16 and 17.

Fig. 11
figure 11

Real-time simulation experimental platform

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Fig. 12
figure 12

Output current and voltage waveforms: a m = 0.2; b m = 0.5; c m = 0.85

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Fig. 13
figure 13

NPP and FCV waveforms

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Fig. 14
figure 14

Waveforms when the load changes

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Fig. 15
figure 15

Waveforms when the frequency varies

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Fig. 16
figure 16

Common-mode voltage waveforms: a conventional modulation; b proposed modulation

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Fig. 17
figure 17

Output current and output voltage waveforms: a conventional modulation; b proposed modulation

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Output current and voltage waveforms of the 5L-ANPC H-bridge inverter can be seen in Fig. 12. These results show the proposed SVPWM algorithm to be correct.

When the voltage difference between Cd1 and Cd2 is 4 kV, the FCV of bridge arm a is 1 kV higher, and the FCV of bridge arm b is 1 kV lower. In this case, the waveforms are shown in Fig. 13. Since uCd1 + uCd2 = 10 kV, only uCd1 is shown in Fig. 13. These results show that both the NPP and the FCV reached a balance within 0.2 s. These results show that the proposed control strategy can be effectively used for the decoupling control of the NPP and the FCV. Thus, the proposed strategy is both feasible and useful.

Figure 14 shows waveforms when the load dynamically changes. It can be seen that the NPP and the FCV remain stable when the load changes. When the load current increases, the amplitude of the fluctuations of the NPP and the FCV increase slightly but stably.

When the output frequency f varies from + 20 to − 20 Hz, the output current and capacitor voltages are shown in Fig. 15. These results show that both the NPP and the FCV are balanced and that the output current is smooth when the frequency varies.

The common-mode voltage of the conventional phase-shifted pulse width modulation and the proposed modulation are shown in Fig. 16. The maximum common-mode voltage of the conventional phase-shifted pulse width modulation is 5000 V. Meanwhile, the maximum common-mode voltage of the proposed modulation is within 1250 V. The proposed modulation has a lower common-mode voltage.

Experimental waveforms of the proposed modulation and the conventional phase-shifted pulse width modulation are provided in Fig. 17, where the voltage THD values are 17.5% and 17.84%. The proposed modulation has a lower voltage THD than the conventional phase-shifted pulse width modulation.

6 Conclusion

This paper proposes a new SVPWM for the 5L-ANPC H-bridge inverter. Twenty-eight available switching vectors are obtained based on the constraints of the switching and the minimized common-mode voltage. The fundamental voltage vectors are selected according to the expected output voltage. The action time of the switching vectors is calculated based on the action time of the fundamental voltage vectors as well as the deviations of the neutral point potential and the floating capacitor voltage. The sequence of the switching vectors in a control cycle is determined by the principle of the minimized switching times. Hardware-in-loop real-time simulation experimental results show that the control of the neutral point potential and the floating capacitor voltage can be decoupled with the proposed SVPWM algorithm and that the inverter has good dynamic performance.