1 Introduction

Today all the VLSI circuits performs on low power with high speed. The ALU operations are essential for low power high speed applications which includes digital signal processing, microprocessor, microcontroller, ASIC, etc., ALU is an onliest combinational logic circuit which entails that the output changes with changing of the input. The ALU is a functional device in microprocessor, performs various logical and arithmetic operations (Rani et al. 2011). Also it represents the fundamental building block of the central processing unit (CPU) of a computer. In this paper, a reversible 8-bit ALU using 8-bit complementing reversible adder, 8-bit reversible multiplier, 4 × 1 reversible multiplexer and other logic gates are designed.

The rapid decrease in the size of the chips has lead to the exponential increase in the number of transistors per unit area. As a result, the energy dissipation is becoming a major obstacle in the evolving Nano-computing era. An operation is said to be physically reversible if there is no energy to heat conversion and no change in entropy. In reversible logic, the state of the computational device just earlier to an operation is solitarily determined by its state just after the operation. In other words, no data about the computational state can ever be lost. Hence the reversible logic can be perceived as a deterministic state machine. Landauer (1961) has shown that for every bit of information that is nullified during an irreversible logic computation kTln2 joules of heat energy is generated, where k is the Boltzmann constant and T is the temperature in Kelvin at which the system is operating. Bennett (1973) showed that the kTln2 amount of energy dissipation would not occur if a computation is carried out in a reversible way. The function f(x1, x2 … xn) of n Boolean variables is known as reversible if:

  1. 1.

    The number of outputs is equal to the number of inputs.

  2. 2.

    Any input pattern maps to a unique output pattern.

There are numerous reversible gates available in the market and to name a few such as Peres gate, Tofoli gate, Feyman gate, Fredkin gate, etc., In this paper, one of the reversible gates known as DKGP gate is used. The speciality of DKGP gate is that it can singly function as half adder, half subtractor, full adder and full subtractor. The basic blocks of ALU such as complementing adder, multiplier and multiplexer are first developed using this DKGP gate.

The single electron transistor or SET is a switching device that uses controlled tunneling of electrons to amplify current. This device was chosen due to its Nano feature in size, coulomb blockade characteristics and less power consumption. There are various SET analytical models based on orthodox theory for metallic SETs. An analytical SET model designed for resistively symmetric devices (RS = RD) and valid for |Vds|< e/C∑, C∑ = CS + CD + CG0 + CG1 (Uchida et al. 2000). Later Inokawa and Takahashi (2003) extended this model to asymmetric SETs but does not account for the background charges effect (see Fig. 1).

Fig. 1
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Block diagram of 8-bit arithmetic and logical unit

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A compact MIB model for SET device, which is appropriate for |Vds|<3e/C∑ and temperature of various ranges, and very relevant to single/ multiple gate symmetric/asymmetric device, is chosen for oneway direction flow to reduce the number of exponential terms. MIB model can be adopted for both digital and analog SET circuit design and for both pure SET and hybrid CMOS-SET circuit simulation (Mahapatra et al. 2004). A current conduction model based on the physical properties of the tunnel junctions has been proposed to explain the deviations observed at high temperature between the empirical data and Monte Carlo simulations. The extension of the model consists of thermionic and a field assisted emission component (Dubuc et al. 2009). Another analytical model for SET which describes the drain source current and gate source of single electron transistor at high temperature and it consists on summing up of tunnel current and thermionic current contribution (Touati et al. 2012). In this work, the basic blocks of ALU based on DKGP gate are advanced to the transistor level by using CMOS and SET technology. The MIB model for SET and available MOS models for CMOS are used. The complete 8-bit reversible ALU block on CMOS and SET is simulated and verified using SPICE simulation. The Nano processors based on this Nano-ALU can be developed in future which will be more advantageous in three dimensional image technology to speed up the processing and to increase stability(Li and Shiau 2018).

2 Literature survey

For SET modeling and simulation, the electron tunneling and its transition probabilistically are treated by master equation method. The probability of electron tunneling is used to determine the current density in compliance with parameters of selected input (Willy and Darma 2016). In analog switch technique select input logic is used as a control logic and passes through another input signal from the gate terminal (Parihar et al. 2014). FA is a fundamental building block for designing ALU. There are numerous FAs available for dissipation of low power such as hybrid FA, low power 10 transistors FA and 11transistor FA. FA performing in low power mode by using subthreshold current and dissipates low power (Gangadhar Reddy and Ramireddy 2014; Ravindra et al. 2013). FA is made from low power XOR gates and 2 is to 1 multiplexer (Tiwari and Deshmukh 2014). ALU using FinFET technology has two gates which are electrically independent, which results minimum complexity and low power consumption due to the reduction of leakage current. In FinFET technology, a thin silicon “Fin” which mould the body of the device (Dhulipalla and Deepak 2011). The reconfigurable logic of multi input floating gate metal oxide semiconductor (MIFG-MOS) transistor is used for ALU design which improves the circuit functionality. MIFG-MOS transistor gives ON and OFF states of the transistor by observing the sum of the weighted inputs. MIFG-MOS transistor reduces the transistor number, complexity and delay which leads to low power dissipation (Srivastava and Srinivasan 2002). Metal gate and high-k dielectric gives extra channel length without modifying the leakage current (Vaishnav and Moyal 2012). Digital logic gates, synchronous and asynchronous counters, low power 8-bit ALU using full adder and multiplexer have been designed using hybrid CMOS-SET (Sharma and Tiwari 2016; Jana et al. 2013a, b). Buffered threshold logic gates have been used to design 4:1 multiplexer for the feedback effect and to increase the stability (Jain and Sarkar 2012). The low power 16 bit ALU has been designed using hybrid CMOS-SET combinational logic (Jana et al. 2014). The phase-modulated counters with less number of MOSFETs and multi-gate SETs has been designed to deal with temperature effect and reliability improvement (Deng and Chen 2013). The stability analysis of full adder using SET has been analyzed (Mahima et al. 2017).

3 Single electron transistor

A single electron transistor (SET) is considered as an essential feature of current research in the field of Nano technology. The single-electron charging energy of a nm scale island and consequent tunneling events to the island was analyzed by C.J. Gorter in 1950s. Gorter (1951) noticed that the granular thin film structure and the suppression of low voltage due to the charging of grains with single electron. The film is actively granular in nature, with a range of grain sizes are only ~ 7–10 nm. This Nano scale size is strong enough for significant charging effects of single electron. A thin oxide layer is then sputtered on top of the granular metal film, and certainly a metal contact is deposited on top to develop a layer of metal nano particles. The thin oxide layers develop tunnel barriers for transfer of electrons. Addition of a third terminal called ‘gate’, the island of the two tunnel junctions forms SET by Fulton and Dolan (1987). SETs are devices in which the charge transport occurs discrete in nature unlike MOS devices.

It comprises of two electrodes namely, the drain and the source, connected through tunnel junctions to one common electrode with a low self-capacitance, known as the island. The third electrode called gate, is capacitively coupled to the island shown in Fig. 2. This gate electrode can tune the electrical potential of the island.

Fig. 2
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Schematic structure of SET

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The single electron tunneling concept can be detailed by considering a tiny metallic sphere. In Fig. 3, consider a small sphere which is electro-neutral. Also seeing that an electron is located near to the sphere and it gets attracted and linked with a sphere which in turn leaving a negative charge on the sphere. Due to that charge, a strong electric field is produced around the sphere. If any other electron comes near to this sphere, it will feel a strong repulsive force exerted by the electric field created around the sphere. This coulomb blockade energy is the repelling energy of preceding electron remain in the island to the next electron coming towards the island.

Fig. 3
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Concept of single electronics

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This coulomb charging energy is the key reason for the suppression of electron transfer across the junction simultaneously. This occurrence is known as “Coulomb blockade” as shown in Fig. 4. In order entering and leaving of electrons from one to another junction is commonly called as “correlated tunneling of electrons”. Since it has the ability to control the tunneling of single electrons across its junction, it performs at high speed. Since power consumption is proportional to number of transferred electrons across the junction, it consumes less power. Since electron tunneling is a discrete process, the electric charge flows through the tunnel junction in multiples of e. Now if the bias voltage V is kept below the Coulomb gap voltage and if the gate voltage is increased, the energy of the initial system (with no electrons on the island) gradually increases, while energy of the system with one excess electron on the island gradually decreases. The periodic oscillation in the Coulomb gap is observed in the IDS-VDS characteristics by changing the gate voltage as shown in Figs. 5 and 6. The SET behaves as a easy switch, because it is influenced by the gate voltage. The SET will turn ‘on’ when Coulomb blockade does not exist and the SET will turn ‘off’ when a Coulomb blockade exists. Since SET is a Nano-scaled switching device, it can hang on to its scalability even on an atomic scale. Single electron device is commonly depend on an intrinsically quantum phenomenon known as the Tunnel effect (Singh et al. 2012).The molecular single-electron transistor (SET) with (10-Boranylanthracene-9-yl) borane molecule as an island has been analyzed in an attempt to model a better acene series SET. The analysis proved that the doped anthracene-based SET has high switching speed and power efficiency related with the other organic molecular SETs reported of the kind.(Boddepalli SanthiBhushan et al. 2016). SET is a promising candidate for attaining higher detection sensitivity due to its coulomb oscillations and thus it can be possibly used as one of the sensors among many in the ultra-sensitive detection of ions and biomolecules in the field of healthcare and life sciences (Malasinghe et al. 2017). SET can also be significantly employed in the detection of infrared images in object recognition especially in infrared animal recognition in the forest (Mangai et al. 2018).

Fig. 4
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Coulomb blockade

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Fig. 5
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Single-electron transistor

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Fig. 6
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Coulomb blockade of IDS-VDS. Characteristic as a function of gate voltage

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4 DKGP reversible gate

A 4* 4 reversible DKGP gate is one among many of the reversible gates available and it can function as both reversible full adder and full subtractor. It is shown in Fig. 7. It can be verified with the input pattern corresponding to a respective output pattern which can be uniquely determined. The logical implementation of both full adder and full subtractor from DKGP gate is shown in Figs. 8 and 9 respectively. If the input P = 0, the gate behaves as a reversible Full adder and if the input P = 1, the gate behaves as a reversible full Subtractor (Krishnaveni.D et al. 2012).

Fig. 7
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A DKGP gate

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Fig. 8
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DKGP gate as a full adder

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Fig. 9
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DKGP gate as a full subtractor

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The 4:2 and 6:2 compressors can be constructed from DKGP full adder and it is shown below in the Figs. 10 and 11 (see Table 1).

Fig. 10
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4:2 compressor using DKGP gate

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Fig. 11
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6:2 compressor using DKGP gate

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Table 1 Truth table of DKGP gate
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Using this reversible gate, all the components of the ALU are developed initially and then it is implemented using CMOS and SET.

5 Reversible 8-bit ALU using single electron transistor

The 8-bit ALU is constructed from NOR/OR gate and NAND/AND gate for logical operations and complementing adder and multiplier for arithmetic operations. All the blocks are implemented using CMOS and SET.

5.1 NOR/OR gate

The gate acts as NOR gate if the control input is zero and acts as OR gate if the control input is one. The transistor implementation of NOR/OR gate using CMOS and SET is shown in the Figs. 12 and 13.

Fig. 12
figure 12

NOR/OR gate using CMOS

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Fig. 13
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NOR/OR gate using SET

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5.2 NAND/AND Gate

The gate acts as NAND gate if the control input is zero and acts as AND gate if the control input is one. The transistor implementation of NAND/AND gate using CMOS and SET is shown in the Figs. 14 and 15.

Fig. 14
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NAND/AND gate using CMOS

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Fig. 15
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NAND/AND gate using SET

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5.3 DKGP gate as a 1-bit full adder

The one bit full adder using DKGP gate has been developed by giving the first input of DKGP gate is zero. The transistor implementation of one bit full adder using CMOS and SET is shown in the Figs. 16 and 17.

Fig. 16
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1-bit full adder using CMOS

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Fig. 17
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1-bit full adder using SET

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5.4 8-bit Reversible Adder/Subtractor

The complementing adder block acts as both 8-bit adder and 8-bit subtractor depending on the control input. If the control input is 0, this block acts as 8 bit adder and if it is 1 then it acts as 8 bit subtractor. This complementing adder is constructed from series of DKGP full adders which is shown in Figs. 18 and 19.

Fig. 18
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Block diagram for 8-bit adder/subtractor using CMOS

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Fig. 19
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Block diagram for 8-bit Adder/Subtractor using SET

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The number of gates has been minimized to develop 8 bit complementing adder block using DKGP gate. The comparison for existing and proposed 8 bit adder with number of gates and garbage outputs is shown in Table 2 and a comparison graph is shown in Fig. 20.

Table 2 Number of gates used for complementing adder block
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Fig. 20
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Comparison of adders with number of gates

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5.5 4:1 Multiplexer

The reversible multiplexer is designed using reversible PV gate is shown in the Figs. 21 and 22. It can work as 2:1 multiplexer. The 4:1 multipl exer can be obtained from three PV gates. The 4:1 mux can be developed by calling the 2:1 mux in program coding(using syntax .subckt). Thus the transistor implementation of 2:1 mux using CMOS and SET is shown below in the Figs. 23 and 24 (see Table 3).

Fig. 21
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PV gate

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Fig. 22
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4:1 Mux using PV gate

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Fig. 23
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2:1 Mux using CMOS

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Fig. 24
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2:1 Mux using SET

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Table 3 Truth table for 4:1 mux
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5.6 8 × 8 Reversible multiplier

The 8-bit multiplier is constructed from 4:2 and 6:2 compressors in order to reduce the partial product addition. There are 22 full adders, eight 4:2 compressors and five 6:2 compressors are employed to develop reversible multiplier. The serial and parallel combination of these compressors are involved in generating the multiplication output. The block diagram for 8-bit Wallace tree multiplier using compressors are shown in Figs. 25 and 26.

Fig. 25
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8 × 8 reversible multiplier using CMOS

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Fig. 26
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8 × 8 reversible multiplier using SET

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The number of gates has been minimized to develop reversible multiplier using DKGP gate. The comparison for existing and proposed 8 bit multiplier with number of gates and garbage outputs is shown in Table 4 and a comparison graph is shown in Fig. 27.

Table 4 Number of gates used for reversible multiplier
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Fig. 27
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Comparison of multiplier with number of gates and garbage outputs

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6 Results and disscussions

The reversible 8-bit ALU is designed with minimum number of gates and implemented with both CMOS and SET technology. The design is simulated using ORCAD tool. The outputs are verified for CMOS-ALU with the operating voltage of 5V. The output glitches are obtained with the operating voltage of less than 2 V. The same output responses with no glitches are obtained for SET-ALU with the operating voltage of 25 mV. The SET technology gives exact output and dissipates ultra low power. The functions of ALU to the control inputs are given in the Table 5. The model parameters of CMOS and SET is given in Table 6. The simulation results of reversible ALU using SET is shown below in the Figs. 28, 29, 30 and 31.

Table 5 Functions of ALU
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Table 6 Values of Parameters used for the simulation
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Fig. 28
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Control inputs (S2 S1 S0)

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Fig. 29
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Input A0–A7

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Fig. 30
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Input B0–B7

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Fig. 31
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Output(O0–-O7)

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The power dissipation of various components involved in ALU using CMOS and SET is shown in the Tables 7 and 8.

Table 7 Power dissipation, delay and PDF of components using CMOS
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Table 8 Power dissipation, delay and PDP of components using SET
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7 Conclusion

The reversible 8-bit ALU is designed using CMOS and SET. The SET technology provides the same output response for the same input signal timing as in CMOS with very low operating voltage. Thus power consumption of SET technology varies drastically with CMOS. This work witnessed that the SET technology provides an alternative approach to conventional CMOS in low power digital applications. Therefore ALU using SET could be a potential towards the development of faster Nano processor with smaller size and low power consumption.. The practical implementation of SET can be done with adequate lithographic techniques and parameter dispersion considerations.