Introduction

The realization of a sustainable society with a low-carbon footprint requires the popularization of electrified vehicles (i.e., hybrid electric vehicles, fuel cell vehicles, and electric vehicles), which have recently received growing interest.1,2,3 These vehicles have batteries, motors, and power control units (PCUs). Power devices that are mounted on power modules in PCUs operate at a high frequency to convert DC to AC power. High-power density PCUs are required to reduce their size and weight. SiC devices are instrumental in achieving high-power density PCUs because they have the potential to operate at higher temperatures than conventional Si devices. Heat-resistant bonding materials are needed to ensure the reliable operation of power modules at high temperatures.4,5,6 Several heat-resistant bonding methods have been reported. These include Bi- or Zn-based soldering,7,8 transient liquid phase bonding,9,10,11 and pure metallic nanoparticle sintering. Nanoparticle sintering methods provide bonding layers with a high melting point despite the low temperatures used in the sintering process. Among them, Ag nanoparticle sintering has received extensive attention because of its high thermal and electrical conductivity.12,13,14,15,16 Several studies have been conducted on Cu nanoparticle sintering,17,18,19,20,21,22,23,24 which is less expensive and has a higher electromigration tolerance than Ag nanoparticle sintering. A previous study24 has suggested that high-reliability Cu nanoparticle bonding layers require micropore suppression and interfacial adhesion improvement. To overcome these issues, we proposed a bonding layer sintered by mixing Cu nanoparticles and Bi-Sn particles; this bonding technique was called “hybrid bonding”.25,26 This bonding layer formed using low additional pressure (3 kPa) showed a high bonding strength (> 30 MPa). To verify the reliable operation of power modules under high temperatures, several reliability tests, such as high-temperature storage, thermal cycles and power cycle tests, are generally required. A previous study27 confirmed that the proposed bonding layer maintained its initial bonding strength after a high-temperature storage test (> 200°C). Although the thermal cycle test is crucial for ensuring the high-temperature operation of the power modules, few studies have undertaken thermal cycle tests for hybrid bonding. This study conducts a nondestructive observation of the degradation process of hybrid bonding under a cyclic thermal stress test using high spatial resolution synchrotron radiation x-ray computed laminography (SRCL) measurements.28,29,30,31,32,33,34,35

Experimental Procedure

Sample Preparation

As shown in Fig. 1, a Si chip (5 × 5 mm2) and a direct bonded aluminum (DBA) substrate (20 × 20 mm2) were bonded together by hybrid bonding. The DBA substrate consisted of an AlN plate and a high-purity Al metal film (99.99%). Cu nanoparticles with a diameter of 230 nm were obtained by decanoic acid (C9H19COOH) and decylamine (C10H21NH2) modification17 Commercial Bi-47 wt.% Sn particles (eutectic temperature of 137°C and diameter < 36 µm) were obtained from Kojundo Chemical Laboratory. The Cu nanoparticles and Bi-Sn powder were mixed at a ratio of 7:3, and α-terpineol was added to the mixture to turn it into a paste using a planetary centrifugal mixer. A Ti (100 nm)/Ni (200 nm)/Ag (100 nm) film was formed as an adhesive layer on the joint surface of the SiC chip and the DBA substrate by magnetron sputtering. The Si chip was mounted on the DBA substrate after applying a 100-µm-thick layer of the paste using a metal mask. Two-step firing (first firing step: heating to 200°C and holding for 10 min; second firing step: heating to 350°C and holding for 5 min) was carried out in an H2 atmosphere while applying a pressure of 0.5 MPa. The sintered sample was subjected to the thermal cycle test in atmospheric air (1 atm). The thermal cycle test was conducted under two testing conditions: (1) minimum and maximum temperatures were − 40 and 150°C, respectively, and the exposure time at each temperature was equal to 30 min; (2) minimum and maximum temperatures were − 40 and 250°C, respectively, and the exposure time at each temperature was 60 min. During the thermal cycle testing, 200 cycles of the thermal cycle stress were applied to the sample.

Fig. 1
figure 1

Schematic diagram of the test sample layered structure.

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Characterization

SRCL measurements were performed from the initial state to 200 cycles at the same location of the joint sample. These measurements were conducted at the BL33XU Toyota beamline36,37 located at the synchrotron radiation x-ray facility SPring-8, which is characterized by a high flux density, small angular divergence, and a quasi-monochromatic energy spectrum.38,39,40,41,42,43 The incident beam to the sample is inclined at an angle of 30° with respect to the sample surface. The SR energy (29 keV) was large enough to penetrate the sample along the direction of the incident beam. The exposure step of the sample rotation was 0.1°. The transmitted SR beam was converted to visible light by a scintillator, which was directed through a lens to a complementary-metal–oxide–semiconductor camera. The voxel size in this setup was 0.33 or 1.3 µm. The measured projection images were reconstructed using the filtered back-projection method, considering the tilt angle of the rotational axis.28,32 As shown in Fig. 1, we focused on the slices of three positions in the thickness direction. After the SRCL measurements, the samples were mechanically polished and etched by Ar ion sputtering for cross-sectional observations. The cross-sectional images and elemental maps were obtained by scanning electron microscopy (SEM) and energy dispersive x-ray spectrometry (EDS).

Results

Thermal Cycle test at Temperatures Between − 40°C and 150°C

The reconstructed cross-sectional images of the hybrid bonding layer parallel to the joint surface by the SRCL measurements under the thermal cycle test (− 40/150°C) are shown in Fig. 2. The brightness of a reconstructed image reflects the weight of an element or the density of the material structure. For instance, the presence of a heavy element or a high-density structure is shown as a bright area in a reconstructed image. According to the reconstructed images before the thermal cycle test, two types of morphologies in the bonding layer were observed: (1) voids with diameters < 100 µm at both bonding interfaces, and (2) voids with diameters < 40 µm in the parent phase. Although there were some voids at the bonding interfaces ((i)-a, (i)-b, and (i)-c in Fig. 2), the interfaces appear to be almost uniform. A comparison between the reconstructed images before and after the thermal cycle loading indicates that the effect of thermal cycle stresses (− 40/150°C) on the microstructure of reconstructed cross-sectional images parallel to the joint surface was insignificant. A–A cross-sectional images of the hybrid bonding layer vertical to the joint surface under the thermal cycle test (− 40/150°C) are shown in Fig. 3. The reconstructed image by the SRCL measurements before and after 200 thermal cycles are shown in Fig. 3a and b. There were only small differences between the reconstructed cross-sectional images vertical to the joint surface before and after the thermal cycle test (Fig. 3a and b). The A–A cross-sectional SEM images vertical to the joint surface shown in Fig. 3c indicate the presence of the interfacial voids on the Si chip side ((I)-a, (I)-b) in addition to the voids in the parent phase ((II)-a). Figure 3c shows that the interfacial voids ((I)-a and (I)-b) are flat in shape, whereas the void in the parent phase ((II)-a) is spherical. Because these voids correspond to the those that were present before the thermal cycle test ((i)-a, (i)-b, and (ii-a) in Fig. 2), it is confirmed that they were not caused by the thermal cycle loading.

Fig. 2
figure 2

Reconstructed cross-sectional images of the hybrid bonding layer parallel to the joint surface by SRCL measurement under thermal cycle test (− 40/150°C).

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Fig. 3
figure 3

A–A cross-sectional images of the hybrid bonding layer vertical to the joint surface under thermal cycle test (− 40/150°C): (a) reconstructed image by SRCL measurement before thermal cycle test; (b) reconstructed 2D image by SRCL measurement after 200 cycles; (c) corresponding SEM image after 200 cycles.

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The cross-sectional SEM–EDS mapping of the hybrid bonding layer after the thermal cycle test (− 40/150°C) is shown in Fig. 4. Three phases (A, B, C) were observed in these images. Phases A and B are sintered Cu and Cu-Sn compounds, respectively, in the parent phase. Phase C is a Bi-related material (Bi or Bi-Ni) at the joint interface.25 Because the reaction of Sn in the Bi-Sn powder with Cu nanoparticles outside the powder resulted in the spherical voids ((II)-a), those voids are presumed to be the traces of the Bi-Sn powder.25 It is observed that Sn migrated widely across the parent phase, while the majority of Bi was segregated at both interfaces. The Ni layer on the Si chip and the DBA substrate remained at their interface in the bonding layer. Figure 4 shows that the initial dense layer was retained during the thermal cycle test. As a result, it was confirmed that the effect of thermal cycle loading (− 40/150°C, 200 cycles) on the degradation of the bonding layer microstructure was insignificant.

Fig. 4
figure 4

Cross-sectional images of hybrid bonding layer after thermal cycle test (− 40/150°C, 200 cycles): SEM image (a); SEM–EDS map for Ni (b), Cu (c), Bi (d), and Sn (e).

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Our previous work24 revealed that thermal cycle stresses (− 40/150°C) cause the propagation of cracks over a wide extent of the conventional Cu nanoparticle bonding layer due to its low sintering density. In contrast, the Cu nanoparticle sintering with the liquid phase Bi-Sn enables the densification of the sintering layer due to the liquid phase sintering and the formation of a Cu-Sn compound with a high decomposition melting temperature.25 Moreover, the initial sintered structure was unaltered even after the thermal cycle loading (as shown in Fig. 2). Therefore, this study confirms that the addition of the Bi-Sn powder to the Cu nanoparticles improves the thermal cycle reliability of the bonding layer.

Thermal Cycle Test at Temperatures Between − 40°C and 250°C

The reconstructed cross-sectional images of the hybrid bonding layer parallel to the joint surface by the SRCL measurements under the thermal cycle test (− 40/250°C) are shown in Fig. 5. The reconstructed images before the thermal cycle test show the crack of the bonding layer (iii), traces of Bi-Sn powder (ii), and interfacial voids (i) formed by the insufficient Bi wetting.25 The changes observed in the interfacial voids ((i)-d, (i)-e, and (i)-f), the Bi-Sn traces ((ii)-b), and the crack ((iii)-a) in the bonding layer caused by the thermal cycle loading were insignificant. Therefore, these morphologies did not become weak spots of reliability. Conversely, the thermal cycle stress loading changed the almost uniform interfacial joint at the Si chip side to a non-uniform interface at the periphery of the Si chip. Moreover, we observed remarkable segregation, assumed to be related to the Bi material designated as (iv)-a in Fig. 5. This interfacial change was remarkable up to 10 cycles, whereas the changes were insignificant after 100 cycles.

Fig. 5
figure 5

Reconstructed cross-sectional images of the hybrid bonding layer parallel to the joint surface by SRCL measurement under thermal cycle test (− 40/250°C).

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The cross-sectional images of the hybrid bonding layer vertical to the joint surface under the thermal cycle test (− 40/250°C) are shown in Fig. 6. The reconstructed images by the SRCL measurements before and after 200 thermal cycles are shown in Fig. 6a and b. The SEM image after 200 thermal cycles is shown in Fig. 6c. The interface voids ((I)-d, (I)-e, and (I)-f) were observed in the cross-sectional SEM images vertical to the joint surface shown in Fig. 6c. These voids correspond to those present before the thermal cycle test ((i)-d, (i)-e, and (i)-f in Fig. 5); therefore, they were not caused by the thermal cycle loading. This Bi segregation ((IV)-a in Fig. 6c) corresponds to the morphology ((iv)-a in Fig. 5). Figure 6c reveals the non-uniformity of the interfacial Bi-related material in the peripheral region 300 µm inward from the chip edge, designated as region (X) in Fig. 6c. Accordingly, the thermal cycle stresses generated remarkable Bi segregation and non-uniformity of the interfacial product (region (X)).

Fig. 6
figure 6

A–A cross-sectional images of the hybrid bonding layer vertical to the joint surface under thermal cycle test (− 40/250°C): (a) reconstructed image by SRCL measurement before thermal cycle test; (b) reconstructed 2D image by SRCL measurement after 200 cycles; (c) corresponding SEM image after 200 cycles.

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Figure 7 shows low-magnification images of the hybrid bonding layer parallel to the joint surface on the Si chip side obtained by SRCL measurements after the thermal cycle test (− 40/250°C, 200 cycles). The morphology ((v)-a) in Fig. 7) shows a network-like macro-void of ~ 50-µm width in the region (Y), which originates from the gas molecules caused by the solvent in the paste and the capping layer of Cu nanoparticles.27 A comparison between Fig. 7a and b indicates that the effect of thermal cycle stress loading (− 40/250°C, 200 cycles) on region (Y) was lower than that on region (X).

Fig. 7
figure 7

Low magnification reconstructed cross-sectional images of the hybrid bonding layer parallel to the joint surface at Si chip side by SRCL measurement after thermal cycle test (− 40/250°C): (a) before thermal cycle test; (b) after 200 cycles.

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Figure 8 shows the cross-sectional SEM–EDS mapping of the hybrid bonding layer after the thermal cycle test (− 40/250°C). As depicted in Fig. 4, phases A (Cu sintered part) and B (Cu-Sn compound) in the parent phase and a phase C (Bi-related material) are also observed. The binary phase diagram indicates that phase B is either Cu6Sn5, Cu3Sn, or Cu41Sn11,and indicates that phase C is Bi3Ni at 350°C (second firing). In our previous study, phase B and phase C were estimated to be Cu3Sn and Bi3Ni based on the SEM–EDS results.25 Although small voids and cracks caused by thermal stresses were found in the parent phase, several interfacial cracks on the Si chip side were generated between the Birelated material and the Ni adhesive layer. These results indicate that the thermal cycle stress only affected the interface on the Si chip side.

Fig. 8
figure 8

Cross-sectional images of hybrid bonding layer after thermal cycle test (− 40/250°C, 200 cycles): SEM image (a); SEM–EDS map for Ni (b), Cu (c), Bi (d), Sn (e).

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Discussion

Segregation of the Bi-Related Material During the Sintering Process

The heating process for sintering causes the shrinkage of the Cu/Bi-Sn paste, while causing the expansion of the Si chip and the DBA substrate. This results in the tensile strain of the bonding layer, especially at the bonding interfaces. In the second firing process at 350°C, melted Bi migrates towards the bonding interface, where the thermal strain is large, without reacting with the sintered Cu portion. This leads to the brittle Bi segregation, which may reduce the interfacial strength at both the Si chip interface and the DBA substrate interface, as shown in Fig. 5. A similar phenomenon was reported by Satoh et al.44 on Zn-mixed Cu nanoparticles/Bi-Sn solder bonding.

Segregation of the Bi-Related Material During the Thermal Cycle Test

The thermal strain is induced by the mismatch of the coefficient of thermal expansion (ΔCTE) between the elements of the sample during the thermal cycle loading. The thermal strain ε applied to the bonding layer under linear approximation is given by Eq. 1:

$$ \varepsilon = \Delta {\text{CTE}} \cdot \Delta T \cdot L $$
(1)

where ΔT is the temperature difference during the thermal cycle test, and L is the length from the center of the joint surface. The CTE of the joint parts are as follows: Si, Al, Cu, and Cu-Sn (Cu3Sn) are 3 ppm/K, 23 ppm/K, 17 ppm/K, and 19 ppm/K, respectively. Equation (1) indicates that the thermal strain at the peripheral interfacial layer of the Si chip side increases during the thermal cycle test. It can be assumed that the large tensile thermal strain during the low-temperature period (around − 40°C) caused micro-voids in the interfacial product formed by the brittle Bi-related material.45,46 When the sample temperature was ~ 250°C, which is close to the Bi melting point, the low-strength Bi segregated at the peripheral interfacial layer of the Si chip side. As a result, the repetition of the micro-void formation and the Bi segregation led to a non-uniform peripheral interfacial layer (X), as shown in Fig. 6c. Conversely, the uniformity in region (Y) at the interface was maintained during the thermal cycle loading because the thermal strain in region (Y) was smaller than that in region (X). Degradation at the central region of a bonding layer between a semiconductor chip and a substrate decreases its thermal and electrical conduction characteristics, resulting in a remarkable increase in the thermal resistance of a power module. In contrast, the effects of the degradation of the bonding layer in the outer peripheral region observed in this study on the conduction characteristics are assumed to be insignificant. Furthermore, because the degradation in the region (X) led to the relaxation of the thermal strain due to the thermal cycle stress loading, it is assumed that the bonding layer did not change significantly after 100 cycles.

Degradation Mode of the Thermal Cycle Stresses with a Large Temperature Difference

DBA substrates with AlN plates of high thermal conductivity have been used for a semiconductor power module that is required to have low thermal resistance.47 The Al film, which has a small Young’s modulus, small yield strength, and small work-hardening rate, is often used as a metal layer for a DBA substrate because the AlN plate has low flexural strength.48 Previous studies have reported the results of the thermal cycle stress test (over 200°C) on a joint sample that was composed of the semiconductor chip, the DBA substrate, and the heat-resistant bonding materials (Ag nanoparticles or Zn-related material).7,49,50 Because the recrystallization temperature is regarded as half of the absolute temperature of the melting point of the metal, the rotation and coarsening of the Al grains due to the thermal cycle stress leads to Al deformation.51 For this reason, the application of the thermal stresses caused the Al of the DBA substrate to deform greatly, resulting in the formation of cracks or voids in the Ag nanoparticles or Zn-based bonding layer. In contrast, our previous study27 revealed that high-temperature storage led to little oxidation of the bonding layer, suppressing the decrease in the mechanical strength. Accordingly, the high bonding strength reduced the Al deformation, resulting in the suppression of the hybrid bonding degradation.

Conclusion

The reliability of a hybrid bonding layer sintered between a Si chip and a DBA substrate under thermal stresses was evaluated by a thermal cycle test at temperatures of − 40/250°C. High spatial resolution SRCL measurements were performed to observe the degradation process of the microstructure within the hybrid bonding layer. While the impact of thermal cycle stress loading on the parent phase in the bonding layer was minimal, thermal cycle stress caused remarkable Bi segregation and a product with a non-uniform interface at the outer peripheral region on the Si chip side. It is assumed that the thermal and electrical conduction characteristics of a power module are not significantly affected by this degradation distribution. Additionally, the changes in the bonding interface result in the relaxation of the thermal strain due to the thermal cycle stress loading. Furthermore, the bonding layer has a high bonding strength, which decreases the Al deformation of the DBA substrate due to the thermal cycle loading and suppresses the degradation process of the bonding layer. Therefore, we believe that hybrid bonding can be a promising technique for achieving the reliable operation and high-power density of power modules at high temperatures.