Introduction

Significant attention has recently been devoted to the epitaxial growth of CdTe layers on alternative substrates (AS), such as Si,1,2 Ge,3 GaAs,4 and GaSb,5,6 to act as buffer layers for the subsequent growth of HgCdTe infrared (IR) materials for detector devices. These studies of lattice-mismatched heteroepitaxial growth have been motivated by the potential for growing device-quality HgCdTe IR materials on large-area, cost-effective substrates for next-generation HgCdTe IR detectors and imaging focal plane arrays (FPAs).7 This would lead to lower cost and larger array format in comparison to current state-of-the-art HgCdTe IR detectors grown on lattice-matched Cd0.96Zn0.04Te (CZT) (211)B substrates, which are smaller-area wafers and much higher cost.8,9,10 It is widely recognized that defects limit the performance of HgCdTe devices and, therefore, FPA operability. Etch pit density (EPD) analysis has been used as a screening technique to qualify HgCdTe epilayers and CdTe buffer layers.11 For HgCdTe grown on lattice-matched CZT, the EPD is typically of the order of mid-104 cm−2, which corresponds with the EPD of the CZT substrates.12 Although alternative substrates have much higher crystalline quality (EPD < 103 cm−2) than CZT, the large lattice mismatch (fl) and difference in thermal expansion coefficient (CTE) (ft) between HgCdTe and these AS (fl = − 19.3%, − 14.3%, − 14.4%, − 6.1%, and ft = − 92%, 14%, 14%, 23% for Si, Ge, GaAs, and GaSb, respectively) inevitably generate misfit dislocations (> 108 cm−2) in the vicinity of the CdTe/AS interface. These misfit dislocations form threading dislocations (TD) that can propagate into the CdTe buffer layer and the subsequent HgCdTe epitaxial layer.13

Providing thick buffer layers is unlikely to yield very high-quality material, so different approaches have been studied to reduce the threading dislocation density (TDD) in CdTe and HgCdTe epitaxial layers grown on AS. These include the use of low-temperature nucleation layers of ZnTe or CdTe,4 and various forms of cyclic thermal annealing (CTA).14 Substantial progress has been made, resulting in routine EPD in HgCdTe and CdTe varying between low-106 cm−2 to low-107 cm−2.4 Although this EPD level is acceptable for the fabrication of shortwave IR (SWIR) and mid-wave IR (MWIR) detectors, a level below mid-105 cm−2 is needed for longwave IR (LWIR) detectors, which are much more sensitive to material defects due to their narrower band gap.15,16 Although EPD values of ~ 105 cm−2 have been achieved in both CdTe/Si and HgCdTe/CdTe/AS layers by using CTA at above 400°C to induce dislocation reduction, there are numerous issues with using this approach at such elevated temperatures. Moreover, the direct growth of HgCdTe on CdTe substrate (EPD of ~ mid-104 cm−2) results in EPD in the range of low-106 cm−2 in HgCdTe, which suggests that reducing the HgCdTe/CdTe lattice-mismatch (fl = 0.25%) is required in order to achieve the desired HgCdTe EPD values for MWIR/LWIR/AS applications.17,18 Therefore, improvement of the crystallinity of the HgCdTe epilayer grown on AS, requires a buffer layer with both low dislocation density as well as in-plane lattice-matching. In the past, one approach for reducing the HgCdTe/CdTe lattice-mismatch was by incorporating Zn and/or Se into the CdTe buffer.19,20 However, due to difficulties related to the epitaxial growth of Cd(Zn, Se)Te by vapor phase methods such as molecular beam epitaxy (MBE), high-quality Cd(Zn, Se)Te ternary buffer layers were difficult to obtain.21 Hence, there is a strong incentive to develop different buffer layer approaches that have higher efficiency in dislocation reduction and better lattice-matching with HgCdTe.

A strained-layer superlattice (SLS), consisting of alternating strained hetero-layers and generally referred to as a dislocation filtering layer (DFL), has been observed to block TD propagation and thus reduce dislocation density in the overlaying epitaxial layer.22,23 Although the dislocation filtering efficiency varies with experimental conditions, modeling results indicate that the minimum TDD obtained in any given structure is likely to be limited by kinetic effects to approximately 104–105 cm−2.24 Movement of TDs in response to misfit strain combined with thermal energy has been shown to be the best way to enhance the annihilation probability.25 The SLS-based DFL technology has been successfully demonstrated in the growth of III–V semiconductors on lattice-mismatched substrates for many years. For example, the TDD has been reduced from ~ 109 cm−2 to ~ 105 cm−2 for GaAs buffer layers grown on Si by incorporating 4 sets of 10-nm In0.18Ga0.18As/10-nm GaAs SLS-based DFLs, leading to high-performance InAs/GaAs quantum dot lasers.26 In contrast to the CTA techniques used in heteroepitaxial growth, it can be anticipated that incorporating a DFL technology will allow thinner buffer layer thickness, shorter processing time, and lower processing temperature to achieve similar EPD levels due to the high dislocation filtering efficiency. Moreover, the successful application of SLS-based DFLs has been reported for a wide range of hetero-material systems in which the DFL structures are grown with a high degree of control over a range of composition and thickness by epitaxial growth techniques such as MBE.27,28,29

Historically, similar dislocation filtering effects can be found in the early growth of heteroepitaxial CdTe on GaAs (001) with the insertion of thick CdZnTe layers.30 However, the (211)B orientation has been widely used for growing high-quality HgCdTe since it requires much lower Hg flux than either (001) or (111)A orientations to maintain the same MBE growth rate, and it is less sensitive to micro-twin formation in comparison to (111) A/B.18 In addition, compared with bulk CdZnTe, SLS-based CdZnTe/CdTe DFLs not only provide more interfaces that increase the chance of coalescence and annihilation of dislocations, but also alleviate growth concerns such as Zn segregation in the CdTe host and the growth temperature incompatibility between ZnTe and CdTe.31 Limited research has been reported in the open literature on the use of SLS-based CdZnTe/CdTe DFL. Although some preliminary results for CdTe SLS-based DFL buffer layers grown on GaSb (211)B substrates have been reported,32 information is still lacking for evaluating this DFL approach on alternative substrates, especially GaAs. High-quality (211)B GaAs substrates are lower cost and more readily available in comparison with GaSb substrates of the same orientation.33

In comparison to non-polar group IV substrates such as Si and Ge, “epi-ready” GaAs is more readily available and has smaller fl and ft with respect to CdTe and HgCdTe. To date, MWIR MCT/GaAs FPAs are commercially available, whereas LWIR MCT/GaAs technology (which is of great interest to the IR industry) is hampered by low operability due to high EPD values. In addition, in the design and MBE growth of CdZnTe/CdTe SLS-based DFL layers, factors such as strain, composition/thickness, growth conditions and annealing temperatures, need to be optimized in order to achieve optimum dislocation filtering efficiency, which represents a large unexplored research space.

Motivated by these considerations, we have undertaken a study of CdTe buffer layers grown on GaAs (211)B substrates and the incorporation of CdZnTe/CdTe SLS-based DFLs. It is shown that the EPD of CdTe buffer layers on GaAs can be effectively reduced from the low-107 cm−2 to the mid-105 cm−2 level using DFLs grown with optimal Zn content and annealing conditions. Moreover, the EPD analysis shows excellent uniformity across the entire 2-inch wafer. These results indicate that DFLs provide a promising approach towards the heteroepitaxy of HgCdTe on large lattice-mismatched substrates with lower dislocation density and smaller lattice-mismatch for application to next-generation IR detectors.

Experimental Section/Methods

Growth of CdTe Buffer Layers on GaAs (211)B Substrates

CdTe buffer layers were grown in a Riber 32P MBE system on 2-inch GaAs (211)B substrates. Elementary Zn, Te, and compound CdTe were loaded in standard Knudsen cells as sources, and the individual fluxes (beam equivalent pressures, BEP) were controlled by adjusting the cell temperatures. To evaluate the in situ oxide desorption process of GaAs substrates prior to MBE growth, reflection-high-energy electron diffraction (RHEED) was used to monitor the transition from a spotty pattern to a streaky pattern as the substrate temperature was raised to ~ 580°C. After oxide desorption at ~ 580°C for 3 min, the substrates were cooled down to 220°C, and a thin ZnTe nucleation layer (< 30 nm) was grown at this temperature for 3 min, and then processed by in situ thermal annealing with a background Te BEP of 3 × 10−6 Torr at 380°C for 15 min. Note that ZnTe has a lattice constant intermediate between those of GaAs and CdTe, contributing to better nucleation on GaAs in comparison to CdTe nucleation layer. The thin ZnTe nucleation layer was used in order to suppress three-dimensional growth and preserve a good (211)B interface for the subsequent CdTe growth.34 After growth of a 2–5 μm thick CdTe bottom layer, several sets of CdZnTe/CdTe SLS DFL were grown, separated by 500-nm-thick CdTe spacer layers. Each set of CdZnTe/CdTe DFL consisted of five periods of ~ 13 nm CdZnTe (20 s MBE growth)/~ 11 nm CdTe (20 s MBE growth). In situ thermal annealing for 15 min was undertaken after each DFL growth. The samples were completed by the growth of a 4–20-μm-thick CdTe top layer. Both the CdZnTe and CdTe layers were grown at about 270°C under Te-rich conditions with the Te/CdTe BEP ratio of approximately 1.5. The CdTe DFL buffer layers were grown with different structural designs and annealing conditions to explore their impact on the final EPD of the top CdTe layer.

Characterization of CdTe Buffer Layers

Fourier-transform IR spectroscopy (FTIR) was used to measure the buffer layer thickness and, therefore, the CdTe growth rate. A Philips X’pert MRD high-resolution x-ray diffractometer (HRXRD) equipped with a four-crystal Ge (220) monochromator was used to obtain double-crystal rocking curve (DCRC) full-width at half-maximum (FWHM) rocking curve values for the layers as well as to determine the structural parameters of the CdZnTe/CdTe DFL, including Zn composition, thickness, and lattice strain through ω–2θ scans and/or reciprocal space mapping (RSM) measurement. Similar XRD analysis has been described in our previous work.32 The CdTe surface morphology of the samples was evaluated using optical microscopy and scanning electron microscopy (SEM). The dislocation density in the samples was characterized via EPD measurements using a standard Everson etchant,35 optical microscopy, and SEM imaging. Cross-sectional transmission electron microscopy (TEM) and SEM images were used to investigate the crystalline quality in more detail. Photoluminescence (PL) spectra were acquired in an unpolarized quasi-backscattering geometry with an Alpha 300 confocal Raman microscope (WITec, GmbH) using a 785 nm laser (laser spot size of ∼ 10 μm) and a 600 g mm−1 diffraction grating (spectral resolution of ∼ 0.75 meV). The CdTe buffer layers were etched to the desired thickness for depth profiling using bromine methanol in order to study the dependence of material properties such as EPD, XRD FWHM, and PL on the thickness.

Results and Discussion

CdTe Buffer Layers with Strained CdZnTe/CdTe Superlattice-Based DFL

Structure Design and MBE Growth

Figure 1a shows a typical sample structure for a CdTe buffer layer on a 2-inch GaAs (211)B substrate with five sets of Cd1−xZnxTe/CdTe SLS-based DFL. The purpose of the SLS layer structure is to increase the likelihood of dislocation annihilation and inhibit dislocation multiplication and/or propagation. As discussed by Wark et al.,24 the key to significant reduction in TDD is TD movement using misfit stress, i.e., in layers with a finite strain-thickness product (εh). Moreover, a good rule of thumb for DFL design in heteroepitaxial growth is given by εchc < εh < 4εchc, where εchc is a constant (experimentally, εchc is ~ 0.24 nm in the GaInAs system). This can be understood by considering that the stress in the DFL needs to be high enough to divert TDs but not enough to generate additional TDs. In a layer of constant composition, dislocation multiplication is expected to commence when the strain thickness product exceeds ~ 4εchc, which places an upper limit on the strain and thickness of a DFL.36

Fig. 1
figure 1

(a) Schematic sample structure for MBE growth of CdTe buffer layers on GaAs (211)B, including several sets of strained CdZnTe/CdTe superlattice-based (SLS) dislocation filtering layers (DFLs). Each DFL layer consists of five periods of Cd1−xZnxTe/CdTe with thicknesses of ~ 13 nm/~ 11 nm, respectively; (b) comparison of x-values as determined by XRD and estimated from the MBE growth conditions for the CdTe DFL buffer layers.

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In calculating this product, the superlattice structure of each DFL set can be considered to be equivalent to a single Cd1−yZnyTe layer having a same total thickness of h = 5d1 + 4d2, and having a mean Zn content of y = xd1/(d1 + d2), and therefore, a mean misfit strain of ε = yfl, where d1 = 13 nm and d2 = 11 nm are the thicknesses of the Cd1−xZnxTe layers and CdTe layers, respectively, and fl = − 5.8% is the lattice-mismatch of ZnTe/CdTe. Hence, the DFL has a strain-thickness product of εh = 3.1x nm, and the constraint condition determines a limited Zn content range of 0.08 < x < 0.30 for our DFL design, assuming the critical strain-thickness product of εchc = 0.24 nm for the Cd1−xZnxTe system. As mentioned previously, a high-quality CdZnTe buffer is challenging to grow, and layers that are too thick and/or have more Zn content may increase the risk of Zn segregation. However, since the CdZnTe SLS layers here are only of the order of 10-nm thick, subsequent CdTe layers should smoothen out any irregularities in the CdZnTe surfaces before other crystal phases nucleate.

Growing a DFL with a specific x-value for the CdZnTe layers (i.e., desired strain) is essential for achieving high dislocation filtering efficiency and repeatable device performance. Under Te-rich growth conditions, the Zn content (\(x\)) in the CdZnTe layers can be estimated using the relationship x = PZn/(PZn + k gct) since Cd1−xZnxTe can be considered an alloy of CdTe and ZnTe, where PZn is the BEP of the Zn cell, gct is the growth rate of CdTe, and k is an adjustable parameter. Experimentally, the value k = 2 × 10−7 h μm−1 was obtained from calibration growths in our MBE system. During MBE growth, the BEP of the CdTe cell (Pct) was fixed to be around 2 × 10−6 Torr, which corresponds to a growth rate of approximately 2 μm h−1. Experimentally, we find that for growing Cd1−xZnxTe with x < 0.2, the Zn cell temperature (TZn) and the corresponding PZn need to be lower than ~ 260°C and 1 × 10−7 Torr which, however, is close to the practical background floor of the ion gauge used for BEP measurements in our Hg-containing MBE chamber. Fortunately, based on the relationship

$${P}_{\mathrm{Zn}}={39617e}^{-14159/({T}_{\mathrm{Zn}}+273)}$$
(1)

fitted from the BEP data measured at higher temperatures of the Zn cell, we can extrapolate PZn for relatively low Zn cell temperatures and can thus grow Cd1−xZnxTe with specific x values < 0.2. This approach was found to be very useful, especially for growing Cd1−xZnxTe with low \(x\) value when the BEP gauge appeared to be influenced by the Hg background pressure after Hg-related growth. As evident from Fig. 1b, x-values estimated from the MBE growth conditions based on the calculated PZn and measured gct are in good agreement with x values determined by XRD measurement.

Dislocation Filtering Effect

The dislocation filtering effect in the CdTe DFL buffer layers grown on GaAs substrates has been confirmed by several characterization methods, including TEM, EPD analysis, and PL. Although TEM can visualize individual defects, it is destructive and time-consuming. Moreover, it has a lower detection limit of TDD of 107–108 cm−2 due to the relatively small volume being analyzed. Moreover, TEM specimen preparation of HgCdTe structures can be challenging due to the fragile nature of the material compared with other semiconductors.37 Defect decoration based on chemical etching, known as EPD etching, has been developed for several semiconductors, including HgCdTe.35,38 EPD etching is also destructive but significantly extends the lower detection limit. For example, 1 min of Everson etching for CdTe (211)B surface (etching rate ~ 1.9 μm min−1) decorates TDs by forming larger surface etch pits (~ 2 μm in size, as shown in Fig. 3), which can be easily detected and counted at lower magnification, thereby facilitating the inspection of larger sample areas. The surface morphology/roughness/polarity and orientation of epitaxial films may affect the validity of EPD measurements.39 The EPD values were obtained from CdTe buffer layers with reasonable surface quality and regular (211)B orientation, as confirmed by XRD measurements. The chemical etching rate for the Cd1−xZnxTe/CdTe DFL region is a factor of 2–5 times (depending on the x value) lower than that for CdTe, and the defect decoration effect appears to be less pronounced if the etching stops within the DFL region, causing difficulties in characterizing TD evolution within the CdTe layer between each DFL set. To control the depth at which the etching is terminated, most CdTe DFL buffer layers were grown with a sandwich structure of ~ 5-μm CdTe bottom layer/DFL region (~ 2.8-μm thick for five sets of DFL)/~ 5-μm CdTe top layer.

In this study, TEM was used to examine the CdTe buffer layer structure, in particular, the interactions between TD and each SLS-based DFL. Figure 2a and d present bright-field (BF) TEM images of CdTe DFL buffer layers grown on GaSb (211)B and GaAs (211)B, respectively, showing clear and sharp interfaces between the DFL and the surrounding CdTe layers. Figure 2b shows a higher-magnification TEM image of the CdTe/GaSb interface, where it can be observed that a TD starts from the interface and propagates through the 2-μm-thick CdTe bottom layer. The observation of an almost dislocation-free top CdTe layer suggests an efficient reduction of TDD by the SLS DFL regions. The dislocation filtering effect of the SLS DFL is demonstrated in the enlarged TEM image in Fig. 2c. In addition to sharp SLS interfaces, apparent TD re-direction and termination at the CdZnTe/CdTe hetero-interfaces are evident, as indicated by the yellow arrows. Similar dislocation filtering has been observed in a CdTe DFL buffer grown on GaAs (211)B substrate with similar DFL design (Fig. 2d).

Fig. 2
figure 2

(a) Cross-sectional bright-field TEM images of 5.2-μm-thick CdTe buffer layer containing four sets of CdZnTe/CdTe DFLs on GaSb (211)B substrate; (b) enlarged TEM image of the CdTe/GaSb substrate interface where threading dislocations originate from; and (c) enlarged TEM image of the DFLs, showing evidence for dislocation filtering (indicated by yellow arrows); (d) TEM image of CdTe DFL buffer layer grown on GaAs (211)B substrate (Color figure online).

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Figure 3a shows an MBE-grown 2-inch CdTe buffer/GaAs (211)B sample, having a uniform and mirror-like surface to the naked eye. In order to examine the material quality of the top CdTe layer across the whole wafer, EPD measurements were performed for a bar cut along the diameter, which still shows a shiny surface after EPD etching, as visible in Fig. 3a. Figure 3b shows a representative SEM image for the etched surface, and the EPD is determined to be approximately 5 × 105 cm−2, agreeing with values determined from optical imaging. As demonstrated in Fig. 3c, the EPD values measured along the wafer diameter are all in the range of mid-105 cm−2, indicating excellent material uniformity across the entire 2-inch wafer. In contrast, as evident from Fig. 3d, the EPD of the bottom CdTe layer is around 2 × 107 cm−2, suggesting that the DFL reduces the dislocation density by a factor of 40. The EPD level achieved for the top CdTe layer is approaching the critical EPD level required for fabricating high-performance LWIR HgCdTe detectors.15

Fig. 3
figure 3

(a) Photograph of 2-inch MBE-grown CdTe buffer/GaAs (211)B with DFL annealed at 320°C; (b) SEM image for EPD measurement of top CdTe layer; (c) optical images for EPD measurement across five points along the wafer diameter; (d) SEM image for EPD measurement for the bottom CdTe surface after EPD etching.

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Figure 4a presents a representative cross-sectional SEM image of a cleaved CdTe DFL buffer layer. After EPD etching, as shown in Fig. 4b, five etch pits in series along the growth direction are visible, which are well separated by each DFL. This result is similar to observations of GaAlAs/GaAs heterojunctions, and is presumably related both to misfit dislocations and TDs present in the vicinity of heterogeneous interfaces.40 As evident from Fig. 4c, the number of cross-sectional etch pits appears to decrease from bottom-to-top after each DFL, suggesting that each DFL acts as a barrier to TD propagation. It is interesting that the DFLs tend to act as agents to reveal the TD propagation path. Although the precise relationship between TD and the observed cross-sectional etch pits is unclear at this stage, it would appear that etch pits form preferentially within the CdTe space layers due to the presence of Zn in the DFL region, which leads to reduced Everson etching in the DFLs. Although the cross-sectional etch pits have been observed experimentally, it remains challenging to apply this approach for characterizing the TD evolution in CdTe DFL buffer layers since there are often only a few pits visible in the cross-sectional surface after EPD etching in most CdTe buffer layers examined.

Fig. 4
figure 4

(a) Cross-sectional SEM images of cleaved CdTe buffer layer with DFLs, and (b) after cross-sectional EPD etching. (c) Depth-dependence of cross-sectional EPD on the number of DFLs.

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As a quick and non-destructive approach, optical techniques such as PL have been widely used in developing optoelectronic devices. However, since these methods are based on the generation/recombination and transport of charge carriers, their application for evaluating TDD present in a layer suffers from the presence of non-ideal surfaces, interfaces, and background impurities, which typically dominate the overall recombination velocity (therefore, PL intensity) and hence screen the impact of bulk TDD. Despite this drawback, a comparison of PL intensities for similar structures grown in the same batch of samples and/or within a short time interval is relevant to TDD measurements, since the MBE growth conditions in terms of background impurities and fluxes can presumably be assumed to be unchanged. To assess the material quality of the CdTe buffer layers grown, RT (room temperature) PL spectroscopy was undertaken for samples grown within the same MBE growth session. Figure 5a and b compare PL intensities of the CdTe buffer layers. Under the same excitation conditions as indicated by the inset in Fig. 5a, these PL intensities of the CdTe peak at around 1.5 eV are very well correlated with the EPD values in the range from low-107 to mid-105, suggesting that this optical method provides a fast and reliable non-destructive approach for evaluating the TDD for CdTe buffer layers with and without DFL. In contrast, as evident from Fig. 5b and c, a larger XRD FWHM does not necessarily imply higher TD density, as will be discussed in the “Impact of DFL Design on Material Properties of CdTe Buffer Layers” section.

Fig. 5
figure 5

(a) Room-temperature PL spectra of CdTe buffer layers with/without DFL. The inset shows that laser intensities are the same, indicating the same excitation conditions for all samples; (b) PL peak intensity and XRD FWHM plotted as a function of the measured EPD for different buffer layers; (c) optical images for EPD measurements on CdTe buffer layers after EPD etching. Sample numbers of “S1”, “S2”, “S3”, “S4”, “S5”, “S6” are labeled for the CdTe buffer layers analyzed in the figure.

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Impact of DFL Design on Material Properties of CdTe Buffer Layers

Dislocation Filtering Efficiency

There are several parameters such as x value in Cd1−xZnxTe layers, CTA temperature, and the number of DFL, as summarized in Fig. 6, that affect the dislocation filtering efficiency (η) and, therefore, the final EPD value of the top CdTe layer. As shown in Fig. 6a, the EPD values of the bottom CdTe layer (EPDb) and the top CdTe layer (EPDt) in CdTe buffer layers with different DFL designs were measured, with the corresponding η as calculated by

$$ \eta = ({\text{EPD}}_{{\text{b}}} - {\text{EPD}}_{{\text{t}}} )/{\text{EPD}}_{{\text{b}}} $$
(2)

and shown in Fig. 6b. In the case of buffer layers with five sets of DFL grown with CTA at 320°C, an optimal x range of 0.15 < x < 0.17 is observed, which leads to a low EPD level ranging from mid-105 cm−2 to low-106 cm−2, and the highest EPD filtering efficiency of ~ 98% within the Zn composition range of 0.08 < x < 0.27 studied. When x = 0.17, samples with no thermal annealing as well as those that underwent annealing at the higher temperature of 360°C resulted in a relative higher EPD level of mid-106 cm−2 and corresponding η of 85% and 60%, respectively. It is generally assumed that moderate thermal annealing for DFL structures can further improve their efficiency of filtering defects due to the combined effect of increasing the mobility of defects and introducing thermal strain (εt) for more efficient defect annihilation.41 The data in Fig. 6b suggests that in CdTe DFL buffer layers without CTA, the optimal x value in Cd1−xZnxTe is relatively high at around 0.23 (η = 94%, EPDt of 2 × 106 cm−2). This is to be expected since higher x value, and therefore, more lattice-mismatch strain in the DFL, can compensate for the lack of benefits associated with CTA.

Fig. 6
figure 6

(a) EPD values measured for the top CdTe and bottom CdTe layers for DFL buffer layers grown with different DFL designs and plotted as a function of Zn content (x), and (b) corresponding EPD filtering efficiency.

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Excessive annealing can result in net surface evaporation of CdTe, surface roughening, Te deficiency related defects, and potential nucleation points for additional dislocations.42 However, this is unlikely to occur for nearly relaxed CdTe when the CTA is carried out at temperatures below 400°C under Te overpressure. Experimentally, we found that the EPD of a CdTe/GaAs buffer without DFL can be reduced from 2 × 107 cm−2 to 1 × 107 cm−2 after introducing CTA at temperatures up to 380°C, corresponding to a TD reduction efficiency of ~ 50%. Furthermore, EPD reduction from low-107 cm−2 to mid-105 cm−2 was observed by other workers for CdTe/Si (ft = − 92%) with 10 cycles of CTA at high temperatures up to ~ 500°C.14 In this case, both additional Te and CdTe fluxes were supplied during the CTA process to prevent surface roughening/evaporation. Note that the EPD reported for CdTe/Ge (ft = 14%) and CdTe/GaAs (ft = 14%) with the use of CTA at ~ 400°C varied in the range of 106–107 cm−2.43,44 These values are relatively high compared to the best reported values for CdTe/Si, which may be explained by the differences in the thermal annealing temperature (ΔT) as well as ft since εt ∝ ftΔT. Further comparisons of the effect of thermal mismatch in various HgCdTe/AS composite structures on their final EPD after CTA are worth investigating.45

Another factor that needs to be considered for the CTA process in CdTe DFL buffer layers is that Cd1−xZnxTe has a larger thermal expansion coefficient (α(x) = (4.7 + 3.63x) × 10−6 K−1) than CdTe (ft = 13% for Cd0.17Zn0.83Te/CdTe).46,47 Thus, additional tensile strain εt may be introduced in the CdZnTe layers when the buffer layers are cooled down from thermal annealing temperatures to room temperature (RT).48 Between RT and typical growth/thermal annealing temperature, this difference in thermal expansion amounts to εt = 1.8 × 10−4 for DFL without annealing, εt = 2.1 × 10−4 for DFL annealed at 320°C, and εt = 2.4 × 10−4 for DFL annealed at 360°C, which are all nearly two orders of magnitude lower than the lattice-mismatch-induced strain of ε = 1 × 10−2 in a Cd1−xZnxTe/CdTe DFL with x = 0.17. These results suggest that thermal mismatch plays a minor role in the dislocation reduction process for the CdTe DFL buffer layers on GaAs with CTA at the temperatures evaluated (< 380°C).

The above discussion suggests that strained CdZnTe layers in the DFL may be more sensitive to CTA, and thus the effect of excessive heating on the strained CdZnTe layers should be considered. It has been found in many lattice-mismatched systems, such as strained InGaAs/GaAs and strained SiGe/Ge, that annealing of the strained layers helps to generate misfit dislocations that relax the strain and reduce critical thickness.49,50,51 Therefore, the decrease of dislocation filtering efficiency observed in the CdTe DFL buffer with CTA at 360°C could be attributed to thermal annealing-assisted misfit dislocation formation and strain relaxation/leakage in the CdZnTe layers. Further detailed control of the annealing temperature and/or annealing duration, as well as Te flux, could be effective in providing CdTe DFL buffers with EPDt < mid-105 cm−2.14 The CdTe DFL buffer layers demonstrate higher efficiency in TD reduction at much lower temperature CTA in comparison to conventional CdTe/AS, which may be beneficial in reducing the risk of structural damage during cooling with highly mismatched thermal expansion, such as CdTe/Si, as well as reducing the risk of Ga contamination in HgCdTe layers grown on GaAs substrates.52

As evident from Fig. 6b, other parameters such as thicknesses of the top and bottom CdTe layers and the number of DFLs, are also expected to affect the EPDt values. It is interesting that considerable EPD reduction can be achieved by using only two sets of DFL, providing much shorter processing times and thinner buffer layers compared with conventional CdTe buffer layers grown with complex CTA procedures. Moreover, the EPDt of CdTe DFL buffer layers with thicker top CdTe layer (> 10 μm) appears to be slightly larger than that with 5 μm, which may be related to lattice relaxation in the top CdTe layer. In principle, the thicknesses of the bottom CdTe as well as the top CdTe can be reduced for the subsequent growth of HgCdTe without affecting dislocation filtering, while improving the lattice matching for HgCdTe/CdTe, as will be discussed in the “Compressively Strained CdTe In-Plane Lattices In/Near the DFL Region” section.

DFL-Induced XRD FWHM Spread in CdTe Buffer Layers

EPD measurements are destructive, as discussed in the “Dislocation Filtering Effect” section, and therefore, have limited application as a screening technique for the manufacturing process. Simple, fast, and non-destructive techniques such as XRD have been used to screen MBE-grown HgCdTe epilayers in terms of dislocation density.10 As evident from Fig. 7a, for previously reported MBE-grown HgCdTe data on lattice-matched CZT substrates, nearly lattice-matched CdTe substrates, and CdTe buffer/AS, all show the general trend that a decrease in EPD is associated with lower XRD FWHM.4,18 Based on the frontier of the data (upper points of data envelope), we can establish an empirically numerical correlation

$$\rho ={10}^{\left[-14.6+20.8\left(1-{e}^{-\frac{{X}_{\mathrm{f}}}{11.3}}\right)+2\left(1-{e}^{-\frac{{X}_{\mathrm{f}}}{104.5}}\right)\right]}$$
(3)

where ρ is EPD and Xf is XRD FWHM. As illustrated in Fig. 7a, the FWHM for a given value of EPD, as deduced from the empirical curve, is close to the lowest FWHM value, which is presumably dominated by the intrinsic dislocation density, while the spread in measured FWHM can be explained by other parameters such as residual strain and/or composition non-uniformity present in the HgCdTe films. From the difference between the curve and the data points in the lower envelope of the experimental data, it is evident that the spread is no larger than 15 arc-sec when the EPD value is in the low-106 cm−2 range or lower. For example, it appears that when EPD is 2 × 106 cm−2 or lower, the smallest FWHM estimated from the curve is 40 arc-sec, while the experimental FWHM is not larger than 55 arc-sec.

Fig. 7
figure 7

(a) EPD of HgCdTe/CdTe/GaAs and HgCdTe/CdTe/Si grown at Teledyne,4 plotted as a function of XRD FWHM of the underlying CdTe buffer layer. XRD FWHM versus EPD for MBE-grown HgCdTe epilayers on CdZnTe and CdTe substrates are also included.18 The solid line was fitted to the frontier of these experimental data (upper envelope of data); (b) EPD of CdTe buffer layers/GaAs (211)B without DFL from the present study, plotted as a function of XRD FWHM and compared to the same fitted curve as in (a); (c) EPD of CdTe buffer layers/GaAs with DFL and some CdTe reference samples from the present study, plotted as a function of XRD FWHM and compared to the fitted curve as in (a), and (d) plotted as a function of Zn content.

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In order to examine this correlation, the experimental data from the present study are plotted in Fig. 7b, indicating that results for buffer layers without DFL are in good agreement with the fitted curve. The large FWHM and EPD (FWHM > 120 arc-sec, EPD ~ mid-107 cm−2) are related to CdTe buffer layers grown with inferior ZnTe nucleation layers. With an optimal ZnTe, the FWHM and EPD are reduced to < 100 arc-sec and low-107 cm−2, respectively, which can be further reduced to 57 arc-sec and ~ 1 × 107 cm−2 when CTA (380°C, 15 min) is applied. However, as shown in Fig. 7c, a much more extensive spread in FWHM values is observed for our CdTe DFL buffer layers. The EPDt for the DFL buffer layers is in the range of mid-105 to mid-106, while the XRD FWHM is in the range of 42–150 arc-sec, which is much larger than the estimated range of 35–50 arc-sec based on the fitted curve from Fig. 7a. Hence, a more residual strain induced by the DFL is suspected to be present in the top CdTe layer of the DFL buffer layers compared to conventional HgCdTe layers. As discussed later, the FWHM spread originates from the compressive strain of the CdTe layers in/near the DFL region. In other words, the tensile-strained CdZnTe superlattice layers can modify the in-plane lattice of their neighboring CdTe superlattice layers and CdTe spacers such that they are compressively strained, thereby relieving their tensile strain.

The correlation between the FWHM spread and the strain related to the DFL buffer design has been investigated. Both the CdTe DFL buffer (x = 0.16) grown with the thickest top CdTe layer (~ 20 μm) and the CdTe DFL buffer grown with the lowest Zn content of x = 0.08 (cap layer thickness ~ 5 μm) have small XRD FWHM that are very close to the expected range of 40–50 arc-sec predicted from the fitted curve. This result corresponds with the fact that a thick top CdTe layer will lead to a relaxed CdTe lattice, and low Zn content will result in lower strain. As evident from Fig. 7d, an FWHM broadening rate of 3 \(\pm \) 1 arc-sec/Zn% is deduced for the DFL buffer layers grown with a 5-μm top CdTe layer and CTA at 320°C. Therefore, the FWHM of 86 arc-sec measured in the CdTe DFL buffer (x = 0.17, EPD = 5 × 105 cm−2) is expected to reduce to 35 arc-sec when the top layer thickness increases from 5 μm to 20 μm or thicker, which is consistent with the estimated value from the FWHM-EPD curve. As evident from Fig. 7b, other parameters such as the thickness of the top CdTe layer, DFL annealing temperature, the number of DFLs, and thickness of the bottom CdTe layer, are also suspected to affect the FWHM values.

Compressively Strained CdTe In-Plane Lattices In/Near the DFL Region

To further understand the abnormal spread in FWHM values for the DFL buffer layers, the thickness-dependent FWHM, EPD, and PL peak energy in the CdTe DFL buffer layers was measured. As evident from Fig. 8a, no apparent EPD ∝1/thickness behavior is observed in the bottom CdTe layer. In contrast, a continuous reduction of the number dislocations during the DFL growth is observed in the CdTe DFL buffer layers (Fig. 8a and e).

Fig. 8
figure 8

Measured (a) EPD, (b) XRD FWHM, (c) simulated XRD intensity, and (d) PL peak energy plotted as a function of thickness measured for CdTe DFL buffer layers. The DFL buffer with x = 0.17 was grown with 2-μm-thick bottom CdTe layer/five sets of DFL/5-μm-thick top CdTe layer, and the DFL buffer with x = 0.16 was grown with 5-μm-thick bottom CdTe layer/five sets of DFL/20-μm-thick top CdTe layer. In order to align the DFL region for these buffer layers, the data from the DFL buffer layers with x = 0.17 were offset horizontally. (e) Optical images of EPD measurements at different depths of the CdTe DFL buffer grown with x = 0.16 and CTA at 320°C.

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As evident from Fig. 8b, the dependence of XRD FWHM on thickness within the CdTe DFL buffer, where an “M” trend is observed near the DFL region, is quite different from that observed for the conventional CdTe buffer layer/AS in which the XRD FWHM decreases monotonically with increasing CdTe thickness.9 Most FWHM broadening is related to mosaic misorientation due to screw and mixed TDs as well as residual strain field due to lattice-mismatched growth.53 As the layer grows, the remainder of the strain is relaxed by forming dislocations, which results in reduction of the TD density and FWHM with increasing CdTe thickness. By using XRD measurements, it has previously been found for CdTe layers grown on Ge (211)B with in situ annealing after growth at 400°C for 1 h, that the stress of 100 MPa and in-plane strain of 1.5 × 10−3 observed for thin CdTe layers with thickness of ~ 25 nm relaxed rapidly in thicker CdTe layers and became negligible beyond 1 μm.54 Even so, the stress near the heterogeneous interface contributes to FWHM broadening for layers with thickness up to 5 μm due to the considerable XRD sampling depth.

To interpret the “M” relationship observed in Fig. 8b for the DFL sample, we modeled the XRD intensity of the (422) plane. For simplicity, it was assumed that both the bottom and top CdTe were fully relaxed. The XRD FWHM broadening was modeled based on the assumption that the slightly strained CdTe in/near the DFL region and the remaining CdTe layers contribute equally to the total XRD intensity. Thus, the dynamics of the XRD for the (422) plane from the buffer layer with DFL involves a continuum description of XRD intensities contributed by the bottom CdTe layer (IB), CdTe in/near the DFL region (ID), and the top CdTe (IT). The results for ID, IT, IB as a function of layer thickness in a CdTe DFL buffer are plotted in Fig. 8c. The total XRD intensity (ID + IT + IB) increases as the layer thickness increases up to 10 μm and then maintains an almost constant value, indicating an average XRD sampling depth of 10 μm. It is noted that the positions in the modeled data where ID = IT + IB in Fig. 8c tend to correlate well with the positions (B, D) where the local maxima of XRD FWHM occur experimentally, as shown in Fig. 8b. In addition, the local minimum of XRD FWHM observed within the DFL region in Fig. 8b can be attributed to position “C” where the XRD intensity is mainly due to CdTe in/near the DFL region, i.e., ID, as shown in Fig. 8c. After the growth of 7-μm or more of the top CdTe, ID becomes negligible, and the XRD FWHM is mainly determined by the relaxed top CdTe layer with reduced EPD, resulting in the smallest FWHM of 42 arc-sec.

In order to assess the strain of the CdTe buffer layers, RT PL spectra were taken for samples at different etch depths. The energies of the PL peaks obtained in this way are compared in Fig. 8d as a function of thickness. For depth-profiling positions in which the etched surface is close to the top DFL, a blueshift of PL peak is observed, which presumably originates from stress in the CdTe layers rather than from quantum-confinement effects induced by the CdZnTe layers. This is because no relaxed CdTe-related PL peak was observed when changing the working distance of the confocal microscopy PL system, and because the PL lineshape remains the same as that observed for other bulk CdTe layers, as shown in Fig. 5a. Considering that the strain-induced blueshift coefficient of the CdTe band gap is about 1.7 × 10−2 eV GPa−1,55 the compressive stress in the CdTe around the DFL region (x = 0.16, CTA at 320°C) was estimated to be around 100 MPa, which corresponds to a compressive in-plane lattice strain of around 1.5 × 10−3. The stress falls off rapidly with distance from the DFL region (steeper than that of the XRD FWHM because the sampling depth of the 785 nm laser beam is less than 1 μm), then decreases gradually, and eventually becomes negligible for the top CdTe layer beyond 7 μm from the top DFL.

To confirm the lattice strain present in the CdTe DFL buffer layers, XRD RSM measurements of asymmetric (333) and symmetric (422) planes were undertaken for the CdTe DFL buffer having the structure of 2-μm bottom CdTe/5 sets of DFL/5-μm top CdTe (x = 0.17, CTA at 320°C, EPDt = 5×105 cm−2). The measured reciprocal lattice points of the (422) planes are shown in Fig. 9a. The dominant bottom peak corresponds to the relaxed top CdTe layer and the nearby sub-peak with lower intensity corresponds to the CdTe layers in/near the DFL region, as indicated in Fig. 9b. The two upper features consist of several interference fringes corresponding to the strained CdZnTe/CdTe DFLs, indicating that sharp CdZnTe/CdTe interfaces have been achieved. The direction for the XRD ω scan for obtaining FWHM for the CdTe DFL buffer layer is also denoted in Fig. 9a and c, and the FWHM would broaden when the top CdTe peak fades away with its thickness decreasing, corresponding with the observations in Fig. 8b.

Fig. 9
figure 9

(a) XRD RSM map for the (422) plane and (c) the corresponding ω–2θ map measured for the DFL buffer grown with x = 0.17 and CTA at 320°C; (b) a schematic representation of CdTe DFL buffer structure on GaAs. The difference in width of each layer represents the difference (not to scale) in in-plane lattice constant. The in-plane lattice relaxes far from the DFL region for the sufficiently thick bottom and top CdTe layers. In/near the DFL region, the in-plane lattice of CdTe is compressively strained, resulting in better lattice-matching with HgCdTe than a relaxed CdTe layer. For the symmetric (422) RSM in (a), the peak separation in the Qx direction indicates the presence of lattice tilting, whereas the peak separation in the Qy direction indicates the presence of lattice mismatch.

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Based on the RSM results, the extracted strain parameters for each layer in the CdTe DFL buffer are summarized in Table I. The mean in-plane compressive strain for the CdTe layers in/near the DFL region is determined to be 0.13%, which is in good agreement with the PL results shown in Fig. 8d. The in-plane lattice of the CdTe layers near the DFL region is compressively strained and slightly tilted with respect to the top CdTe layer, leading to a spread in XRD FWHM but better in-plane lattice-matching with HgCdTe, in comparison to conventional single-layer CdTe buffer layers/AS. The tilt direction towards the [11\(\overline{1}\)] crystallographic direction and the small tilt angle of 0.05° is due to the small in-plane lattice-mismatch between the compressively strained CdTe in/near the DFL region and the relaxed CdTe top layer.56

Table I Summary of XRD results of the CdTe DFL buffer shown in Fig. 9
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Although an EPD of ~ 105 cm−2 has been reported for CdTe/Si with the use of optimal CTA, the typical EPD values for HgCdTe/CdTe/AS, and even for HgCdTe layers grown on CdTe substrates, appear to be limited to the level of low-106 cm−2.17,18 Defects in the HgCdTe originate not only from defects in the CdTe buffer but also from the small in-plane lattice-mismatch between HgCdTe/CdTe (fl = 0.25%). The EPD saturation at a level of low-106 cm−2 is believed to be due to the formation of sessile (immobile) dislocations from the fusion of glissile dislocations since it cannot be further reduced by thermal annealing of the HgCdTe layers. In face-centered-cubic semiconductors, such as III–V GaAs and II–VI CdTe, there is an exchange between mobile and sessile TDs that leads to a balance between the two defect populations, allowing continued TDD reduction.24 Therefore, it can be expected that DFL provides a promising approach towards high-quality heteroepitaxy of HgCdTe on large lattice-mismatched substrates having lower dislocation density and smaller lattice-mismatch for future applications in next-generation IR detectors.

Conclusions

This study has demonstrated a dramatic improvement in the material quality of CdTe buffer layers grown on 2-inch lattice-mismatched GaAs (211)B substrates by using CdZnTe/CdTe SLS-based DFL. The DFL approach has reduced the routine EPD from low-107 cm−2 to low-106 cm−2, and 5 × 105 cm−2 for the best layer, which approaches the critical EPD level required for fabricating high-performance LWIR HgCdTe detectors. The dislocation filtering efficiency is found to be highly dependent on the balance between stress and thermal annealing, and even lower EPD can be expected with further optimization of the DFL structural design, growth parameters, and annealing conditions. Moreover, the in-plane lattice of the CdTe layers near the DFL region is found to be compressively strained, leading to a spread in XRD FWHM but better in-plane lattice-matching with HgCdTe, in comparison to conventional single-layer CdTe buffers/AS.

More work needs to be done to investigate the impact of growth and annealing temperature, and the thickness and composition of superlattice layers on the final EPD of the top HgCdTe layer, and their impact on HgCdTe device performance. The beneficial effects of CdZnTe/CdTe DFL are not limited to GaAs and GaSb substrates but could also be applied to the growth of CdTe buffer layers on other alternative substrates such as Si and Ge, which would be a feasible approach for growing high-quality CdTe and HgCdTe materials on large-area alternative substrates for next-generation HgCdTe IR detectors and imaging FPAs with lower cost and larger array format. We anticipate that this technology and associated IR applications will continue to expand in the foreseeable future.