1 Introduction

Conventional CMOS technology has encountered some challenges, such as physical scalability limits, leakage power consumption, and short channel effects [18]. Under the circumstance, a large amount of research on nano-scale has been done extensively. Quantum-dot cellular automata (QCA), a promising alternative technology with potential advantages of fast speed, high density and ultra-low power consumption [27, 32], offers a new method of computation and information transmission. QCA was first proposed by Lent et al. in 1993 [27], and was developed rapidly in recent years. Some experimental devices have been fabricated and tested [4, 25, 46]. To date, the implementation for multi-layer circuits has not been reported [5, 14], while coplanar circuit have already been fabricated [32].

The most distinct feature of QCA is that interaction between cells is absolute Columbic repulsion. Thus there is no current in circuits, which has a potential for extremely low energy dissipation, even makes it lower than traditional kBT in the most optimistic condition [39, 40]. Nevertheless, as an emerging technology, it is necessary to characterize all aspects of QCA. Due to the small size and the fact that electrons actually involve in computation, power consumption is an important parameter. Analogous to conventional CMOS designs, power loss in clocked QCA circuit can be categorized into two types that are commonly used in circuit theory: switching power and leakage power [39]. Switching power which depends on input combinations happens at the time when the cell is changing its state. Leakage power which has nothing to do with input states occurs when the clock goes up or falls down so as to ‘depolarize’ or ‘polarize’ a cell. The proportion of the two in total power dissipation relates strongly to the clock energy. To solve the power consumption in QCA circuits, various estimation models have been proposed, of which two representatives are the accurate power dissipation model and the upper bound power dissipation model, proposed by John Timler et al. and Saket Srivastava et al., respectively [39, 41]. Power dissipation of QCA devices and circuits can be estimated using these models so that we can pick out the superior. QCAPro based on the upper bound power model can be used to assess the performance of QCA designs under power analysis attack, including average, maximum, and minimum power dissipation [40].

Yet QCA technology has not been put into production heavily. One principal limitation is the high fault rate in manufacturing, particularly for molecular QCA, since it is difficult to be high precision within nanoscale. The fault rate has been predicted as high as 50% of the devices [17, 48]. Any defect could result in possible invalidation of device functions. Thus a device with fault tolerance appears to be particularly significant in practice. Robustness and fault tolerance properties have been investigated during the past few years [23, 34]. There are various types of defects that may occur in QCA devices during the fabrication, such as cell misalignment, cell displacement, cell omission, cell rotation and so on. Functionalities of a device may still exist when these defects happen, namely reliability. This is just the direction we are pursuing for. In this paper, we analyze the reliability of QCA designs in presence of single-cell omissions. The designs with the property of insensitiveness to cell omissions will show good prospects in further development.

The main aim of our work is to seek out a three and five-input majority gates with fault tolerance. In order to characterize the proposed majority gates, comparisons are made with their counterparts in terms of area, number of cells, energy dissipation and fault tolerance. By applying the proposed designs to practical circuits and comparing with relevant circuits, the functionality and practicability of them are verified.

The reminder of the paper is organized as follows: Section 2 presents QCA theoretical background and some basic devices. Elaborately selected and our proposed designs as well as their applications will be shown and discussed in Section 3. The simulation results of all circuits are displayed in Section 4. Finally, conclusions are given in Section 5.

2 QCA

The elementary units in QCA are cells. A quantum cell can be viewed as a square with four dots positioned at the corners of it [42]. The cell contains two extra mobile electrons which can quantum mechanically tunnel between dots within the cell but not cells. Due to Columbic repulsion, electrons always occupy the diagonal positions of square in the absence of any external influence. Thus, two possible polarization states, i.e. “P = −1” and “P = +1”, can be used to represent logic “0” and logic “1” respectively, as shown in Fig. 1a [30]. There is another type of QCA cells, i.e. rotated cells, which are able to achieve the same result, as illustrated in Fig. 1b. The difference between these two types of cells is the way of information transmission according to Columbic repulsion of electrons. Two neighboring standard cells will achieve same polarization, while rotated cells will get reverse polarization. The rotated cells can be used to realize coplanar wire-crossing with standard cells.

Fig. 1
figure 1

a Standard cells representing logic “0” and “1”. b Rotated cells representing logic “0” and “1”

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Two fundamental building blocks utilized as critical elements in QCA circuits are inverters and majority gates [35]. Since every QCA circuit can be implemented only using majority gates and inverters, efficient constructions of them are of great importance [31]. Figure 2 shows two frequently-used inverters.

Fig. 2
figure 2

Two typical inverters a Normal inverter. b Simplest inverter

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As depicted in Fig. 3a, a three-input majority gate is composed of five cells, with three input cells labeled as A, B, C, an output cell marked with F and the center one called device cell. The logic expression of it is F = M (A, B, C) = AB + BC + AC. The output of majority gate depends on the values of given inputs that occupy the major, just like a voter. Two-input “AND” gate or “OR” gate can be implemented by fixing a input into logic 0 or logic 1, respectively, as shown in Fig. 3b and c. The governing equations for “AND” and “OR” gates using 3-input majority gate are

$$ F=M\left(A,B,0\right)= AB $$
(1)
$$ F=M\left(A,B,1\right)=A+B $$
(2)
Fig. 3
figure 3

Logic gates and schematics a Three-input majority logic gate. b AND gate. c OR gate

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With “AND”, “OR” and inverters, any logic function can be realized.

On account of the important role of 3-input majority gate in QCA, different designs have been investigated over last years. Even though the three-input majority gate in Fig. 3a is the simplest and the most elementary one, missing of any one cell could lead to defects. In Fig. 4 six formerly proposed types of 3-input majority gates with fault tolerance are shown. Seeking for high degree of fault tolerance, low power dissipation, small area and number of cells is beneficial to future realization. These layouts are designed to balance above factors.

Fig. 4
figure 4

Previous fault-tolerant three-input majority gates a In [9]. b In [7]. c In [24]. d In [38]. e In [3]. f In [8]

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The logic function of five-input majority gate can be presented as:

$$ {\displaystyle \begin{array}{l}F=M\left(A,B,C,D,E\right)= ABC+ ABD+ ABE+ ACD\\ {}+ ACE+ ADE+ BCD+ BCE+ BDE+ CDE\end{array}} $$
(3)

where A, B, C, D and E are inputs and F is output.

Similar to 3-input majority gate, “AND” or “OR” gate can also be realized using 5-input majority gate. By forcing two of the five inputs’ polarizations to −1 or + 1, a 3-input “AND” or “OR” gate is formed. As yet, several implementations of 5-input majority gate have been reported, as shown in Fig. 5.

Fig. 5
figure 5

Previous fault-tolerant five-input majority gates a In [31]. b In [1]. c In [1]. d In [8]. e In [13]. f In [10]

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To minimize the power dissipation and hold the stable state of a QCA system consistently, the adiabatic switching mechanism, which is achieved by an external electric field, was introduced to solve the disadvantages of abrupt switching. This method is absolutely different from the clocking mechanism represented by the levels of voltage in CMOS-based circuits [19, 26, 41]. During the adiabatic switching, QCA system can always not only remain in instantaneous ground state, but also gain the least amount of power consumption. As shown in Fig. 6, the QCA clocking mechanism has four clocking zones, each of which is shifted from the previous one by 90° and has four phases: switch, hold, release and relax [43]. At the beginning, the cells in a system stand at the relax state because the inter-dot tunnel barriers are controlled at the lowest level. With the gradually increased barriers over switch phase and peaking in hold state, the polarizations of the cells will encode the binary information. During the release phase the tunnel barriers decrease and then reach the lowest value at relax state, which results in the complete loses of polarization information in each cell and preparation for the next cycle [22].

Fig. 6
figure 6

QCA four clocking phases within clock zones

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The equation for the instantaneous total power for a single QCA cell is written as

$$ {P}_{total}=\frac{dE}{dt}=\frac{\mathrm{\hslash}}{2}\frac{d\overrightarrow{\Gamma}}{dt}\cdot \overrightarrow{\lambda}+\frac{\mathrm{\hslash}}{2}\overrightarrow{\Gamma}\cdot \frac{d\overrightarrow{\lambda}}{dt}={P}_1+{P}_2 $$
(4)

where \( \overrightarrow{\Gamma} \) represents the real 3-D energy vector, \( \overrightarrow{\uplambda} \) is the coherence vector. The first term P 1 in above equation represents the difference (P in - P out ) between power input (P in ) and power output (P out ) and the power (P clock ) transferred from clocking signal. The second term P 2 gives the dissipated power (P diss ) that is exactly our concerned. In a quasi-infinite QCA array, P in achieved from left neighboring cell is equal to P out released power to the right neighboring cell. Moreover, in switch phase, with the increasing of inter-dot barrier, an amount of energy transfers from clocking to cell. Afterwards, most of the energy returns to clocking over lowering phase of barrier, which leads to a trivial power dissipation just named P diss .

3 Proposed Fault-Tolerant Designs and Applications

3.1 Proposed Designs

Fault-tolerant design in QCA is an essential subject for representation of suitable functionality of the circuits. Faults always occur without expectation during the assembly of a circuit, such as “misalignment” cells (quantum cells are shifted from their intended locations), “missing” cells (a quantum cell or several quantum cells is or are missing), “dislocation” cells (quantum cells are rotated relative to other cells in the array), all of which may result in the termination of function of circuits. In the paper, we focus on the defects of cell omissions. We propose two kinds of novel designs with respect to majority gates including 3-input and 5-input. Three-input majority gate in Fig. 7a and five-input majority gate in Fig. 7b are both based on a 5 × 5 module. Three-input majority gate is added two more inputs to implement five-input majority gate, which is convenient to achieve the transformation between these two gates.

Fig. 7
figure 7

Proposed fault-tolerant gates a Three-input majority gate. b Five-input majority gate

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In order to authenticate the correctness and the functionality of our proposed designs as well as previously related designs, QCADesigner version 2.0.3 [44] with the bistable approximation engine setup summarized in Table 1 is used.

Table 1 Parameters of bistable approximation
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3.2 Physical Proof for Five-Input Majority Gate with One Cell Omission

Since proposed five-input majority gate has 27 cells and any cell missing could lead to invalidation of the design, we should check all the faults that may occur in cells to verify the correctness of the scheme. Here, as shown in Fig. 8, we just prove one of the faults that occurs in the third row, forth column of the 5 × 5 module. Similarly, other faults can be proved as well. Five inputs of the majority gate are assumed to A = C = E = 1 and B = D = 0. Figure 8a and b denote two possible states of the output F, respectively. By calculating the total electrostatic energy of these two configurations, we can find the more stable one with lower kink energy level. The electrostatic energy between two electrons is calculated using Eq. (5).

$$ U=\frac{kq_1{q}_2}{r} $$
(5)

where U is electrostatic energy between two electrons, k is a constant, q 1 and q 2 are electron charges, and r is distance between these two electrons.

Fig. 8
figure 8

Two configurations with one cell omission of a The one value for x1 and y1. b The zero value for x2 and y2

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By computing the electrostatic energy between 14 electrons and x, y respectively, the total electrostatic energy can be achieved. Further detailed calculation is shown in Table 2. The eventual results (\( {U}_{T_1}<{U}_{T_2} \)) prove that the state in Fig. 8a is the more stable one. The functionality also can be verified using QCADesigner.

Table 2 Physical verification for radius of effect of 41 nm
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3.3 Application

As mentioned earlier, many QCA designs including adders, multipliers, multiplexers etc. can be implemented based on majority gates. Two novel one-bit full adders are displayed using three and five-input majority gates proposed, as shown in Fig. 9. Figure 9a displays a full-adder with three three-input majority gates. The other one shown in Fig. 9b is implemented using a three-input majority gate and a five-input majority gate. As illustrated in Fig. 10, the 4-bit carry flow adder, which has a 1.5 clock cycles, is implemented with coplanar crossovers in each unit. The n-bit carry flow adder can be constructed by cascading n proposed adders logically.

Fig. 9
figure 9

Proposed full adders with a Three three-input majority gates. b A three-input majority gate and a five-input majority gate

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Fig. 10
figure 10

Layout of the proposed 4-bit fault-tolerant adder with full adder P1

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4 Simulation Results

4.1 Three-Input Majority Gate

Table 3 displays the physical properties of three-input majority gates from different references. P denotes the proposed 3-input majority gate. Figure 11 depicts the bar-graphs of these comparisons.

Table 3 Physical properties of different three-input majority gates
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Fig. 11
figure 11

Three-input majority gate properties a Area. b Number of cells. c Fault tolerance. d Average energy dissipation. e Average leakage energy dissipation. f Average switching energy dissipation

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The gate in [26] has the smallest area, number of cells and energy dissipation in contrast with other gates. However, the design will lose its function when any one cell misses, namely the fault tolerance is 0, just as shown in Fig. 11c. P reaches 45.70% improvement in fault tolerance compared with [7] which can be viewed as a 3 × 3 tile. [38] is a grand design with largest area, maximum cell counts and highest average energy dissipation. The fault tolerance of it, 97.44%, is also the highest one. All the cases are correct except one on the left of the output cell F in the presence of single-cell omission. But limited by the manufacturing process of QCA technology, rotated cells used in the design are yet to come true, thereby making it unsuitable for practical realization. [3, 8] can be considered as a 4 × 7 module and a 3 × 5 module respectively. Fault tolerance of gate P leads to 25.91% and 34.92% improvements compared with that of them, respectively. The gate in [3], in terms of area, number of cells, energy dissipation and fault tolerance, always shows poorer performance in contrast with P. Fault tolerances of [9, 24] are almost equal to that of P. However, the superiority of gate P is that it can be extended into five-input majority gate by adding another two input cells as shown in Fig. 7b. Note that the structure of [9] is highly similar to that of P. But the simulation results with QCADesigner show erroneous outputs when adding two more inputs just like the way in Fig. 7.

Figure 11d-f illustrate the average energy, average leakage energy, average switching energy dissipation for the majority gates listed. Although the average energy dissipation of the proposed design is not the optimal, we can sum up that the three-input majority gate proposed in the paper displays significant practical value by comparisons and tradeoffs with previous proposed designs.

4.2 Five-Input Majority Gate

Table 4 displays the physical properties of different five-input majority gates. P is the proposed five-input majority gate. It is apparent that the fault tolerance of gate P is highest, achieving 47.62%, with relatively small area and number of cells. Figure 12 illustrate these characteristics lucidly. These characteristics make the design P a superior scheme. Although the structure of [31] is simplest, the fault tolerance of it is 0. Besides, the specificity of five inputs of design results in that the multi-layer structure must be needed if the design is employed to circuits. Analogous to above mentioned rotated cells, multi-layer structure is also a pitfall which has not been resolved so far. [1] in Fig. 5b, [1] in Fig. 5c and [8] can be regarded as a 3 × 3, 5 × 5 and 3 × 5 module respectively. As shown in Fig. 12c, the fault tolerance of [1] in Fig. 5b is 0. The structures of [1] in Fig. 5c and P are almost same apart from the positions of inputs and outputs. No matter from the view of area and number of cells or energy dissipation and fault tolerance, however, the design P surpasses the design in Fig. 5c. [8] has no significant difference compared with P in terms of area, number of cells and average energy dissipation. But the fault tolerance of it is far (35.12%) lower than that of P. [10, 13] both are magnificent structures with the bigger areas, the greater complexities, and the higher energy dissipations compared with other designs. However, neither [13] nor [10] can reach the same degree of fault tolerance of P, 3.17% and 13.53% lower than that of P respectively. Besides, the output cell of [10] is surrounded by other cells so that a multi-layer structure is needed to connect to circuits, which drastically reduces the feasibility of the scheme.

Table 4 Physical properties of different five-input majority gates
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Fig. 12
figure 12

Five-input majority gate properties a Area. b Number of cells. c Fault tolerance. d Average energy dissipation. e Average leakage energy dissipation. f Average switching energy dissipation

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4.3 Proposed Multi-Bit Adders

The correct simulation results using QCADesigner verify the functional behaviors of the proposed full adders, as shown in Fig. 13a and b, respectively.

Fig. 13
figure 13

Simulation results for full adders a P1. b P2

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In order to judge the merits of the work, comparisons are made with other one-bit full adders with respect to area, delay and fault tolerance. Here, the reason why we don’t involve energy dissipation is that QCAPro used in the analysis of energy dissipation can be used for single-layer designs only, while most full adders are multi-layer constructions.

Table 5 presents the comparisons of full adders. Proposed one-bit full adders shown in Fig. 9a and b are labeled as P1 and P2 respectively. The areas of P1 and P2, shown in Fig. 14a, are in the middle position. P1 and P2 are both using three clock phases shown in Fig. 14b. The fault tolerance of carry of P1 and P2 is also high, achieving 85.12% and 93.58% respectively, which is at a higher level, as shown in Fig. 14c. What’s more, as apparent from Fig. 14d, fault tolerance of sum of P1 and P2 is above all others, up to 59.5% and 41.28% respectively. Especially P1, the improvement of it is quite significant. Weighing up these factors, P1 and P2 are of great value.

Table 5 Physical properties of different full adders
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Fig. 14
figure 14

Full adder properties a Area. b Delay. c Fault tolerance-carry. d Fault tolerance-sum

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Table 6 lists the comparison for area of the multi-bit adders with several existing adders. To display the contrast effect of the area, the trend carves are made in Fig. 15a. Clock delay comparision is shown in Fig. 15b. Table 7 indicates the number of majority gates (MV), the number of inverters (INV), the number of crossings and the delay in various adders. The complexity of the adders is denoted as M + I + C, where M, I and C represent the number of majority gates, number of inverters, number of crossings, respectively, as demonstrated in Fig. 15c. Reference [28] described a criterion about the design of cost functions for QCA circuits as Cost = (M2 + I + C2) × T, where T(clock cycles) is the delay of one circuit. Figure 15d illustrates the comparison of the QCA cost listed in Table 7. From the trend curves of 12 multi-adders in Fig. 15, it is found to be that P surpasses the huge majority adders, ranking the fifth in area, the fourth in complexity and cost. Only the multi-bit adders in [6, 37] are always superior to the proposed one in these three aspects. The multi-adders in [35] is also better than P in terms of area and cost but the complexity. The value of our proposed multi-adders, however, is the implementation of crossing with coplanar types while adders in [6, 35, 37] are multi-layer crossings. Although the multi-layer designs will be area-efficient, they bring the fabrication difficulty at the same time because the multi-layer crossovers require at least three layers to design the circuits. Note that P shows the best performance in the present of all the coplanar crossings. Combined with forementioned analysis, the proposed adders will be better alternatives.

Table 6 Area of multi-bit adders (μm2)
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Fig. 15
figure 15

Comparison of the proposed multi-bit adders to previous adders in terms of a Area. b Delay. c Complexity. d Cost = (M2 + I + C2) × T

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Table 7 Summary of n-bit adders
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5 Conclusion

In this paper, we proposed a three-input majority gate based on a 5 × 5 module, the main method of module design methodology. Then a five-input majority gate was implemented with this gate by adding two more inputs on the basis of three-input majority gate, which distinguishes our designs from others. Both two designs showed better simulation results than prior work given area, number of cells, energy dissipation and fault tolerance into comprehensive consideration. Especially in fault tolerance, two designs are up to 80.95% and 47.62% respectively in the presence of one cell omission. One-bit full adders were implemented based on proposed three-input and five-input majority gates. Compared with existing designs, these two adders behave well, which verifies the practicability of the proposed majority gates at the same time. Moreover, to illustrate the applications of the proposed full adder and its scalability, the multi-bit designs were designed and also showed the better performance in terms of area, complexity and QCA cost in contrast to existing adders.