Controlling the ambipolar current in ultrathin SOI tunnel FETs using the back-bias effect

Abstract

A two-dimensional (2-D) technology computer-aided design (TCAD)-based simulation study of the back bias in the ultrathin silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) is presented. The transfer characteristics of a conventional TFET called the back-bias TFET (BB-TFET) depend on the back bias and the oxide thickness below the TFET epitaxial layer. The back bias affects the electric field at the source/channel and drain/channel junctions, hence both the ON-state current ($I_{\mathrm{ON}}$) and the ambipolar current ($I_{\mathrm{AMB}}$) reduce with a negative back-bias voltage. This reduction in $I_{\mathrm{ON}}$ is not desirable in a TFET, hence a modified TFET structure called the back-bias underdrain TFET (BBUD-TFET) is proposed. In the BBUD-TFET, the back bias is applied on a p-Si pocket placed under the drain region, which is isolated using an ultrathin oxide. The back bias in the proposed BBUD-TFET mainly affects the electric field at the drain/channel interface, having a negligible impact on the source/channel interface. The BBUD-TFET structure is analyzed with ${\mathrm{SiO}}_2$ or ${\mathrm{HfO}}_2$ as the gate oxide. In the BBUD-TFET with ${\mathrm{HfO}}_2$ as the gate oxide, the back bias completely suppresses the ambipolar current without reducing $I_{\mathrm{ON}}$. Furthermore, the oxide thickness and back-bias voltage are optimized for the BBUD-TFET structure. In this study, 2-D TCAD simulations are carried out to investigate and analyze the performance of the BB-TFET and BBUD-TFET.

1 Introduction

Tunneling field-effect transistors (TFETs) are gaining importance due to their suppressed subthreshold swing (SS). However, these devices also suffer from low ON-state current ($I_{\mathrm{ON}}$) and high leakage current due to ambipolar conduction, i.e., the conduction of current in the OFF-state ($I_{\mathrm{OFF}}$) [1,2,3]. This ambipolar effect is undesirable for the performance of inverter-based logical circuits [4]. On the other hand, the low $I_{\mathrm{ON}}$ increases the charging and discharging time, hence decreasing the speed of circuits and making the TFET unsuitable to meet International Technology Roadmap for Semiconductors (ITRS) requirements [4, 5]. Therefore, increasing $I_{\mathrm{ON}}$ while suppressing the ambipolar current ($I_{\mathrm{AMB}}$) are the main research challenges to make TFETs suitable for use in low-power circuit applications.

Several techniques have been reported in literature to suppress $I_{\mathrm{AMB}}$ in TFETs [5,6,7,8,9,10,11,12,13,14]. Hraziia et al. [5] utilized a gate–drain underlap region and a low-$\kappa$ spacer in the gate–drain region, and placed the contact at the top and bottom of the structure to reduce the ambipolar effect in double-gate (DG)-TFETs. The proposed structure delivered $I_{\mathrm{AMB}}$$\sim 10^{-14} \,{\mathrm{A}}/\upmu {\mathrm{m}}$ with $I_{\mathrm{ON}}$$\sim 10^{5} \,{\mathrm{A}}/\upmu {\mathrm{m}}$. Abdi and Kumar [6] proposed a gate-on-drain overlapping configuration in the DG-TFET to suppress $I_{\mathrm{AMB}}$. The overlapped gate-on-drain configuration suppresses $I_{\mathrm{AMB}}$ ($\sim 10^{-15} \,{\mathrm{A}}/\upmu {\mathrm{m}}$) with $I_\mathrm{ON}/I_{\mathrm{OFF}}$ of $\sim 10^{6}$. Raad et al. [7] reported a TFET structure with three gate materials in which the work function of the gate material on the source and drain sides was taken to be lower than the work function of the gate material in the middle. This device also employed a low-$\kappa$ dielectric on the drain side and a high-$\kappa$ dielectric on the source side. The reported TFET suppressed $I_{\mathrm{AMB}}$ to $\sim 10^{-16} \,{\mathrm{A}}/\upmu {\mathrm{m}}$ while improving $I_{\mathrm{ON}}$ to $\sim 10^{4} \, {\mathrm{A}}/\upmu {\mathrm{m}}$. Narang et al. [8] used a heterogeneous gate oxide with a gate–drain underlap configuration to minimize the $I_{\mathrm{AMB}}$ ($\sim 10^{-12} \, {\mathrm{A}}/\upmu {\mathrm{m}}$) of the device. Similarly, gate material engineering has been used to reduce the $I_{\mathrm{AMB}}$ of DG-TFETs by Nigam et al. [9]. They took a low-work-function gate material at the source and drain sides and a high-work-function gate material in the middle. This DG-TFET structure has been demonstrated to achieve a SS, $I_{\mathrm{OFF}}$, and $I_{\mathrm{ON}}$/$I_{\mathrm{OFF}}$ of 19 mV/dec, $2.29\times 10^{-17} \, {\mathrm{A}}/\upmu {\mathrm{m}}$, and $7.22\times 10^{11}$, respectively. Sharkar et al. [10] presented a drain engineering approach to lower the $I_{\mathrm{AMB}}$ of the SOI TFET. Those authors established that the relative increase in thickness of the low-doping drain region over the high-doping drain region increased the tunneling width, leading to an appreciable reduction in $I_{\mathrm{AMB}}$ ($\sim 10^{-15} \, {\mathrm{A}}/\upmu {\mathrm{m}}$). Singh and Kondekar [11] proposed an electrostatically doped ferroelectric Schottky barrier TFET (ED-FE-SB TFET) by analyzing the effect of negative capacitance. The proposed device showed SS, $I_{\mathrm{AMB}}$, and $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ of 56 mV/dec, $8.74\times 10^{-9} \, {\mathrm{A}}/\upmu {\mathrm{m}}$, and $6.74\times 10^{7}$, respectively. Rahimian and Fathipour [12] demonstrated an asymmetric junctionless nanowire (AJN) TFET having an $n^+$ pocket at the source. The AJN TFET provided SS, $I_{\mathrm{AMB}}$, and $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ of 38 mV/dec, $7.5\times 10^{-12} \, {\mathrm{A}}/\upmu {\mathrm{m}}$, and $3.87\times 10^{9}$, respectively. Ashita et al. [13] reported an electron–hole bilayer (EHB) TFET with double dielectric pockets in the source and drain. The proposed structure achieved an SS, $I_{\mathrm{OFF}}$, and $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ of 17.75 mV/dec, $9.09\times 10^{-17} \, {\mathrm{A}}/\upmu {\mathrm{m}}$, and $2.55\times 10^{9}$, respectively. Further, Bal et al. [14] proposed a dual-material gate (DMG) TFET and studied its energy band modulation profile. The DMG TFET provided SS, $I_{\mathrm{OFF}}$, and $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ of 17 mV/dec, $3\times 10^{-13} \,{\mathrm{A}}/\upmu {\mathrm{m}}$, and $6.67\times 10^{9}$, respectively.

The effect of back biasing on the performance of TFETs has also been studied in literature [15,16,17,18]. Guo et al. [15] improved the $I_{\mathrm{ON}}$/$I_{\mathrm{OFF}}$ ratio and SS of the SOI TFET through back biasing, including the effect of variation in the source and drain doping underneath the gate electrode. A similar study was reported on the germanium-on-insulator (GOI) TFET by Matheu et al. [16]. Sahay and Kumar [17] proposed the inclusion of a heterodielectric box (HDB) over a heavily doped grounded substrate at the channel/drain interface with ${\mathrm{SiO}}_2$ under the source/channel interface and a high-$\kappa$ (${\mathrm{HfO}}_2$) dielectric under the drain region. Those authors reduced $I_{\mathrm{AMB}}$ to $\sim 10^{-16} \, {\mathrm{A}}/\upmu {\mathrm{m}}$ due to the increased tunneling width at the drain/channel interface and improved the $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ ratio to $\sim 10^{10}$. Further, Wang et al. [18] presented an ultrathin-body GeSn TFET with a back gate bias to improve the $I_{\mathrm{ON}}$, SS, and $I_{\mathrm{AMB}}$.

Note that the techniques applied to suppress $I_{\mathrm{AMB}}$ in the cited articles also degrade the $I_{\mathrm{ON}}$ of the TFET, resulting in a low $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ ratio. Therefore, it is desirable to design a TFET structure that can provide a lower $I_{\mathrm{AMB}}$ but higher $I_{\mathrm{ON}}$ simultaneously. In this work, the conventional TFET with a back bias applied on the p-Si layer over the buried oxide (BOX) and under the device is called the BB-TFET. In the BB-TFET structure, $I_{\mathrm{AMB}}$ is completely suppressed and the SS is improved. However, $I_{\mathrm{ON}}$ is also reduced in the BB-TFET structure. To overcome this reduction in $I_{\mathrm{ON}}$, the back-bias underdrain TFET (BBUD-TFET) is proposed, in which the back biasing is applied on the p-Si pocket under the drain region. The BBUD-TFET achieves complete elimination of $I_{\mathrm{AMB}}$ as well as a significant improvement in SS and $I_{\mathrm{ON}}$. The performance of the BB-TFET and BBUD-TFET is investigated using 2-D TCAD simulations in the ATLAS device simulator [19].

Fig. 1

The calibration of the simulation setup using a prefabricated TFET [20]

2 The simulation setup

The BB-TFET and BBUD-TFET structures are implemented in the TCAD simulator by invoking suitable models. In this study, the Lombardi mobility (CVT) model is used to include the effect of the concentration- and field-dependent mobility. The Shockley–Read–Hall (SRH) model is chosen to incorporate the phenomenon of carrier recombination. The bandgap narrowing (BGN) model is selected to include the effect of the high concentration in the bandgap. Fermi–Dirac statistics is employed to incorporate certain properties of the highly doped region. Moreover, the nonlocal band-to-band tunneling model is used to simulate the tunneling effect in the devices. To calibrate the simulation setup, a prefabricated TFET [20] is implemented and simulated using the above-mentioned models. Figure 1 shows a comparison of the simulated and fabricated transfer characteristics of the published TFET structure, revealing a good match between the simulated and experimental results.

Fig. 2

A schematic cross-sectional view (not to the scale) of the BB-TFET

2.1 The device structures, results, and discussion

A cross-sectional view of the BB-TFET structure on SOI is shown in Fig. 2. The structure consists of an ultrathin ${\mathrm{SiO}}_2$ layer over the p-Si region placed on the BOX. The various device structural parameters used in this study are: gate oxide (GOX) thickness ($T_{\mathrm{OX}}) = 1 {\mathrm { nm}}$, channel length ${(L)} = 50\, \hbox{nm}$, channel thickness ($T_{\mathrm{si}}) = 10\, \hbox{nm}$, $p^+$-source region doping $= 1\times 10^{20} \, {\mathrm{cm}}^{-3}$, n-channel doping $= 1\times 10^{17} \, {\mathrm{cm}}^{-3}$, $n^+$-drain region doping $= 5\times 10^{18} \, {\mathrm{cm}}^{-3}$, p-Si layer doping $= 1\times 10^{15} \, {\mathrm{cm}}^{-3}$, and the work function of the gate material $= 4.7\, \hbox{eV}$, while the dimension of the ultrathin ${\mathrm{SiO}}_2$ ($T_{\mathrm{OB}}$) is varied from 2 to 10 nm. A negative back-bias voltage ($V_{\mathrm{BB}}$) is applied to the p-Si layer from the drain to source uniformly. The application of $V_{\mathrm{BB}}$ reduces the electric field at the drain/channel and source/channel interfaces. Note that the electric field at the drain/channel interface is responsible for the $I_{\mathrm{AMB}}$ in the TFET structure. Therefore, the reduction in the electric field at this interface leads to suppression of $I_{\mathrm{AMB}}$. The $I_{\mathrm{ON}}$ of the device depends on the tunneling of carriers at the source/channel interface, hence a reduction in the electric field at this interface results in a degradation in $I_{\mathrm{ON}}$.

Fig. 3

The transfer characteristics of the BB-TFET at different back-bias voltages

The effect of $V_{\mathrm{BB}}$ on the transfer characteristics of the BB-TFET is shown in Fig. 3. Note from this figure that the application of a negative $V_{\mathrm{BB}}$ entirely suppresses the $I_{\mathrm{AMB}}$ but also decreases the $I_{\mathrm{ON}}$ of the device. This figure reveals that, when $V_{\mathrm{BB}}$ is increased from −1 to −2 V, the $I_{\mathrm{AMB}}$ in the device is completely suppressed but the $I_{\mathrm{OFF}}$ increases. In the OFF-state condition ($V_{\mathrm{GS}}= 0\, \hbox{V}$), the current in the BB-TFET is obtained as $1.49\times 10^{-11}\, \hbox{A}/\upmu \hbox {m}$, $1.5\times 10^{-17}\, \hbox{A}/\upmu \hbox {m}$, and $3.8\times 10^{-17}\, \hbox{A}/\upmu \hbox {m}$ at $V_{\mathrm{BB}} = 0\, \hbox{V}$, $V_{\mathrm{BB}} = -1\, \hbox{V}$, and $V_{\mathrm{BB}} = -2\, \hbox{V}$, respectively. Further, changing $V_{\mathrm{BB}}$ from −1 to −2 V significantly reduces the $I_{\mathrm{ON}}$. In the ON-state condition ($V_{\mathrm{GS}}= 1.2\, \hbox{V}$), the $I_{\mathrm{ON}}$ is found to be $1.64\times 10^{-6}\, \hbox{A}/\upmu \hbox {m}$, $8.8\times 10^{-7}\, \hbox{A}/\upmu \hbox {m}$, and $3.76\times 10^{-8}\, \hbox{A}/\upmu \hbox {m}$ at $V_{\mathrm{BB}} = 0\, \hbox{V}$, $V_{\mathrm{BB}} = -1\, \hbox{V}$, and $V_{\mathrm{BB}} = -2\, \hbox{V}$, respectively. For $V_{\mathrm{BB}}= -1\, \hbox{V}$, the SS and threshold voltage ($V_{\mathrm{t}}$) are calculated as 17.5 mV/dec and 0.84 V, respectively.

The reduction in $I_{\mathrm{AMB}}$ and $I_{\mathrm{ON}}$ with $V_{\mathrm{BB}}$ can be better explained based on the electric field distribution in the structure.

The $I_{\mathrm{ON}}$ and $I_{\mathrm{AMB}}$ of the TFET depend on the band-to-band tunneling (BTBT) at the source/channel and drain/channel junctions, respectively [21]. The BTBT rate ($G_{\mathrm{BTBT}}$) depends on the local electric field ($\varepsilon$) at the junction according to the equation [22]

$$\begin{aligned} G_{\mathrm{BTBT}} = A\varepsilon ^\sigma {\mathrm{exp}}\left( -\frac{B}{\varepsilon }\right), \end{aligned}$$

(1)

where A is a constant related to the effective electron mass, B is the tunneling probability constant, and $\sigma$ is the transition constant. The 2-D electric field distribution in the BB-TFET with and without back bias in the OFF-state is shown in Fig. 4. As depicted in Fig. 4b, in the OFF-state ($V_{\mathrm{GS}} = 0\, \hbox{V}$), the application of the back bias drastically reduces the electric field at the drain/channel interface compared with Fig. 4a. This reduction in the electric field at the drain/channel junction leads to complete suppression of $I_{\mathrm{AMB}}$. Note that, although $I_{\mathrm{AMB}}$ is suppressed with the back bias, $I_{\mathrm{OFF}}$ increases as $V_{\mathrm{BB}}$ is increased from 1 to −2 V due to the higher electric field in the drain region.

Furthermore, the effect of the back bias on the transfer characteristics of the BB-TFET can be explained based on the tunneling probability. The tunneling probability ($T_{\mathrm{WKB}}$) in a TFET is given by the Wentzel–Kramer–Brillouin (WKB) approximation, which is written as [2, 23]:

$$\begin{aligned} T_{\mathrm{WKB}} \approx {\mathrm{exp}}\left( -\frac{4\lambda \sqrt{2m^*}\sqrt{E_{\mathrm{g}}^3}}{3q\hbar (E_{\mathrm{g}}+\varDelta \phi )}\right), \end{aligned}$$

(2)

where $\lambda$ and $\varDelta \phi$ denote the tunneling width and the effective tunneling energy range, respectively (as shown in Fig. 5). The effective electron mass is $m^*$, and the bandgap energy is $E_{\mathrm{g}}$.

Fig. 4

The electric field distribution in the BB-TFET in the OFF-state at a$V_{\mathrm{BB}} = 0\, \hbox{V}$ and b$V_{\mathrm{BB}} = -2$ V

Figure 5 shows the energy band diagram of the BB-TFET at different $V_{\mathrm{BB}}$ values along the cut line $C_1$ in the OFF-state. This figure reveals a significant overlap between the conduction band (CB) and valance band (VB) at the drain/channel junction without a back bias ($V_{\mathrm{BB}} = 0\, \hbox{V}$). This increases the $T_{\mathrm{WKB}}$ at the drain/channel interface, leading to a large $I_{\mathrm{AMB}}$. On the other hand, with the application of the back bias, there is no overlap between the CB and VB at the drain/channel interface, hence the $I_{\mathrm{AMB}}$ is completely eliminated.

Fig. 5

The energy band diagram along the cut line $C_1$ in the BB-TFET with ${\mathrm{SiO}}_2$ as the GOX in the OFF-state

Fig. 6

The electric field distribution in the BB-TFET in the ON-state at a$V_{\mathrm{BB}} = 0\, \hbox{V}$ and b$V_{\mathrm{BB}} = -2\, \hbox{V}$

Fig. 7

The energy band diagram along the cut line $C_2$ in the BB-TFET with ${\mathrm{SiO}}_2$ as the GOX in the ON-state

In the ON-state ($V_{\mathrm{GS}}=1.2\, \hbox{V}$), the effect of the back bias on the electric field and energy band diagram at the source/channel interface is illustrated in Figs. 6 and 7. It is clear from Fig. 6a, b that the back bias also reduces the electric field significantly at the source/channel junction. This decrease in the electric field at the source/channel junction degrades the $I_{\mathrm{ON}}$ of the BB-TFET. Meanwhile, it is evident from the energy band diagram (Fig. 7) that the $\lambda$ remains almost unaffected by the back bias, while $\varDelta \phi$ reduces with an increase in the negative $V_{\mathrm{BB}}$. As observed from this figure, the reduction in $\varDelta \phi$ is small at $V_{\mathrm{BB}} = -1\, \hbox{V}$ as compared with at $V_{\mathrm{BB}} = -2\, \hbox{V}$. Therefore, the $I_{\mathrm{ON}}$ decreases by a small amount at $V_{\mathrm{BB}} = -1\, \hbox{V}$ when compared with $I_{\mathrm{ON}}$ without a back bias. On the other hand, the $I_{\mathrm{ON}}$ decreases significantly at $V_{\mathrm{BB}} =-2\, \hbox{V}$ due to the large reduction in $\varDelta \phi$.

Fig. 8

A schematic cross-sectional view (not to the scale) of the BBUD-TFET

Although the back bias in the BB-TFET suppresses the ambipolar current completely at $V_{\mathrm{BB}} = -1\, \hbox{V}$, it also degrades the $I_{\mathrm{ON}}$. This is due to the fact that the negative back bias reduces the $\varDelta \phi$ at the drain/channel and source/channel junctions. To overcome this effect of $V_{\mathrm{BB}}$ on the $I_{\mathrm{ON}}$ in the BB-TFET, the back bias can be applied under the drain region only, resulting in the new structure called the BBUD-TFET as proposed in Fig. 8. In this structure, a p-Si region is introduced below the drain, being separated from the $n+$ drain by an oxide with thickness of $T_{\mathrm{OB}}$. The $V_{\mathrm{BB}}$ is applied to the p-Si region, which will mainly affect the drain/channel junction but with a negligible effect on the source/channel interface. The other structural parameters of the BBUD-TFET remain identical to those of the BB-TFET to enable comparison of their performance parameters.

Fig. 9

The fabrication steps for the BBUD-TFET structure

The fabrication steps for the BBUD-TFET are illustrated in Fig. 9. Initially, an SOI wafer with the required n-channel concentration is taken. Photoresist (PR) is applied over the whole wafer then patterned as shown in Fig. 9a. Reactive-ion etching (RIE) is used to remove the desired Sin-epitaxial layer as well as ${\mathrm{SiO}}_2$ (BOX) layer to obtain the trench structure shown in Fig. 9b. The RIE process offers a high selectivity ratio of 35:1 for both Si and ${\mathrm{SiO}}_2$. In the next step, p-type Si is grown in the trench, as shown in Fig. 9c. The growth of Si over ${\mathrm{SiO}}_2$ is achieved using a chemical vapor deposition (CVD) process in which the epitaxial layer is seeded through an opening in the ${\mathrm{SiO}}_2$ surface. This growth is carried out using a mixture of SiH₂Cl₂, ${\mathrm{H}}_2$, and HCl in the temperature range of 1050 to 1200 °C. To avoid problems related to the occurrence of silicon nucleation over ${\mathrm{SiO}}_2$, which would introduce defects into the overgrowing Si epitaxial layer, the growth process is carried out in a series of growth/etch steps [24]. As illustrated in Fig. 9d, a ${\mathrm{SiO}}_2$ layer with thickness $T_{\mathrm{OB}}$ is deposited over the p-Si in the trench. In the next step, $n^+-Si$ is grown over the ${\mathrm{SiO}}_2$ to form the drain region of the TFET, as shown in Fig. 9e. Finally, as shown in Fig. 9f, the proposed BBUD-TFET structure is obtained using the same fabrication steps as applied for a conventional TFET [25, 26]. Note that, in the BBUD-TFET, the p-Si region is aligned with the $n^+$ drain region, which is advantageous from the fabrication point of view.

Fig. 10

The transfer characteristics of the BBUD-TFET

Fig. 11

The OFF-state electric field distribution in the a BB-TFET and b BBUD-TFET with ${\mathrm{SiO}}_2$ as the GOX

The transfer characteristics of the BBUD-TFET for different values of $V_{\mathrm{BB}}$ are plotted in Fig. 10. Note from this figure that the OFF-state characteristics of the BBUD-TFET are identical to those of the BB-TFET. However, the effect of $V_{\mathrm{BB}}$ on $I_{\mathrm{ON}}$ is significantly reduced in the BBUD-TFET. Therefore, the $I_{\mathrm{ON}}$ in the BBUD-TFET is higher than that in the BB-TFET. At $V_{\mathrm{BB}} = -1\, \hbox{V}$, the $I_{\mathrm{ON}}$ and $I_{\mathrm{OFF}}$ of the BBUD-TFET are found to be $1.71\times 10^{-6}\, \hbox{A}/\upmu \hbox {m}$ and $1.54\times 10^{-17}\, \hbox{A}/\upmu \hbox {m}$, respectively. Moreover, at $V_{\mathrm{BB}} = -1\, \hbox{V}$, the SS and $V_{\mathrm{t}}$ are obtained as 15.2 mV/dec and 0.79 V, respectively.

Fig. 12

The OFF-state energy band diagram along the cut line $C_1$ in the BB-TFET and BBUD-TFET with ${\mathrm{SiO}}_2$ as the GOX

Fig. 13

The ON-state electric field distribution in the a BB-TFET and b BBUD-TFET with ${\mathrm{SiO}}_2$ as the GOX

It is clear from Fig. 11a, b that the electric field contours at the drain/channel junction are almost identical for both structures. This fact is also illustrated by the energy band diagram shown in Fig. 12, in which there is negligible change in $\lambda$ and $\varDelta \phi$. Therefore, the OFF-state characteristics of the BB-TFET and BBUD-TFET are identical.

Figure 13a and b show the effect of $V_{\mathrm{BB}}$ on the electric field distribution in the BB-TFET and BBUD-TFET in the ON-state condition, respectively. It is observed from this figure that the electric field at the source/channel junction in the BBUD-TFET is higher than that in the BB-TFET with a back bias. Furthermore, it is clear from the energy band diagram shown in Fig. 14 that the $\lambda$ decreases while $\varDelta \phi$ increases with the back bias in the BBUD-TFET in comparison with BB-TFET. Therefore, the effect of $V_{\mathrm{BB}}$ at the source/channel junction of the BBUD-TFET is lesser compared with in the BB-TFET, hence the $I_{\mathrm{ON}}$ in the BBUD-TFET is higher than that in the BB-TFET.

Fig. 14

The ON-state energy band diagram along the cut line $C_1$ in the BB-TFET and BBUD-TFET with ${\mathrm{SiO}}_2$ as the GOX

Fig. 15

The transfer characteristics of the BBUD-TFET with ${\mathrm{HfO}}_2$ as the GOX

Moreover, the transfer characteristics of the BBUD-TFET can be further improved by using a high-$\kappa$ dielectric material as the GOX [27, 28]. In this work, the BBUD-TFET structure is also simulated with the replacement of ${\mathrm{SiO}}_2$ by ${\mathrm{HfO}}_2$ as the GOX. Note that the thickness of the ${\mathrm{HfO}}_2$ is kept the same as that of the ${\mathrm{SiO}}_2$ (1 nm). Figure 15 shows the transfer characteristics of the BBUD-TFET with ${\mathrm{HfO}}_2$ as the GOX. As shown in this figure, without a back bias ($V_{\mathrm{BB}}=0$), both the $I_{\mathrm{ON}}$ and $I_{\mathrm{AMB}}$ of the BBUD-TFET with ${\mathrm{HfO}}_2$ as the GOX are substantially higher than for the BBUD-TFET with ${\mathrm{SiO}}_2$ as the GOX (as shown in Fig. 10). However, the $V_{\mathrm{BB}}$ in this device also results in complete elimination of the $I_{\mathrm{AMB}}$ with only slight degradation in $I_{\mathrm{ON}}$. It is observed that, for $V_{\mathrm{BB}}=-1\, \hbox{V}$, the device exhibits the lowest $I_{\mathrm{OFF}}$ without any compromise in $I_{\mathrm{ON}}$. At $V_{\mathrm{BB}} = -1\, \hbox{V}$, the $I_{\mathrm{ON}}$ and $I_{\mathrm{OFF}}$ of the BBUD-TFET with ${\mathrm{HfO}}_2$ as the GOX are found to be $3.13\times 10^{-4}\, \hbox{A}/\upmu \hbox {m}$ and $1.77\times 10^{-17}\, \hbox{A}/\upmu \hbox {m}$, respectively. Moreover, at $V_{\mathrm{BB}} = -1\, \hbox{V}$, the SS and $V_{\mathrm{t}}$ are obtained as 7.6 mV/dec and 0.42 V, respectively.

Fig. 16

The OFF-state electric field distribution in the BBUD-TFET with a${\mathrm{SiO}}_2$ and b${\mathrm{HfO}}_2$ as the GOX

Fig. 17

The OFF-state energy band diagram along the cut line $C_1$ in the BBUD-TFET with ${\mathrm{SiO}}_2$ and ${\mathrm{HfO}}_2$ as the GOX

This improvement in the transfer characteristics of the BBUD-TFET can be explained with the help of the electric field distribution and energy band diagram with ${\mathrm{SiO}}_2$ and ${\mathrm{HfO}}_2$ as the GOX (Figs. 16, 17). As observed from Fig. 16, the electric field at both junctions near the gate is higher in the case of ${\mathrm{HfO}}_2$. On the other hand, the electric field is identical in both structures near the channel/${\mathrm{SiO}}_2$ interface due to the back-bias effect. The cut line $C_1$ is taken at the drain/channel interface near to the back surface. The energy bands overlap with each other in both cases, hence the $I_{\mathrm{OFF}}$ is identical in both devices. The electric field contours and energy band diagram in the BBUD-TFET in the ON-state are shown in Figs. 18 and 19. From Fig. 18, it is observed that the electric field at the source/channel interface in the BBUD-TFET is higher with ${\mathrm{HfO}}_2$ as compared with ${\mathrm{SiO}}_2$. This enhanced electric field at the source/channel junction results in greater energy band bending, as illustrated in Fig. 19.

Fig. 18

The ON-state electric field distribution in the BBUD-TFET with a${\mathrm{SiO}}_2$ and b${\mathrm{HfO}}_2$ as the GOX

Fig. 19

The ON-state energy band diagram along the cut line $C_1$ in the BBUD-TFET with ${\mathrm{SiO}}_2$ and ${\mathrm{HfO}}_2$ as the GOX

3 The optimization of the BBUD-TFET

Fig. 20

The effect of T_OB on the transfer characteristics of the BBUD-TFET with ${\mathrm{HfO}}_2$ as the GOX

Fig. 21

The variation in $I_{\mathrm{ON}}$ and the $I_{\mathrm{ON}}$/$I_{\mathrm{OFF}}$ ratio with $T_{\mathrm{OB}}$ for the BBUD-TFET with ${\mathrm{HfO}}_2$ as the GOX

Fig. 22

The optimized values of $T_{\mathrm{OB}}$ for different values of $V_{\mathrm{BB}}$ for the BBUD-TFET with ${\mathrm{HfO}}_2$ as the GOX

Figure 20 shows the transfer characteristics of the BBUD-TEFT with ${\mathrm{HfO}}_2$ as the GOX for different values of $T_{\mathrm{OB}}$ at $V_{\mathrm{BB}}$ = −1 V. Note from this figure that $I_{\mathrm{OFF}}$ decreases with an increase in $T_{\mathrm{OB}}$ up to 6 nm. Thereafter, $I_{\mathrm{AMB}}$ increases due to the reduced control of the $V_{\mathrm{BB}}$ over the electric field at the drain/channel junction. On the other hand, the $I_{\mathrm{ON}}$ increases continuously with an increase in $T_{\mathrm{OB}}$ because, for higher values of $T_{\mathrm{OB}}$, the effect of $V_{\mathrm{BB}}$ on the source/channel junction is diminished. To determine the optimum value of $T_{\mathrm{OB}}$ at $V_{\mathrm{BB}} = -1\, \hbox{V}$, the $I_{\mathrm{ON}}$ and $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ ratio are plotted in Fig. 21, clearly revealing that the $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ ratio is maximum for $T_{\mathrm{OB}} = 6$ nm. Therefore, the optimum value of $T_{\mathrm{OB}}$ is taken as 6 nm for $V_{\mathrm{BB}} = -1\, \hbox{V}$. Similarly, the optimum value of $T_{\mathrm{OB}}$ is found for other values of $V_{\mathrm{BB}}$ and plotted in Fig. 22. The optimum value of $T_{\mathrm{OB}}$ increases for higher values of $V_{\mathrm{BB}}$.

The performance parameters of the BB-TFET and BBUD-TFET structures are compared with other TFETs reported in literature in Table 1. It is evident that the BBUD-TFET with ${\mathrm{HfO}}_2$ as the GOX provides a $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ ratio of 1.77$\times 10^{13}$, which is significantly higher than that ($\sim 10^{2}$) of the reported dual material control gate (DMCG)-TFET structure [9]. Further, it is also observed that the BBUD-TFET with ${\mathrm{HfO}}_2$ as the GOX provides the lowest value of SS when compared with the other reported structures.

Table 1 A comparison of the performance parameters of the BB-TFET and BBUD-TFET structures with other reported TFETs

4 Conclusions

The effect of the back-bias voltage on the transfer characteristics of the BB-TFET and BBUD-TFET is evaluated and investigated using 2-D TCAD simulations. The back-bias voltage in the BB-TFET reduces the electric field at both the source/channel and drain/channel junctions, which leads to a reduction in the tunneling probability and hence a substantial reduction in the $I_{\mathrm{AMB}}$ and $I_{\mathrm{ON}}$ of the device. At $V_{\mathrm{BB}} = -1\, \hbox{V}$, the $I_{\mathrm{ON}}$ and $I_{\mathrm{OFF}}$ of the BB-TFET are found to be 2.24 $\times 10^{-7}\, \hbox{A}/\upmu \hbox {m}$ and $1.18\times 10^{-17}\, \hbox{A}/\upmu \hbox {m}$, respectively. To overcome the effect of $V_{\mathrm{BB}}$ at the source/channel junction in the BB-TFET, the conventional TFET structure is modified to the BBUD-TFET, in which the $V_{\mathrm{BB}}$ affects mainly the drain/channel junction. The BBUD-TFET is then studied with ${\mathrm{SiO}}_2$ or ${\mathrm{HfO}}_2$ as the GOX. The simulation results reveal that the BBUD-TFET with ${\mathrm{HfO}}_2$ as the GOX offers complete elimination of $I_{\mathrm{AMB}}$ but with no effect on $I_{\mathrm{ON}}$. At $V_{\mathrm{BB}} = -1\, \hbox{V}$, the $I_{\mathrm{ON}}$ and $I_{\mathrm{OFF}}$ of the BBUD-TFET with ${\mathrm{HfO}}_2$ as the GOX are found to be $3.13\times 10^{-4}\, \hbox{A}/\upmu \hbox {m}$ and $1.77\times 10^{-17}\, \hbox{A}/\upmu \hbox {m}$, respectively. The $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ ratio of the BBUD-TFET with ${\mathrm{HfO}}_2$ as the GOX is found to be $1.77\times 10^{13}$, which is much higher than for other TFET structures. With a back bias in the ultrathin SOI TFET, the $T_{\mathrm{OB}}$ and $V_{\mathrm{BB}}$ are two important parameters to control the $I_{\mathrm{AMB}}$ in the device. The improvement in the performance parameters of the BB-TFET and BBUD-TFET can be explained with the help of the electric field contours and energy band diagrams of the devices. The proposed device exhibits superior performance parameters as compared with other TFET structures reported in literature. Thus, the proposed BBUD-TFET is an attractive candidate for use in low-power switching applications.