1 Introduction

During the last thirty years due to the needs of tremendous operational speed and processing a number of data, many new ideas are being floated in the field of computing. These include exploration of implementation of optical processor for switches in one hand and on the other hand the logical development from binary to multivalued logic are also being included in their field of activities. Though the major attraction for optical processors lies in the parallel operation but it was also felt that it is possible to implement multivalued logic in optical system using the polarization states of light beam along with the presence or absence of light [1]. The parallelism of optical beam could not be properly utilized using cascaded single-bit operating units therefore a signed digit number system was initiated with the pioneering works of Avizienis [2]. The carry free operation was also suggested using a modified signed digit [3–5] or modified trinary [6] system. The demand for implementations of such gates has also extended the activities in the field [7–12].

However, Lukasiewicz [13] who initiated the use of ternary logic based on three states has modified it later [14–17] with an idea that four states logic is a much better proposition. This paper is an extension of the modified trinary system [18–21] to a quadruple-valued logic system along with its implementation. In the implementation the different states are represented with a dibit representation using presence and absence of light of two orthogonal polarization states of light beam.

2 Quadruple valued logic representations and the system

The four-state representations of the quadruple valued logic system may be classified as the true, partly true, partly false and the false. In this case we have considered these four states explicitly as {0,1,2,3} and their di-bit representations as {00,01,10,11}. It is to be noted here that the four valued system with states {0,1,2,3} does not satisfy the basic field conditions whereas as a dibit representation of the form 00→0, 01→1, 10→2 and 11→3 may be used to represent a four valued logic where the basic two valued logic are applicable. As four is not a prime number, it cannot be considered as a field nevertheless this can be included in Galois Field GF(k r), where k is a prime number and r is a positive integer [22]. The logical states, their representations and corresponding dibit representations and the state of polarization is given in the Table 1.

Table 1 Quadruple-valued logic system
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3 Truth tables based on di-bit representation

The basic logical operations with dibit representation as mentioned in the earlier section may be expressed in the following fashion. In the present system the normal logical gates e.g., OR, AND, NOT, XOR, NAND, NOR and XNOR may be represented bit-wise. The truth table for these conventional bit wise logic gates are represented in Table 2.

Table 2 Truth tables for (a) OR, (b) AND, (c) NOT, (d) XOR, (e) NAND, (f) NOR and (g) XNOR gates
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It is interesting to note at this point that the addition and multiplication are not simple bit-wise XOR and AND operations, these operations are performed in bit serial fashion. This is apparent from the truth table given in Table 3. In binary system the XOR gate is also the modulo-2 gate and thus gives the addition, which is not true in case of dibit logic gates based on binary logic for each bit as in such cases, XOR operation is not the modulo-4 gate. Similarly, AND gate defined in Table 2 does not represent either the multiplication logic or generates the carry bit. Then four-valued logic system calls for a more number of gates and the mathematical equations are to be developed using bit serial fashion. The most important mathematical gates i.e., the addition gate and the multiplication gates may be defined in the following fashion.

Table 3 Truth tables for (a) addition and (b) multiplication
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For addition gate,

Similarly, the multiplication gate

The corresponding truth tables for the addition and multiplication are given in Tables 3(a) and 3(b) respectively. It is to be noted that addition is obtained by modulo-4 gate.

Thus the logical and mathematical operations over GF(2m) field can be subdivided in different classes. Some operations are bit-wise but for others it is in bit serial fashion, in which some information are carried over from the results of earlier bit.

4 Implementation of quadruple valued logics using opto-electronics systems

In optics, using two orthogonal states of polarization as well as that of absence and presence of light at a time we can generate four-state logic system using dibit representation. In this chapter the logic used has been extended to incorporate dibit representation in quadruple valued system.

4.1 The basic building block

The basic building block to implement the logical operations in quadruple valued logic system is shown in Fig. 1. Light from a laser source L after passing through the polarizer P is polarized at an angle 45° with respect to the two crystal axes and incident on the savart plate S1 as shown in Fig. 1. The light incident on S1 is splitted into two orthogonal components and comes out of S1 with a spatial shift between them. The electrically addressable negative SLMs—P1 and P2 are then used for the controlling of two components of inputs beam. The nature of the negative SLM is such that it is transparent when there is no electric voltage applied on it and it becomes opaque when an electric voltage is applied on it. The property of positive SLM is just reverse. Hence the input may be considered as in the form of dibit (two bits) representation.

Fig. 1
figure 1

Basic building block

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The second savart plate S2 is then re-unites the two polarized beam for further operations. Various logic gates as mentioned in Table 2 and Table 3 may be implemented by combining this very basic module.

4.2 OR gate

The circuit diagram of OR Gate is shown in Fig. 2. The polarized parallel beam coming from the Laser source L through polarizer P is incident on the beam splitter BS1—where it is splitted into two directions as shown. One part is incident on the savart plate S1 and the other part on the mirror M1. The savart plate S1 splits the beam into two orthogonal components—the p-polarization and the s-polarization. The input A (combination of A1 and A2) controls the positive SLMs P1 and P2 and accordingly the p-polarization and s-polarization come out of P1 and P2 and they recombined by the savart plate S2 and incident on the beam splitter BS2. On the other hand the ray reflected by the mirror M1 is incident on the savart plate S3 and by similar process it is also spatially modulated by the positive SLMs P3 and P4 depending on the input B (combinations of B1 and B2). Then the rays are re-united again by S4 and after reflection by the mirror M2 it is incident on the beam splitter BS2. The output finally comes out from BS2. We are considering the beams which are orthogonally polarized to each other so there will be incoherent superposition of intensity thus phase shift does not produce any effect.

Fig. 2
figure 2

OR gate

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For example, say A=00 (i.e. A1=0 and A2=0), then the components of the light beam splitted by S1 will be obstructed by P1 and P2 and hence the output of S2 will be dark i.e., absence of p and s-polarizations. Say, the second input B=11 (i.e., B1=1 and B2=1), then both the p and s-polarizations will pass through P3 and P4 and so the emerging ray from S4 will contain both the p and s-polarizations. Hence the final output from BS2 is 11—which follows the truth table for OR gate. Similarly, it is valid for other input combinations also as per Table 2(a).

4.3 AND gate

Figure 3 is the circuit diagram for the AND Gate. The polarized light beam incident on the first savart plate S1 is splitted into the two orthogonal components with a spatial shift and modulated by the positive SLMs P1 and P2 by means of the input A (combination of A1 and A2) and they reunited again at S2. The emerging ray is then incident on the second building block and modulated again by the positive SLMs P3 and P4 as per the input B (combination of B1 and B2). Depending on A and B the output will occur according to the AND Gate truth table shown in Table 2(b).

Fig. 3
figure 3

AND gate

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4.4 NOT gate

The output obtained from this gate is simply the complement of the input. The circuit diagram is shown in Fig. 4. The savart plate S1 decomposes the incident beam into two orthogonally polarized beams with a spatial shift. The only input A (combination of A1 and A2) is applied through the SLMs P1 and P2 and accordingly the essential components of the polarized beams are present in the light coming out of the savart plate S2. Now it is allowed to pass through the savart plate S3, where, the opto-electrical converters (O/E) C1 and C2 are used in the path of the rays to convert the light signal into electric voltage—which are then feed to the positive SLMs P3 and P4 to control the polarized components of the beam coming out of the savart plate S4. The savart plate S5 is then used to re-unite the final components present and to get the final output, which is simply the complement of the input A. Here, the output follows the truth table of NOT Gate as shown in Table 2(c).

Fig. 4
figure 4

NOT gate

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For example, suppose A=01 i.e., A1=0 and A2=1—hence, no voltage is applied at SLM P1 but a voltage is applied at SLM P2. As a result, no p-polarization is present from the output of P1 but s-polarization is available from the output of P2 and when they recombine at S2, only s-polarization is available at the output of S2. As a result when it is passes through S3 only C2 of the O/E converter will be activated and correspondingly P4 will be energized but P3 will remain at zero voltage. So the ray following the path BS1, M1 and savart plate S4 will be modulated by the negative SLMs P3 and P4 such that only the p-polarization is present at the output coming out of S5, which corresponds to 10. So it is simply the complemented output of the input. For other inputs also it follows the truth table of NOT gate as shown in Table 2(c).

4.5 Exclusive-OR (XOR) gate

The circuit diagram for the exclusive-OR (XOR) gate is shown in Fig. 5. The combination as shown follows the truth table for XOR Gate shown in Table 2(d). The two inputs are respectively A (combination of A1 and A2) and B (combination of B1 and B2).

Fig. 5
figure 5

XOR gate

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4.6 NAND gate

The circuit diagram for the NAND gate is shown in the Fig. 6. The combination as shown follows the truth table for NAND gate given in Table 2(e).

Fig. 6
figure 6

NAND gate

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4.7 NOR gate

The circuit diagram for the NOR gate is shown in the Fig. 7. The combination as shown follows the truth table for NOR gate as per Table 2(f).

Fig. 7
figure 7

NOR gate

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5 Adder circuit

The adders of quadruple valued logics can also be classified into two categories—

  1. (i)

    Half Adder and

  2. (ii)

    Full Adder.

5.1 Quadruple-valued half adder

A half adder has two inputs and two outputs. The outputs are called Sum and Carry(Cout) respectively. The Sum output is the addition of two inputs and Carry is the carry out generated from the addition. The truth table for the half adder is given in the Table 4.

Table 4 Truth table for half adder
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5.1.1 Truth tables of quadruple-valued half adder based on dibit representation

Here we can represent the inputs as well as the outputs in the dibit form. The dibit representations of the two inputs A and B and the outputs S and C are given below:

$$\everymath{\displaystyle} \begin{array}{@{}l@{\quad}l} \mbox{Inputs:} & \mathrm{A} = a_{j}a_{i} \quad \mbox{and} \quad \mathrm{B} = b_{j} b_{i} \\[2mm] \mbox{Output:} & \mathrm{Sum}\ (\mathrm{Sum}) = \mathrm{S} = s_{j} s_{i} \\[2mm] & \mathrm{Carry}\ (\mathrm{Cout}) = \mathrm{C} = c_{j} c_{i} \end{array} $$

The truth tables for the Sum and Carry in the dibit form are given in Table 5.

Table 5 Truth tables for (a) Carry and (b) Sum
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5.1.2 Expressions for Sum and Carry

From the truth Table 5 we can write the expressions for the Sum and Carry as follows:

5.1.3 Block diagram of quadruple-valued half adder

The block diagram of Half-Adder circuit is shown in Fig. 8. A and B are the two inputs and the outputs are Sum and Carry (Cout).

Fig. 8
figure 8

Block diagram of quadruple-valued half adder

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5.2 Quadruple-valued full adder

The truth table for the quadruple-valued full adder is given in the Table 6. It is clear from the truth table that it is accomplished by four half adders and multiplexing their output based on the carry-in. The first half adder is identical to a normal half adder since the carry-in is 0. The second adder with carry-in=1, the third adder with carry-in=2 and the fourth adder with carry-in=3.

Table 6 Truth table for full adder
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5.2.1 Block diagram of quadruple-valued full adder

The block diagram of quadruple valued full-adder circuit is shown in Fig. 9. A and B are the two normal inputs and Cin is the other input and the outputs available from the full-adder circuits are Sum and Carry (Cout). This full adder circuit can be constructed from the half adder circuit and by using the logic gates as discussed earlier in this chapter.

Fig. 9
figure 9

Block diagram of quadruple-valued full adder

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6 Subtractor circuit

The subtractor of quadruple valued logics can also be classified into two categories—

  1. (i)

    Half Subtractor and

  2. (ii)

    Full Subtractor.

6.1 Quadruple-valued half subtractor

A half subtractor has two inputs and two outputs. The outputs are called Difference (D) and Borrow (Bout) respectively. The Difference output is the diffence of two inputs and Borrow is the barrow out generated from the subtraction. The truth table for the half subtractor is given in the Table 7.

Table 7 Truth table for half adder
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6.1.1 Truth tables of quadruple-valued half adder based on dibit representation

Here we can represent the inputs as well as the outputs in the dibit form. The dibit representations of the two inputs A and B and the outputs D and Br are given below:

$$\everymath{\displaystyle} \begin{array}[b]{@{}l@{\quad}l} \mbox{Inputs:} & \mathrm{A} = a_{j}a_{i} \quad \mbox{and} \quad \mathrm{B} = b_{j} b_{i} \\[2mm] \mbox{Output:} & \mathrm{Difference}\ (\mathrm{D}) = \mathrm{D} = d_{j} d_{i} \\[2mm] & \mathrm{Borrow}\ (\mathrm{Bout}) = \mathrm{B}_{r} = b_{rj} b_{ri} \end{array} $$

The truth tables for the Difference and Borrow in the dibit form are given in Table 8.

Table 8 Truth tables for (a) borrow and (b) difference
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6.1.2 Expressions for sum and carry

From the truth Table 5 we can write the expressions for the Difference and Borrow as follows

$$\everymath{\displaystyle} \begin{array}{@{}l} \mbox{B}_{ri} = (\bar{b}_{j}\, \mbox{AND}\ \bar{b}_{i} \, \mbox{AND}\ a_{i}) + \bigl[b_{j} \, \mbox{OR}\ ( \bar{b}_{i}\, \mbox{AND}\ a_{i})\bigr]\, \mbox{AND}\ a_{j} \\[2mm] \mbox{B}_{rj} = 0 \\[2mm] \mbox{D}_{i} = \bar{b}_{i} \ \mbox{XOR}\ a_{i} \\[2mm] \mbox{D} _{j} = b_{i} \ \mbox{AND}\ (b_j \ \mbox{XOR}\ a_j) + (b_j \ \mbox{AND}\ \bar{a}_j \ \mbox{AND}\ \bar{a}_i) \\[2mm] \hphantom{\mbox{D} _{j} =}{}+ \bigl[\bigl(\bar{b}_i \ \mbox{AND}\ (b_j \ \mbox{XNOR}\ a_j) \bigr) \ \mbox{OR}\ (b_j \ \mbox{AND}\ a_j) \bigr]\ \\ [2mm] \hphantom{\mbox{D} _{j} ={}+ \bigl[} \mbox{AND}\ a_i \end{array} $$

6.1.3 Block diagram of quadruple-valued half subtractor

The block diagram of Half-Subtractor circuit is shown in Fig. 10. A and B are the two inputs and the outputs are Difference and Borrow (Bout).

Fig. 10
figure 10

Block diagram of quadruple-valued half subtractor

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6.2 Quadruple-valued full subtractor

The truth table for the quadruple-valued full subtractor is given in the Table 9. It is clear from the truth table that it is accomplished by four half subtractors and multiplexing their output based on the borrow-in.

Table 9 Truth table for full subtractor
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6.2.1 Block diagram of quadruple-valued full subtractor

The block diagram of quadruple valued full-Subtractor circuit is shown in Fig. 11. A and B are the two normal inputs and Bin is the other input and the outputs available from the full-subtractor circuits are Difference and Borrow (Bout).

Fig. 11
figure 11

Block diagram of quadruple-valued full subtractor

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7 Conclusions

In this paper we have discussed the very basic quadruple-valued logic systems and their practical implementations by using the Electro-Optic Technique (EOT) with opto-electronic devices for the fast operation. The dibit representation of this logic helps to implement the system in a simpler manner. In ideal situations the optical devices, mirror, SLM, polarizer etc. in the logic gates have no insertion losses. However, in realistic situations, these losses are important. The polarizer used at the input end absorbs much energy but this polarizer may be avoided if one takes a polarized laser. The main losses are at the switches i.e. at the SLMs, the losses incurred is not much as the SLMs are used in two modes either it allows the beam or not. The losses incurred are very much comparable to switches used in normal binary photonics switches. The devices discussed here are the passive components—so the bandwidth depends on the switching time of the SLMs and now-a-days very fast optical switches are also available. Moreover, the operating wavelength mainly depends on the selection of Savart plates and SLMs, which are available from visible to IR (Infra-Red) region, but the light must be highly monochromatic for proper performance of the optical components.

The purpose of this study is to explore the quadruple logic system with opto-electronic implementation for the very explicit potential areas like, grey image processing, fuzzy logic implementations, fractal formations and any other emerging areas where the fast operations are needed. Though in optoelectronic implementations, the optical parallelism is sacrificed due to the connections amongst cells, however, the advantages of four-state implementation make it possible to handle more information at a time.