1 Introduction

Recently, the researches in the nanostructures and quantum dot fields have gained much attention [1,2,3,4]. Quantum-dot cellular automata (QCA) as a new electronic paradigm is possibly going to be the main hopeful substitute for future high performance integrated circuits [5,6,7,8,9]. Following the apparent reduction of property extent of Very Large Scale Integration (VLSI) systems, Complementary Metal Oxide Semiconductor (CMOS) technology has met many critical challenges and problems [10,11,12,13]. In recent years, research attempts have been concentrated on novel devices to substitute CMOS technology. In this regard, QCA has more attractive due to its ability for performing standard calculations with its vast computation switching velocity, down potency dissipation, and little measures [14,15,16,17,18]. Logic states of QCA are expressed by cells that are constructed from two extra electrons and four quantum dots [19,20,21,22]. Information is transmitted through interactions among QCA cells. Therefore, it only eludes flow discharge in circuits [23,24,25,26,27].

One of the most popular sequential circuits is the shift register, which is broadly used in digital systems. The presentation of many digital flows is measured by utilized shift register efficiency [28]. Shift register flow is produced using a collection of flip flops connected to save the data [29]. It can transfer the input signal from one position to either right or left. Shift registers can contain consecutive and collateral entrances and productions. The essential part of the structure of each shift register is the D-flip flop circuits [30,31,32]. Thus, due to the importance of Parallel-In-Parallel-Out (PIPO) and Serial Input-Serial Output (SISO) among many types of shift registers and their inherent efficient performance, designing new structures with the reduced size is of great importance.

This research proposes an emerging and efficient design for SISO and PIPO shift registers standing on well-optimized dual edge-triggered D-flip flop in QCA technology. Offered 3-bit shift registers are combined of three cascading D-flip flops with the capability to shift data to the right for each clock cycle. Evaluation of suggested structures has been carried out by comparison with some earlier designs in the literature. Proposed power-efficient shift registers have a robust implementation with developments in cell count, area, and latency. The contributions of the current work are:

  • Designing a new shift register of PIPO and SISO based on QCA applying dual edge-triggered D-flip flop;

  • Examining the offered shift registers and comparing them with existing circuits;

  • Verifying the operation and accuracy of suggested plans utilizing QCA designer instrument.

This research is explained in five sections. In the second part, prior similar works of the shift register circuits are reviewed. The new scheme of SISO and PIPO shift register with the utilization of dual edge-triggered D flip flop have been represented in Section 3. QCA layout along simulation outcomes is demonstrated in the fourth part. Besides, the comparison of offered shift registers with other circuits for various parameters is shown in this section. Finally, a conclusion is given in the last section.

2 Related Work

A design of serial shift register using a recent emerging edge-triggered D flip-flop containing readjust susceptibility has been proposed by Zoka and Gholami [33]. Effective execution of D-flip flop flows has utilized a measure for implementing a readjust entrance into D-flip flop. This D-flip flop along a reset entrance is susceptible to a clock edge. Presented D flip flop was applied in a 3-bit sequential shift register for demonstrating the accurate circuit execution. In this shift register, as the readjust entrance is triggered, total outputs become 0. The used cells of current design have been more than equivalent flows, but it is able to work with identical velocity and postponements of shift registers.

A new designed reversible Serial In Parallel Out (SIPO) shift register with the utilization of reversible Dual Edge Triggered (DET) D flip flop is presented by Singh and Pandey [34]. The used DET D flip flop in this shift register has been schemed to employ two pairs of Fredkin and Feynman gates, which constitute two parallel opposite level-sensitive flip-flops, and the last Fredkin gate is employed as a multiplexer. In 4-bit SIPO shift register, input has been utilized by first flip flop and four outputs taken from all the flip flops. The consequences have illustrated the fact that the energy consumed of introduced design is ultra-low.

Also, a new 3-bit SISO QCA-based shift register depending on three new D flip flop circuits has been presented by Divshali et al. [28]. In this work, the first three QCA D-flip flops are provided, and then they are used to design the SISO shift register. This shift register has been executed in 5 categories that D flip flops have been applied in groups 1, 3, and 5. The second and fourth categories have been executed to transfer information. 5-layer 3-bit QCA-based SISO shift register flow provides better performance of the region.

In the end, Das and De [35] have suggested an optimum SISO shift register structure with the utilization of a novel QCA D flip-flop layout. Level sensitive construction D flip-flop has been obtained utilizing a bound node 3-bit SISO shift register, which is produced of three connected D flip flops. The presented shift register has been obtained in one category and has a lower cell amount with more system aggregate in compared to others. Energy utilization examinations have demonstrated that the suggested scheme includes down power utilization. Table 1 compares the significant benefits and defects of reviewed QCA-based shift register schemes.

Table 1 Summary of prior explained QCA shift registers
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3 Proposed Design

D-type flip flops are primary blocks in many digital circuits such as shift registers and as an essential storage element that can maintain a binary state [36]. Therefore, many researchers try to complete the efficiency of D flip flop circuits. This section introduces a Dual Edge Triggered QCA-based D-flip flop extracted from a suggested design by Roshan and Gholami [37]. Then, an impressive and novel scheme has been proposed for PIPO and SISO shift registers standing on QCA-based D-flop flop circuit. In the current structure, D latch has been planned using a multiplexer through response by production toward first input along with proper postponement with feedback route. A level-to-edge triggered converter has been utilized for transforming latch to flip flop. In this converter, a 2 to 1 multiplexer is utilized, where a clock signal applied to select input and created a postponement cycle in clock conversion route to two D0 and D1 inputs of multiplexer. Therefore, standing on this method, the clock ongoing amount with the previous state of it can be produced. Thus, eq. 1 can be considered for the converter of dual-edge. Figure 1 depicts the Dual Edge Triggered D flip flop structure.

Fig. 1
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Schematic of dual edge-triggered D flip flop

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$$ {CLK}_{new}=\overline{CLK_t}.{CLK}_{t-1}+{CLK}_t.{\overline{CLK}}_{t-1} $$
(1)

Table 2 summarizes the falling edge-triggered D Flip-Flop truth table. As can be seen, if CLKt and CLKt-1 are 0, the output on the base flip flop prior amount (D0) is determinant and indicating that there is no edge. When CLKt is 1 and CLKt-1is 0, the production has been the same with the amount in D1 that illustrates the accurate recognition of emerging edge. When CLKt is 0 and CLKt-1is 1, the output is the same with the amount on D1, which reflects the accurate falling edge recognition. Eventually, if CLKt and CLKt-1 are equal to 1, the output is the same with the amount of D0 and maintains the prior flip flop amount.

Table 2 The dual edge-triggered D flip flop truth table
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Shift register as a type of sequential circuits is composed of a flip-flops chain linked to each other in a way that its content is able to modify one location to right or left. An n bit shift register includes n D flip flop. Those flip flops have been managed by an ordinary clock. SISO and PIPO shift registers are the most comfortable shift registers that contain only flip flops. The single flip flop production is inputted to the subsequent flip flop following the clock in SISO shift register. In suggested QCA SISO shift register, serial input has been utilized for the leftmost dual edge-triggered QCA D flip flop, and sequential production has been obtained from the rightmost dual edge. The 3-bit SISO shift register schematic structure that, with each clock, pulse changes the input register data one bit to the right, has been indicated in Fig. 2. In QCA PIPO shift register, the entrances have been filled in parallel in dual edge-triggered QCA flip flops concurrently. Besides, they are accessible in collateral by flip flops’ different stages in the chain. Figure 3 shows a 3-bit PIPO shift register block diagram with 3 separate inputs.

Fig. 2
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Schematic 3-bit SISO shift register diagram

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Fig. 3
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Schematic 3-bit PIPO shift register diagram

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4 Simulation Results

In this part, first, a glance at the used tool to simulation is provided, and then the suggested shift registers’ QCA-based plan, their output waveforms, and analogy with modern plans have been considered.

4.1 Simulation Tool

QCA designer has been considered as an accurate simulator that mimics the QCA parts and finds the condition of the entrance to production signs as the outcomes. This tool is developed for functionality checking of QCA circuits and allows the designer to abruptly layout [38]. QCA designer version 2.0.3 has been applied to detect functional correctness of suggested structures. Simulation parameters, which mentioned in Fig. 4, have been in predetermined values, and a bistable approximation processing engine is employed for testing various settings.

Fig. 4
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QCADesigner parameters for bistable approximation engine

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4.2 The Layout of Suggested Designs

QCA dual edge-triggered D flip flop execution architecture has been indicated in Fig. 5. As can be seen, in this architecture, the whole of the outputs and inputs have been accessible for utilizing in huger circuits, and only one layer is needed. This D flip flop is composed of 49 QCA cells with an occupation space of 0.04 μm2, and the input signal is delivered to the output after 2 clock flow delay. Cells containing diverse colors express four signals of the clock that are employed for contemporizing and manage one another cycle pieces by rights.

Fig. 5
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The dual edge-triggered D flip flop scheme in QCA

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The 3-bit SISO shift register QCA layout standing on dual edge-triggered D-flip flop has been indicated in Fig. 6. The proposed single layer shift register is constructed of three D-flip flops and includes one clock entrance, single information entrance, and one production from last flip flop. As can be seen in this SISO shift register, 167 QCA cells have been used, and the space occupied is 0.22 μm2. Serial data are shifted to the right and appear on output after 6 cycles of clock postponement. Moreover, presented 3-bit PIPO shift register QCA plan has been indicated in Fig. 7. The offered flow has been executed in one layer and produced of three dual edges triggered D-flip flops. This type of shift register has three data inputs, three outputs, and one common clock input. The cells’ item of this execution has been considered about 177, and the region reports 0.16 μm2. 3-bit information has been produced by D1, D2, D3 in collateral, and after 2 clock cycle postponement, information obtained is gathered as production based on their ranking from Q1, Q2, Q3.

Fig. 6
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Suggested 3-bit SISO shift register design in QCA

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Fig. 7
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Suggested 3-bit PIPO shift register design in QCA

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4.3 Validity Analysis

Figure 8 depicts the valid performance of dual edge-triggered D flip flop. Different dual amounts have been utilized at D entrance. The D input amounts are moved to the output in falling and rising clock edges. D has been 0 in clock’s first collapsing edge. So, the efficiency will be 0. The output does not experience any alternation until the subsequent ascending clock edge. Now, the insert of D is equal to 1, so the output is changed to 1. This design spans 2 clock cycle delay from input to output.

Fig. 8
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Simulation waveforms for QCA dual edge-triggered D flip flop

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Implementation outcomes of suggested 3-bit QCA SISO shift register have been indicated in Fig. 9. In the earliest falling of the clock edge, the D input values are 0, which is entered to QA while QB and QC are still empty. In the next ascending clock edge, the input of D has been 1, which is entered to QA, and prior D amount input is shifted to the right at located QB while QC still remains empty. In the third clock edge, the input of D entered to QA with the amount of 0, value of insert of D from the second stage is shifted to B while the value of D input in QB previously is now shifted to QC and so on. Afterwards, the earliest significant QC efficiency will be obtained after 6 clock flow postponement. Moreover, Fig. 10 depicts the execution outcomes of suggested 3-bit QCA PIPO shift register. Collateral data have been filled in register altogether and shifted to their relevant productions via the same clock edge. Consequences show accurate production after 2 clock flow.

Fig. 9
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Simulation waveforms for 3-bit QCA SISO shift register

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Fig. 10
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Simulation waveforms for 3-bit QCA PIPO shift register

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4.4 Comparisons

Suggested PIPO and SISO shift registers are compared in Table 3 with previous designs. Based on implementation results, it can be proven that the proposed 3-bit shift registers are superior compared to other related works concerning the occupied area requirement and the number of cells. The 3-bit shift registers are based on edge-triggered D flip flop while PIPO shift register in [39] is based on Level Triggered D flip flop. The indicated designs can be easily extended to n-bit since all inputs are available. Also, the results can be found that although proposed shift registers operate with a higher latency than similar circuits, but provide better performance.

Table 3 The presented 3-bit QCA shift registers’ comparative table with other related works
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5 Conclusion and Future Works

Efficient and robust 3-bit PIPO and SISO shift register designs based on an optimal dual edge-triggered D flip flop model in QCA technology have been introduced in this article. Suggested 3-bit QCA shift register circuits are executed in one layer that supplies the circulations’ easiness. Simulations are performed using the bistable approximation engine and a collection of vector table simulation outcomes of QCA designer tool. Also, these two circuits’ structural attributes are discussed in effective regions, difficulty, and delay that indicate a significant preference of suggested layouts due to the area occupation and cell count. These structures may be impressive for the design of high-performance digital systems and circuits in the future. Moreover, the proposed QCA-based shift registers are able to be developed to the great layout of instruction. They might be utilized as the main instruction block of common target nano-computers. Risk and reliability assessment [40,41,42] of suggested design is another absorbing script for further investigations. Finally, the delay and speed optimization from sequential circuit modules could be considered for future studies.