1 Introduction

Today’s PPS are important elements in phase array radars, antenna switch and positioning systems. The phase shifters have two kinds of structures, passive and active. The PPS is a bilateral network, but the active-type is an unilateral network. The advantage of PPS is that it can be used to both transmit and receive path at the same time. The structure of PPS is a combination of low/high pass filters. For radio frequency (RF)/microwave switch design, PIN diode [1], Micro Electro Mechanical System (MEMS) [2], Low Temperature Co-fire Ceramic (LTCC) [3] and Field Effect Transistor (FET) (in both GaAs and CMOS processes) are the four commonly used technologies. However, considering the cost, integration, switching speed, power consumption, and linearity, FET switches based on III–V compounds (e.g., GaAs), especially pHEMTs, are the most attractive choice on the wireless communication market [4].

Many different passive and active MMICs PS have been reported in literature [5–7]. A switched high-pass/low-pass phase shifter for the X band with 6-bit resolution has been reported in [6]. The technology can be implemented in MMICs. So, the designer can be able to use lumped elements such as inductors, capacitors, resistors and transistors together. Here the dimension of the chip is much smaller than other methods [8]. All connections between elements (microstrip lines) are simulated using advanced design system (ADS) Momentum for planar electromagnetic simulations to take into account the coupling between adjacent microstrip lines.

In Sect. 2, the optimization of switch will explain how to use phase shifter designing. In Sect. 3, the configuration of SPDT is introduced and in the last Sect. 4, the structure of 90° phase shifter block indicated optimized switch and SPDT are presented.

2 Optimized switch

In this section, an original method is used to describe the investigation on the improvement of the insertion loss and isolation of the pHEMT switch. Fundamentally, the role of the switch is very important in PPS designing. In PPSs, some undesired effects occur due to parasitic elements of transistors. These affects are found in the phase and insertion loss variation of the PPS. The Fig. 1 illustrates GaAs pHEMT switch in standard and proposed form. In this method, the undesired effects of transistors are reduced.

Fig. 1
figure 1

Simulated insertion loss and isolation for the switch in standard and proposed form

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As shown in Fig. 1, a diode is added on a gate of transistor. Usually, a diode is modeled by a dynamic resistor (R d ) and a capacitor (C d ). The C d is the junction capacitor between the anode and cathode of diode in the depletion region. The C d and gate capacitor (C g ) are series together as shown in Fig. 2. Also, the C d is significantly less than C g .

$$\frac{{C_{g \times } C_{d} }}{{C_{g} + C_{d} }} \cong C_{d} \quad if \quad C_{g} \gg C_{d}$$
(1)
Fig. 2
figure 2

Equivalent circuit of the proposed switch

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The Eq. (1) shows that C g of the proposed switch is smaller than the standard form. The Fig. 2 shows the equivalent circuit of the proposed switch. The parameters of the proposed switch in Fig. 1 can be modeled with parasitic elements like as a C d , C gs , C ds , C gd , g ds and g m .v gs as shown in Fig. 2. The next equation is extracted from the solving of polynomial function for the Z-parameters matrix where the Z in is the input impedance of the proposed switch.

The input impedance of the proposed switch is given by:

$$\begin{aligned} Z_{in} = & \\ & \frac{{\left[ {g_{ds} .R_{L} .C_{d} + C_{d} + g_{ds} .R_{L} .C_{gd} + g_{m} .R_{L} .C_{gd} + C_{gd} + g_{ds} .R_{L} .C_{gs} + C_{gs} } \right] + [C_{ds} .C_{d} .R_{L} + C_{gd} .C_{d} .R_{L} + C_{gd} .C_{ds} .R_{L} + C_{gs} .C_{gd} .R_{L} ]s}}{{C_{d} .\left[ {g_{ds} .R_{L} .C_{gd} + g_{m} .R_{L} .C_{gd} + C_{gd} + g_{ds} .R_{L} .C_{gs} + C_{gs} } \right]s + C_{d} .\left[ {C_{ds} .C_{d} .R_{L} + C_{gd} .C_{d} .R_{L} + C_{gd} .C_{ds} .R_{L} + C_{gs} .C_{gd} .R_{L} } \right]s^{2} }} \\ \end{aligned}$$
(2)

If we assume that the transistor is unilateral, then C gd is omitted.

$$Z_{in} = \frac{{\left[ {g_{ds} .R_{L} .C_{d} + C_{d} + G_{ds} .R_{L} .C_{gs} + C_{gs} } \right] + \left[ {C_{d} .C_{ds} .R_{L} } \right]s}}{{\left[ {g_{ds} .C_{gs} .C_{d} .R_{L} + C_{gs} .C_{d} } \right]s + \left[ {C_{gs} .C_{ds} .C_{d} .R_{L} } \right]s^{2} }} = \frac{{(C_{d} + C_{gs} )}}{{s(C_{gs} .C_{d} )}}$$
(3)

The behaviors of the switches are illustrated in Fig. 3 [4]. Figure 3 shows the study of the characteristics of the standard and proposed switches. The Fig. 3(a) shows that the gate capacitor (C g ) of the transistor changes significantly in 20 GHz bandwidth. If the input power increases, the non-linear effect of the transistor will be found through the large signal phenomenon of pHEMT transistor. But in Fig. 3(b), the C g of the proposed switch is decreased, hence, the large signal and nonlinear effects of the new method are declined. Table 1 shows the value of C g as a function of frequency from Fig. 3.

Fig. 3
figure 3

The smith chart of (a) Standard switch structure. (b) Proposed method structure

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Table 1 The C g values in standard and the proposed method
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As it is evident in the Fig. 4 and Table 1, the proposed switch is suitable for the phase shifter designing. Because in PPS application, the behavioral switch have an undesirable effect in PPS specification, so, it has been tried to design a good switch with minimum undesirable effect. The Fig. 4 shows that the phase variation is decreased in proposed switch, whereas in standard switch the phase variation is too much in on–off mode. In standard switch, the phase variation is more than 15 degrees, but in the proposed, phase variation is maximum 2 degrees in on–off mode@ 10 GHz. Some parameters such as phase uniformity, the best insertion loss and maximum input power handling are very important in PPSs [9].

Fig. 4
figure 4

The phase shift of standard and proposed switch

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3 SPDT structure

In this section, we describe how by using the proposed method, the performance of the GaAs switch can be improved. The schematic circuit diagram of the implemented SPDT switching circuit is shown in Fig. 5. The size of the transistors has been selected for high power handling. Since the breakdown voltage in a GaAs HEMT is larger than the pinch off voltage, power handling of the switch is set by the open channel current limit of a transistor. Therefore, in order to have a design with acceptable power handling, total gate width of the series pHEMTs has to be selected in a fitting manner [10].

Fig. 5
figure 5

Schematic of SPDT

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In Fig. 5, the series transistors M1 and M2 perform the main switching functions, and the shunt transistor M3 and M4 increase the isolation of the switch. Under these conditions, one of the RF inputs (P2 or P3) is connected to the common port (P1) through a low value of the complementary HEMT’s on—resistance, while another one is isolated from the common port by the large value of the drain—source resistance in the “off” mode. The D1 and D2 are increased the power handling of SPDT switches. The Fig. 6 shows the simulation results of the proposed SPDT switch. As shown in Fig. 6(a), the insertion loss is 0.7 dB with variation of ±0.1 dB and its isolation is better than 28 dB. Also, Fig. 6(b) shows that the P1dB of the circuit is 28 dBm [10].

Fig. 6
figure 6

(a) Simulation result of Insertion loss and Isolation (b) Simulation result of 1 dB compression point and pout versus pin

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4 90o phase shifter Block structure

The Fig. 7 illustrates the proposed 90o block structure. This configuration has two SPDT switches in input and output of block. The proposed block includes a high pass and a band pass filter.

Fig. 7
figure 7

Proposed 90o block

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The Fig. 8(a) shows the structure of high pass filter through which the SPDT switch leads signal to high pass section of the proposed block. Then, the signal finds a path to the ground via L 1 and C 1 .

Fig. 8
figure 8

(a) High pass filter (b) Band pass filter

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The Fig. 8(b) illustrates the band pass filter at the second state. The signal finds the ground via L 2 , C 2 to 50 Ω impedance matching.

The Eqs. (4) and (5) are the transfer function of high pass and band pass filter respectively.

$$H_{H.P} \left( s \right) = \frac{{\left( {C_{1}^{2} L_{1} Z_{0} } \right)s^{3} }}{{1 + \left( {C_{1} Z_{0} } \right)s + \left( {2 C_{1} L_{1} } \right)s^{2} + \left( {C_{1}^{2} L_{1} Z_{0} } \right)s^{3} }}$$
(4)
$$H_{B.P} \left( s \right) = \frac{{\left( {C_{2}^{2} Z_{0} } \right)s^{2} }}{{\left( {2C_{2} } \right)s + \left( {C_{2}^{2} Z_{0} } \right)s^{2} + \left( {C_{2}^{2} L_{2} } \right)s^{3} }}$$
(5)

The S-parameters of the high pass filter are given by:

$$S_{H.P 11} = \frac{{j(2C_{1} \omega - C_{1}^{2} L_{1} \omega^{3} - Z_{0}^{2} L_{1} \omega )}}{{2Z_{0} - 2Z_{0} L_{1} C_{1} \omega^{2} + j\left( {Z_{0}^{2} L_{1} \omega + 2C_{1} \omega - C_{1}^{2} L_{1} \omega^{3} } \right)}}$$
(6)
$$S_{H.P 12} = \frac{{2Z_{0} }}{{2Z_{0} - 2Z_{0} L_{1} C_{1} \omega^{2} + j\left( {Z_{0}^{2} L_{1} \omega + 2C_{1} \omega - C_{1}^{2} L_{1} \omega^{3} } \right)}}$$
(7)

By using the above equations, the best values of L 1 and C 1 are calculated. To achieve the best impedance matching in input and output circuit of central angular frequency (ω0), S 11  = 0 should be considered, so the relationships between L 1 and C 1 are:

$$L_{1} = \frac{{2C_{1} \omega_{0} }}{{C_{1}^{2} \omega_{0} + Z_{0}^{2} \omega_{0} }}$$
(8)

From S 21 , the values of phase shift, L 1 and C 1 in central angular frequency (ω0) are obtained as follows:

$$\Delta \varphi = - \tan^{ - 1} \left( {\frac{{Z_{0}^{2} L_{1} \omega_{0} + 2C_{1} \omega_{0} - C_{1}^{2} L_{1} \omega_{0}^{3} }}{{2Z_{0} - 2Z_{0} L_{1} C_{1} \omega_{0}^{2} }}} \right)$$
(9)
$$C_{1} = \frac{{Z_{0} \tan \left( {{\raise0.7ex\hbox{${\Delta \varphi }$} \!\mathord{\left/ {\vphantom {{\Delta \varphi } 2}}\right.\kern-0pt} \!\lower0.7ex\hbox{$2$}}} \right)}}{{\omega_{0} }} ;L_{1} = \frac{\sin (\Delta \varphi )}{{Z_{0} \omega_{0} }}$$
(10)

Also,the S-parameters of the band pass filter are given by:

$$S_{B.P 11} = \frac{{j(C_{2} L_{2} \omega^{2} - 2)}}{{2Z_{0} C_{2} \omega + j(C_{2} L_{2} \omega^{2} - 2)}}$$
(11)
$$S_{B.P 12} = \frac{{2Z_{0} C_{2} \omega }}{{2Z_{0} C_{2} \omega + j(C_{2} L_{2} \omega^{2} - 2)}}$$
(12)

By using above equations, the best value of L 2 and C 2 are calculated. To give the best impedance matching of circuit in ω0, S 11 should be equal to zero. So L 2 and C 2 are:

$$\left. {\frac{d}{d\omega }\left( { - \tan^{ - 1} \left( {\frac{{L_{2} C_{2} \omega^{2} - 2}}{{2Z_{0} C_{2} \omega }}} \right)} \right)} \right|_{{\omega = \omega_{0} }} = \frac{ - 1}{{Z_{0} C_{2} \omega_{0}^{2} }}$$
(13)

By evaluating Eqs. (9) and (13), the best value of C 2 and L 2 are achieved.

$$L_{2} = \frac{{2Z_{0} \tan (\Delta \varphi /2)}}{{\omega_{0} }} ; C_{2} = \frac{1}{{2Z_{0} \omega_{0} \tan (\Delta \varphi /2)}}$$
(14)

The values of C 1 , C 2 , L 1 and L 2 are shown in Table 2.

Table 2 Components values
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The Fig. 9 shows the photograph of 90o block in pHEMT GaAs technology.

Fig. 9
figure 9

Photograph of 90o block

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The Fig. 10 shows the simulation and the measurement results of 90o phase shifter block. The measured phase shift is 87o ± 3.5o over 8–12 GHz.

Fig. 10
figure 10

The measurement and the simulation results of 90o phase shifter

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The Fig. 11 shows the simulation and the measurement of the insertion loss of the proposed block. The measured insertion loss is −1.6 ± 0.1 dB over 8–12 GHz.

Fig. 11
figure 11

The measurement and the simulation results of insertion loss

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The Fig. 12 shows the simulation and the measurement of the S 11 of 90o block in “ON” and “OFF” state.

Fig. 12
figure 12

The measurement and the simulation results of S11

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The Fig. 13 illustrates phase shift of the block versus input power. This diagram shows that the output phase shift has less phase variation in 25 dBm input power.

Fig. 13
figure 13

The measurement and the simulation results of phase variation versus input power

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In the Fig. 14, 1 dB compression point of the proposed block is determined. The result shows that P1dB is 25 dBm.

Fig. 14
figure 14

The measurement and the simulation results of 1 dB compression point and output power versus input power

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The Table 3 presents a detailed comparison between some of the same studies.

Table 3 Comparison of 90o phase shifter blocks
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5 Conclusions

In this study, by using 0.15 µm pHEMT technology, a MMIC 90o block is fabricated and measured in X-band. In this work, a transistor switch is optimized by using the proposed method, and then utilized in the SPDT switch. The SPDT switch is used in the proposed block. The measurement results of the proposed block show that the insertion loss is −1.6 dB, the phase shift is 87o ± 3.5o over 8–12 GHz. The phase linearity and P1dB are more than 25 dBm. The die size is 1 mm2. The measurements hence show a good correlation between simulation and the measurement results. So, the results demonstrate the great potential of the proposed block for high performance phased array radar systems.