Novel input stages for current feedback operational amplifiers

Abstract

This paper considers the trade-offs involved in the design of six new input stages intended to improve the performance of a current feedback operational amplifier (CFOA), over that possible using an established input circuit configuration, with respect to three major characteristics, viz, common mode rejection ratio (CMRR), offset voltage and slew-rate.

1 Introduction

The op-amp has evolved steadily over the years with improved designs from a number of the specialist manufacturers. The conventional op-amp is actually a voltage op-amp (VOA), so named because it has the distinctive characteristic of a high input impedance at both the inverting and non-inverting input terminals, and makes use of voltage feedback when used for linear signal processing applications.

Although attempts have been made to improve the performance of the basic VOA structure, the architecture of the VOA unfortunately has inherent limitations in respect of both the gain-bandwidth trade-off and slew-rate. Typically, the gain-bandwidth product is a constant and the slew-rate is limited to a maximum value determined by the input stage bias current. The slew-rate limitations of the VOA are overcome in a newer architecture op-amp, referred to as the current-feedback op-amp (CFOA) [1, 2], so-called because the feedback signal fed into the low input impedance inverting input terminal is current rather than voltage. Typically, slew-rate values for the CFOA range from 500 V/μs to 2,500 V/μs [3–5], whereas the slew-rates of VOAs are much lower, in the region of 1 V/μs to 500 V/μs. This is a direct result of the use of current as the feedback error signal. An advantage, related to the high slew-rate achieved in the CFOA, is that the bandwidth is almost independent of the closed-loop gain, unlike the VOA where the gain-bandwidth product is constant [5]. This gives the CFOA particular advantages in applications requiring variable closed-loop gains with constant bandwidth, such as in automatic gain control (AGC) systems [5, 6].

Although the idea of the CFOA existed some thirty years ago, it was market demand for video signal processing that stimulated interest in the development of a monolithic CFOA in 1987 by Elantec [7, 8]. A factor that held back the arrival of the CFOA was the lack of an advanced complementary bipolar technology, with PNP transistors providing electrical performances comparable with those of NPN types. The semiconductor technique that now enables this is dielectric isolation, which means that both PNP and NPN devices can be fabricated as vertical transistors, and hence offer similar performance characteristics [3, 7].

Unfortunately, the CFOA exhibits relatively poor DC precision, compared with that of the VOA. However, the nature of many high frequency applications is such that this precision may not be a problem with the result that the very high inherent slew-rate puts the CFOA in the spotlight [3].

The CFOA can offer considerable performance advantages when used to realise IF and RF applications [9]. Moreover, the CFOA is absolutely necessary to digital engineers who are involved in the design of high-speed analog-to-digital conversion systems, since these depend heavily on a sampling process in order not to obscure information [10, 11]. The CFOA delivers a high slew-rate and, as such, is the most suitable op-amp for this operation.

Fig. 1

Schematic of an established CFOA architecture

For video-systems engineers there are two important specifications to be considered, namely, (i) the differential gain (DG), and (ii), the differential phase (DP) [5]. DG and DP are two figures-of-merit of an op-amp that relate to the incremental change in closed-loop gain and phase resulting from a change in input and output, referenced to zero volts for a specific frequency. The DG and DP of most VOAs are not constant when varying DC offsets are added to a constant-frequency AC input signal [5]. This can cause problems when processing composite video signals, with picture distortion occurring if the DG and DP are too high. Thanks mainly to circuit topology, the typical CFOA exhibits a much better DG and DP performance than the typical VOA, thus making the CFOA an excellent amplifier for dealing with composite video signals [12, 13]. The other significant application areas for the CFOA are in high speed active-filter design, and line drivers [14].

Despite the many advantages of the CFOA over the VOAs, there exist certain limitations, one of which is the common-mode rejection ratio. The CMRR of CFOAs is generally quite poor, mainly because of the asymmetrical nature of the complementary-pair input stage, and the fact that input bias currents are unequal and uncorrelated. This paper is primarily concerned with circuit techniques for improving the CMRR [12, 14].

Fig. 2

Representation of section A, for common mode signal v _cm

Fig. 3

Representation of section A, for differential-mode signal v _dm

2 An established input architecture

For comparison purposes, the schematic circuit of an established CFOA architecture is shown in Fig. 1 [15].

For simplicity in a first-order analysis, the NPN and PNP transistors are assumed to have identical characteristics. Within the contour A, Q ₁ together with its emitter load (bias current source I _Q with output resistance r _s ) and Q ₃ comprise an input ‘half-circuit’ and it is the half-circuit concept that is explored further in this paper. The other half-circuit, comprising Q ₂ and its emitter load and Q ₃, behaves in an identical, complementary, manner. Consider, first, the CMRR, ρ.

Figure 2, in which diode D ₁ represents the base-emitter junction of Q ₁, shows an equivalent circuit for A when a common-mode input signal, v _cm, is applied. As far as the change, i, in the collector current of Q ₃ is concerned, the circuit behaves like a 1:1 current mirror in which the effective rail supply is decreased in amount by v _cm, so, i comprises two components, viz, −(v _cm/r _s ) due to the current change in D ₁ and −(v _cm/r _o due to the change in collector emitter voltage across the common-emitter collector output resistance, r _o , of Q ₃. Thus:

$$ i = - v_{cm} \left( {\frac{1}{{r_s }} + \frac{1}{{r_o }}} \right) $$

(1)

This neglects the current change in the collector-base resistance, r _μ, of Q ₃ but since $r_\mu \gg r_o$ [16], that is negligible. The common-mode current, i _cm, flowing in load impedance Z, in Fig. 1, after being transmitted via the 1:1 current mirrors CM1, CM2 is double that given in Eq. (1), because of the complementary action of Q ₂, Q ₄ Hence,

$$ g_{Tc} = \left| {\frac{{i_{cm} }}{{v_{cm} }}} \right| = 2\left( {\frac{1}{{r_s }} + \frac{1}{{r_o }}} \right) $$

(2)

Figure 3 shows the equivalent circuit for A when a differential-mode signal, v _dm, is applied. Again, i has two major components, one due to change in base-emitter voltage (≅v _dm), the other due to change in collector-emitter voltage of Q ₃

$$ i \cong v_{dm} \left( {g_m + \frac{1}{{r_{\rm o} }}} \right) $$

(3)

In this equation g _m (the transconductance of Q ₃) = I _Q/V _T , V _T (=KT/q) being the ‘thermal voltage’ (≈25 mV at room temperature). As with i _cm, i _dm is double that given by Eq. (3)

$$ g_{Td} = \left| {\frac{{i_{dm} }}{{v_{dm} }}} \right| \approx 2\left( {g_m + \frac{1}{{r_o }}} \right) \approx 2g_m $$

(4)

The approximation is valid as $g_m \gg 1/r_{o}$ where, $r_{o} = V_{A} /I_{Q} ,{\rm }V_{A}$ ($\gg V_T$) being the Early voltage. From Eqs. (2) and (4);

$$ \rho = \frac{{g_{Td} }}{{g_{Tc} }} \approx \frac{{g_m }}{{\left( {\frac{1}{{r_s }} + \frac{1}{{r_o }}} \right)}} $$

(5)

For the special case r _s = r _o ,

$$ \rho \approx \frac{{V_{\rm A} }}{{2V_{\rm T} }} $$

(6)

This equation is applicable when I _Q is the output of a simple current mirror, as is meant to be the case for Fig. 1. Simulation tests show that doubling V _A doubles ρ [17].

Fig. 4

Half-circuit B

Consider, next, the offset voltage, V _os. This is the voltage at the emitter of Q ₃ when Fig. 1 is connected as a unity-gain follower (V _o connected to the inverting input) and V _I is set to zero. Ideally V _os = 0, but in reality V _os is finite (a few mV) because of mismatch in the V _BEs of Q ₁, Q ₃.

Finally, consider the slew-rate, SR. This, like V _os, is measured in the unity-gain configuration with a resistance (typically between 750 Ω and 2 kΩ for 15 V rail supplies) [18] connected between V _o and the inverting input, when a positive-going voltage step is applied at the non-inverting input. Transistors Q ₁ and Q ₄ in Fig. 1 tend to switch off and the SR is limited by the current, I _Q, available at the base of Q ₃.

3 Improved half-circuits

In the replacement for A (of Fig. 1) in the circuits that follow, r _s is maximised by having I _Q supplied by a cascode source referenced to the rail supplies, and r _o , is made to appear larger by employing a bootstrapped cascode transistor Q ₅.

The bootstrapping technique typifies the configuration. Type 1 circuits are exemplified in Figs. 4–6. In these the base of Q ₅ is bootstrapped to the inverting input, which follows the non-inverting input in normal CFOA operation: a suggested name for this is ‘reverse bootstrapping’. The output resistance at the collector of Q ₅ is approximately equal to βV _A /I _Q (β being the common emitter current gain of Q ₅). This replaces r _o , in Eq. (5); consequently ρ increases by a factor β. The V _os, however, is poor in half-circuit B because of practical mismatch in the V _BE of Q ₁ and Q ₃. This is remedied in half-circuit C, in which Q ₁ is now an NPN transistor, diode-strapped. In half-circuit D, the diode-strapped transistor of Fig. 5 functions as a normal transistor and the emitter-follower Q ₈ increases the SR by making more current available at the base of Q ₃.

Fig. 5

Half-circuit C

Fig. 6

Half-circuit D

Fig. 7

Half-circuit E

Fig. 8

Half-circuit F

Fig. 9

Half-circuit G

Type 2 circuits are-exemplified in Figs. 7–9, in which the base of Q ₅ is driven from the non-inverting input (‘forward-bootstrapping’) Figs. 8, 9, like Fig. 7, employ emitter-followers to drive the base of Q ₃ for increased SR. In Fig. 9, Q ₁ and Q ₃ both operate at the same V _CB (≈0), as well as the same collector current, to ensure a very low V _os. Note that, for a given I _Q , half-circuit A requires the minimum input d.c. bias current. In all the half-circuits, except A, the vertical stacking of transistors necessary to improve the performance parameters detracts from the dynamic output voltage swing of the CFOA because of V _BE summation.

Fig. 10

A CFOA using half-circuit B

Fig. 11

CMRR ∼ Frequency

Fig. 12

AC gain accuracy ∼ Frequency

Fig. 13

Frequency responses for unity closed-loop gain

Fig. 14

Transient response

Fig. 15

Input impedance∼frequency for the CFOAs, each configured as a non-inverting unity gain amplifier

We now consider the design of CFOAs that incorporate these six new input circuits. The performance of each new CFOA is compared with that of the basic one shown in Fig. 1. OrCAD PSpice was used to verify the operation and performance of the circuits. The technology used in the simulation was the complementary bipolar XFCB process of Analog Devices, Santa Clara, California.

In all the new designs, unless otherwise indicated, the main current biasing circuitry is the same as that used in Fig. 10. Furthermore, all simulation measurements refer to I _Q = 0.2 mA, V _CC = ±5 V, at room temperature (27°C).

Table 1 Characteristics of the conventional and the improved CFOA using half-circuit B

Fig. 16

Input impedances (inverting)∼Frequency

Fig. 17

A CFOA using half-circuit C

4 Reverse bootstrapping

4.1 Performance with half-circuit B

In Fig. 10, the buffered current mirrors, (Q ₇+Q ₈+Q ₉+ Q ₁₇+Q ₂₁) and (Q ₅+Q ₆+Q ₁₀+Q ₁₈+Q ₂₆) are supplied with a common input current, I _Q , via the resistor R _Q . Since the operation of the two buffered-mirrors is the same, only one is considered here, (Q ₇+Q ₈+Q ₅+Q ₁₇+Q ₂₁). The output from Q ₇ supplies the cascode transistor Q ₁₁ with the emitter current for Q ₁. The base bias voltage for Q ₁₁ is provided by the voltage drop across the series connected and diode-strapped transistors Q ₁₅, Q ₁₃ the biasing current for which is supplied by an output of Q ₁₈ in the other buffered current- mirror. The cascoding of Q ₇ ensures greater constancy in the emitter current of Q ₁ as the input voltage changes: it results in a better CMRR and less variation of incremental input resistance over the input voltage range. The output from Q ₁₇ supplies current for the bias circuitry of cascode transistor Q ₁₂ and the output from Q ₂₁ supplies biasing current for Q ₂₂, Q ₂₃ connected to the base of cascode transistor Q ₁₉ in the reverse-bootstrapping scheme [19].

Fig. 18

CMRR ∼ Frequency

Fig. 19

AC gain accuracy ∼ Frequency

Fig. 20

Frequency responses for unity closed-loop gain

Fig. 21

Transient response

Fig. 22

Input impedance ∼ frequency for the CFOAs, each configured as a non-inverting unity gain amplifier

Fig. 23

Input impedance (inverting) ∼ Frequency

4.2 Performance with half-circuit C

The circuit diagram of a CFOA using half-circuit C is shown in Fig. 17, and should be compared with that using the half-circuit B, shown in Fig. 10. A significant difference between the two input circuits of the CFOAs is the use of NPN transistors for both Q ₁ and Q ₃, and the application of the input signal to the emitter of Q ₁ rather than its base. Similarly, Q ₂, Q ₄ are both PNP transistors and the input applied to the emitter of Q ₂ rather than its base. Furthermore, Q ₁, Q ₂ are now strapped to operate as diodes. From Fig. 17, it follows that the DC voltage difference from the (+) to (−) is first increased (decreased) by V _BEQ1 (V _BEQ2), and then decreased (increased) by V _BEQ3 (V _BEQ4) [20], thus,

$$ V_{\rm os} = |V_{{\rm BEQ_1} } - V_{{\rm BEQ3} } | = |V_{{\rm EBQ2} } - V_{{\rm EBQ4} } | $$

(7)

Because the matching between the same-type transistors (NPN or PNP) is good, a better V _OS can be achieved.

Table 2 Characteristics of the conventional and the improved CFOA using half-circuit C

Fig. 24

A CFOA using half-circuit D

Fig. 25

CMRR ∼ Frequency

Fig. 26

AC gain accuracy ∼ Frequency

Fig. 27

Frequency responses for unity closed-loop gain

Fig. 28

Transient response

4.3 Performance with half-circuit D

See Table 3.

5 Forward bootstrapping

5.1 Performance with half-circuit E

The biasing scheme is that used in previous designs, but the cascode transistors for Q ₃, Q ₄ do not, of course, require the same level of bias currents as are necessary for reverse bootstrapping.

Table 3 Characteristics of the conventional and the improved CFOA using half-circuit D

Fig. 29

Input impedance ∼ frequency for the CFOAs, each configured as a non-inverting unity gain amplifier

Fig. 30

Input impedance (inverting) ∼ Frequency

Fig. 31

A CFOA using half-circuit E

Fig. 32

CMRR ∼ Frequency

Fig. 33

AC gain accuracy ∼ Frequency

5.2 Performance with half-circuit F

This differs from half-circuit E in that Q ₁₁, Q ₁₂ now function as emitter-follower transistors rather than diodes

Fig. 34

Frequency responses for unity closed-loop gain

Fig. 35

Transient response

Fig. 36

Input impedance ∼ frequency for the CFOAs, each configured as a non-inverting unity gain amplifier

Fig. 37

Input impedance (inverting) ∼ Frequency

Table 4 Characteristics of the conventional and the improved CFOA using half-circuit E

Fig. 38

A CFOA using half-circuit F

Fig. 39

CMRR ∼ Frequency

Fig. 40

AC gain accuracy ∼ Frequency

Fig. 41

Frequency responses for unity closed-loop gain

Fig. 42

Transient response

5.3 Performance with half-circuit G

The architecture in this is based on the design and use in a repeated pattern of a current-transfer cell.

Table 5 Characteristics of the conventional and the improved CFOA using half-circuit F

Fig. 43

Input impedance ∼ frequency for the CFOAs, each configured as a non-inverting unity gain amplifier

Fig. 44

Input impedance (inverting) ∼ Frequency

Fig. 45

A CFOA using half-circuit G

Fig. 46

CMRR ∼ Frequency

The dotted contour, b, encloses a current-transfer cell (shown earlier, in Fig. 9) which is replicated three times, in NPN form, in the input stage. A similar PNP cell is also replicated three times in the design. The output stage of the CFOA is conventional. The mirror-symmetry of the input stage about an imaginary horizontal line joining the ‘non-inverting’, and ‘inverting’ inputs helps promote a low offset-voltage.

Fig. 47

AC gain accuracy ∼ Frequency

Fig. 48

Frequency responses for unity closed-loop gain

Fig. 49

Transient response

Fig. 50

Input impedance ∼ frequency for the CFOAs, each configured as a non-inverting unity gain amplifier

Table 6 Characteristics of the conventional and the improved CFOA using half-circuit G

Fig. 51

Input impedance (inverting) ∼ Frequency

6 Conclusions

This paper has presented some analysis and discussion that provides insight into a methodology for the design of input stages for high performance CFOAs. For the maximum output voltage swing the input stage of a well-established CFOA is the best option. For comparable slew-rate, but improved CMRR and reduced offset voltage, other choices are possible.

A number of new CFOAs with performances much better than that of the conventional CFOA have been introduced in this paper. A comparison of performance parameters is summarised in Table 7. However, the price paid for these improvements is a reduced output voltage swing, because of vertical transistor stacking, for given rail supply voltages.

Table 7 Comparison of CFOA performance parameters