1 Introduction

Cadmium Zinc Telluride (CdZnTe) is a ternary II-VI semiconductor material with a high atomic number which provides strong absorption [1, 2]. It also has excellent optoelectronic properties and low leakage current due to its wide bandgap properties. CdZnTe is used in many important applications, such as solar cells [3], photodiodes [4], photoconductors [5], room temperature gamma-ray [6], X-ray detectors [7], infrared windows [8] and light-emitting diodes [9]. In this study, a detailed analysis of electrical properties of the CdZnTe/Si structure has been examined and it has been observed that Si semiconductor material could be a suitable heterojunction partner. The reasoning behind the production of CdZnTe/Si diode is the fact that the properties of Si material are very well-known which assists the evaluation of the electrical response of the film in the junction.

National Renewable Energy Laboratory (NREL) and EPIR Technologies conducted studies to develop CdZnTe-based top cells grown on p-Si solar cells as a platform to manufacture high-efficiency tandem cells [10]. Additionally, CdZnTe thin films deposited on Si substrates by molecular-beam epitaxy (MBE) have been studied to facilitate the production of HgCdTe IR detectors [11]. MOVPE growth of thick single crystal CdZnTe epitaxial layers on Si substrates were also studied for nuclear radiation detection applications [12]. In accordance with the corresponding studies, it was necessary to examine the electrical properties of the thermally evaporated CdZnTe/Si diode in a wide range of temperatures and frequencies for possible future applications. Therefore, we have conducted temperature-dependent current-voltage (I–V), frequency-dependent capacitance-voltage \(\left( {C - V} \right) \)and conductance-voltage \(\left( {G - V} \right) \)measurements under dark conditions. Temperature-dependent \(\left( {I - V} \right) \) measurements were performed to analyze the dominant conduction mechanisms through the junction and to determine the main diode parameters. In addition, frequency-dependent \(\left( {C - V} \right) \) and \(\left( {G - V} \right) \)measurements have been conducted to investigate junction properties and to understand the effect of the deep levels on the capacitance. Long-lived traps which are important to identify the physical processes in the diode, the relation between the formation of deep traps and possible degradation mechanisms were explored by extended range of frequencies [13].

2 Experimental details

CdZnTe/p-Si diode structure was prepared on p-type Si substrate having \((100)\) orientation and l Ω∙cm bulk resistivity with 2 × 1017 cm−3 doping concentration. The RCA-cleaned substrate was etched in a 10% HF solution for 10 s immediately before loading into the deposition chamber. Al back contact was thermally evaporated and annealed at 450 °C under the continuous N2 flow to enhance the ohmicity of Al-contact. Then, CdZnTe layer was deposited by thermal evaporation method with a chamber pressure of 1 × 10−6 mbar at room temperature. The CdZnTe crystal pieces, which is used as a source material, were obtained from the ingots produced by Vertical Gradient Freeze (VGF) method in METU-CGL (Crystal Growth Laboratory) with the purity of 99.999% [14]. The rate of evaporation and film thickness were monitored and controlled by InficonXTM/2 quartz crystal monitor and CdZnTe film was deposited with a 5 Å/s evaporation rate and the final film thickness of this layer was measured as ~ 750 nm by Dektak 6 M profilometer. Deposited CdZnTe/p-Si was dipped into a solution of 2.1 g CdCl2 in 100 ml methanol and annealed for 15 min at 300 °C under N2 atmosphere prior to Au front contact formation. CdCl2 treatment is a critical step to improve device performance. Then, 100 nm thick Au front contact was deposited using electron-beam evaporation and the fabricated structure was annealed at 100 °C to enhance the adhesion of the contacts to the film surface. The schematic cross-section of the Au/CdZnTe/p-Si/Al diode structure is shown in Fig. 1.

Fig. 1
figure 1

Schematic cross-section of the Au/CdZnTe/p-Si/Al diode structure

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The temperature-dependent I–V measurements were performed using Keithley 2401 source-meter for the bias voltage of ± 3 V in the temperature range of 220–340 K. For these measurements, a CTI-Cryogenics Model 22 refrigerator system combined with Model SC helium generator was used, and the temperature on the diode was adjusted using a Lakeshore DRC-91C controller. Additionally, the room temperature \(\left( {C - V} \right) \) and

\(\left( {G - V} \right) \)measurements were carried out in a wide frequency range from 1 kHz to 1 MHz using computer-controlled Hewlett Packard 4192A LF model impedance analyzer.

3 Result and discussion

3.1 Temperature-dependent current–voltage analysis

Temperature-dependent \(\left( {I - V} \right) \) measurements were performed to determine the dominant conduction mechanisms and obtain the main diode parameters. Zero-bias barrier height (ϕB0) and ideality factor (\(n\)) are the two important parameters determined from \(\left( {I - V} \right) \) plots using thermionic emission (TE) theory. According to the diode equation [15], the forward-biased current can be modeled as;

$$I = I_{0} \left[ {\exp \left( {\frac{{{\text{qV}}}}{{{\text{nkT}}}}} \right) - 1} \right]$$
(1)

where \({I}_{0}\) is the reverse-saturation current, \(q\) is the electronic charge, \(V\) is the voltage value in the forward bias region, \(n\) is the ideality factor, \(k\) is the Boltzmann constant and \(T\) is the ambient temperature. Figure 2 shows the \(\left( {I - V} \right) \) characteristics of CdZnTe/Si diode structure at various ambient temperatures. According to the measurement results, the forward current is higher than the reverse-biased current for all temperature values.

Fig. 2
figure 2

\(I-V\) characteristics of CdZnTe/p-Si diode structure at various ambient temperatures

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Intercepts of the \(\left( {I - V} \right) \) plot with the current axis give the value of the I0 values at any given temperature. I0 value was used to estimate the ϕB0 values using the relation

$$q\Phi_{B0} = - kT\ln \left( {\frac{{I_{0} }}{{A^{*} AT^{2} }}} \right)$$
(2)

where \(A^*\) is the effective Richardson constant and \(A\) s the device area. \(A^*\) value for p-type Si was used as 32 Acm−2 k2 under the assumption of uniform barrier height formation in the diode [15]. The obtained \(n\), \({I}_{0}\), and \({\Phi}_{B0}\) values for each temperature are tabulated in Table 1.

Table 1 Diode parameters of CdZnTe/p-Si structure under dark conditions in the temperature range of 220–340 K
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As stated in Table 1, the increase in \({\Phi}_{B0}\) and decrease in \(n\) with increasing temperature indicates an improvement in the junction [16]. The increase in \({\Phi}_{B0}\) with temperature provides smaller leakage current and therefore an increase in the rectification behavior. However, at lower temperatures, the ideality factor much greater than unity results in deterioration of the device parameters [17]. Because of the observed temperature dependency in the analysis, the current transport at low temperatures was controlled by the current flowing across the patches of low barrier heights, resulting in a higher \(n\) value [18]. An apparent increase in the n and a decrease in the barrier height at low temperatures are probably caused by inhomogeneous barrier formation from low barrier patches [19]. However, TE theory is based on homogeneous barrier height formation in the junction. Considering the inhomogeneous barrier height formation and deviation from TE theory, Gaussian distribution (GD) of barrier height was studied based on a mean value \(\bar{\Phi}_{B0}\) with the standard deviation of \({\sigma }_{0}\) to explain the carrier transport mechanism across the junction [20,21,22,23]. This approximation has been achieved by determining the degree of barrier height variation under the Tung’s theoretical approach [24] and a good linear relationship between \({\Phi}_{B0}\) and \(n\) was obtained in Fig. 3. In Tung’s model, bias and temperature dependent diode parameters extracted from bias and temperature independent patch parameters [24].

Fig. 3
figure 3

The linear relation between barrier height and ideality factor for CdZnTe/p-Si diode structure

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GD model was used to describe the potential fluctuations considering a continuous barrier distribution at the interface. Using the GD model, the total current is expressed as a sum of the current flows in all individual barrier patches [25]. Therefore, the total junction current dominated by low barrier patches is given as:

$$I = AA^{*} T^{2} \exp \left[ {\left( {- \frac{qV}{{kT}}} \right)\left( { \Phi- \frac{{q\sigma_{0}^{2} }}{2kT}} \right)} \right]\exp \left( {\frac{qV}{{n_{ap} kT}}} \right)\left[ {1 - \exp \left( { - \frac{qV}{{kT}}} \right)} \right]$$
(3)

with modified reverse saturation current,

$$I_{0} = AA^{*} T^{2} \exp \left( { - \frac{{q\Phi _{ap} }}{kT}} \right)$$
(4)

where \({n}_{ap}\) and \({\Phi}_{ap}\) are the apparent ideality factor and apparent barrier height, respectively. Using GD function, \({\Phi}_{ap}\) can be expressed as the temperature variation in \({\Phi}_{B0}\):

$$\Phi_{{{\text{ap}}}} = \overline{\Phi }_{{{\text{B0}}}} - \frac{{q\sigma_{0}^{2} }}{2kT}$$
(5)

As represented in Fig. 4(a), \({\Phi}_{B0}\) has a linear relation with \(q/2kT\) and from the analysis of intercept and slope, \(\bar{\Phi}_{B0}\) and \({\sigma }_{0}\) have been determined, respectively. The value of \({\sigma }_{0}\) was found to be 0.18 while the \(\bar{\Phi}_{B0}\) value was obtained as 1.31 eV. In the GD model, \({\sigma }_{0}\), which is a measure of the barrier homogeneity, shows 14% deviation from the mean value \(\bar{\Phi}_{B0}\). According to the obtained values, the forward-biased current mechanism in CdZnTe/Si diode conforms to a junction with GD of barrier height due to inhomogeneity of the interface layer and non-uniformity of interface charges. According to the GD model, \({\rho }_{2}\) and \({\rho }_{3}\), the coefficients indicating the voltage deformation of the barrier height distribution can be extracted from the following equation

$$\left( {\frac{1}{{n_{ap} }} - 1} \right) = - \rho_{2} + \frac{{q\rho_{3} }}{2kT}$$
(6)
Fig. 4
figure 4

Plot of a \({\Phi}_{B0}\) vs. \(q/2kT\), and b \(\left({n}^{-1}-1\right)\) vs. \(q/2kT\) for CdZnTe/p-Si diode structure

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While Eq. 6 examines the relation between temperature and \(n\), Fig. 4(b) shows the corresponding voltage deformation of the GD of the barrier height with respect to \(n\). The voltage coefficients were determined from the intercept and slope of the straight line as, \({\rho }_{2}\) = 0.0153 V and \({\rho }_{3}\) = 0.387, respectively.

Finally, modified Richardson constant \({A}^{*}\) was calculated for GD type inhomogeneous barrier height. Using Eq. 3, modified \({A}^{*}\) can be determined as

$$\left( {\frac{{I_{0} }}{{T^{2} }}} \right) - \left( {\frac{{q^{2} \sigma_{s}^{2} }}{{2k^{2} T^{2} }}} \right) = \ln \left( {AA^{*} } \right) - \frac{{q\overline{\Phi }_{B0} }}{kT}$$
(7)

The modified Richardson plot using Eq. 7 was given in Fig. 5. The \({\overline{\Phi}}_{B0}\) and \({A}^{*}\) values were found as 1.32 eV and 32.095 Acm−2 k−2 from the slope and intercept of the

Fig. 5
figure 5

\(ln[\left({I}_{0}/{T}^{2}\right)-\left({q}^{2}{\sigma }_{0}^{2}\right)/\left(2{k}^{2}{T}^{2}\right)]\) vs. \(q/kT\) for CdZnTe/p-Si diode structure

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\(ln[\left({I}_{0}/{T}^{2}\right)-\left({q}^{2}{\sigma }_{0}^{2}\right)/\left(2{k}^{2}{T}^{2}\right)]\) vs. \(q/kT\) plot, respectively. The value of \({\overline{\Phi}}_{B0}\) obtained using Eqs. 4 and 7, were found to be very similar. Even the inhomogeneity of the barrier height exists in the diode, the modified \({A}^{*}\) value was in accordance with the reported values [26].

3.2 Frequency-dependent capacitance–voltage analysis

In this study, the frequency dependence of the forward and reverse bias \( \left( {I - V} \right) \) and \( \left( {G - V} \right) \) characteristics of Au/CdZnTe/p-Si/Al diode structure have been investigated in the frequency range of 1 kHz – 1 MHz and voltage range of \(\pm\) 3 V at room temperature.

As can be seen in Fig. 6a, b, capacitance and conductance of the diode show sensitivity to applied voltage and frequency. Capacitance values are decreasing while conductance increases with increasing frequency. The obtained higher values of capacitance at low frequencies in Fig. 6a can be attributed to the carrier charges at surface traps and their relaxation time, since they can easily follow the ac signal and yield an excess in the measured capacitance [27]. The capacitance at high frequency represents the response of free carriers, while capacitance at low frequency represents the response of not only free carriers but also deep trap levels [27,28,29]. Significant amount of deep trap levels may co-exist with the shallow levels and contribute noticeably to the space charge [30]. This is because the CdZnTe film may be non-intentionally doped which suggests that the free carriers are due to the defects. These defects may be intrinsic to the polycrystalline CdZnTe or due to extrinsic impurities such as Cl resulting from CdCl2 treatment [31]. Ideally, the \( \left( {C - V} \right) \) and \( \left( {G - V} \right) \) characteristics are expected to be independent of frequency. Several mechanisms can give rise to a frequency dependent capacitance and conductance such as, Schottky barrier behavior, deep traps in CdZnTe, Cl diffusion, the front contact, interface traps and high series resistance [32, 33].

Fig. 6
figure 6

Frequency dependence of a \( \left( {C - V} \right) \) and b \( \left( {G - V} \right) \) plots of CdZnTe/p-Si diode structure at room temperature

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Additionally, \({R}_{s}\) (series resistance) and \({D}_{it}\) (Density of interface traps) are important parameters that significantly change both the \( \left( {C - V} \right) \) and \( \left( {G - V} \right) \) characteristics from ideal cases [32]. \({R}_{s}\) parameter is effective in the forward bias region for high frequencies, while \({D}_{it}\) is effective at low frequencies.

3.2.1 Series resistance (\({\mathbf{R}}_{\mathbf{s}}\))

It should be noted that the value of series resistance can affect both capacitance and conductance characteristics. The value of voltage-dependent resistance \({R}_{i}\) can be extracted in the total measured range as

$$R_{i} = \frac{{G_{m} }}{{G_{m}^{2} + \left( {\omega C_{m} } \right)^{2} }}$$
(8)

where \(\omega\)\((2\pi f)\) is the angular frequency and \({C}_{m}\) and \({G}_{m}\) are the measured capacitance and conductance values for any voltage. Although this approach evaluates the effects of parasitic resistance in the total measured range, at sufficiently high frequencies \((f\ge 300 kHz)\) and in the positive voltage region, it can be used to calculate the \({R}_{s}\) values [22, 23, 32].

The applied bias voltage and frequency dependence profile of the \({R}_{s}\) were evaluated according to Eq. 8 for high frequencies, and its characteristic behavior is presented in Fig. 7. As shown in the figure, the value of \({R}_{s}\) increased with decreasing frequencies due to the impurities at CdZnTe/Si interface layer, front metal contact, and CdZnTe layer.

Fig. 7
figure 7

\({R}_{s}\) at different frequencies for the forward bias region of CdZnTe/p-Si diode structure under the dark condition at room temperature

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3.2.2 The density of interface traps \({(\mathbf{D}}_{\mathbf{i}\mathbf{t}}\))

\({D}_{it}\) can be attributed to the periodic lattice structure at the surface, surface preparation, interfacial layer, and impurities in the semiconductor. Hill-Coleman approximation technique is a quantitative method to obtain the density of interface traps [34]. According to this approximation, frequency-dependent \( \left( {C - V} \right) \) and corresponding \(G/w-V\) plots are required for the estimation of \({D}_{it}\). As a result, frequency dependence distribution of \({D}_{it}\) can be determined as [35];

$$ D_{{it}} = \left( {\frac{2}{{qA}}} \right)\frac{{\left( {G_{m} /w} \right)_{{\max }} }}{{\left( {\left( {G_{m} /w} \right)_{{\max }} /C_{i} } \right)^{2} + \left( {1 - C_{m} /C_{i} } \right)^{2} }},\,\,\,C_{i} = C_{m} \left[ {1 + \frac{{G_{m} }}{{wC_{m} }}} \right] $$
(9)

where \(q\) is the elementary charge, \(A\) is the diode area, \({G}_{m}/w\) is the max-peak value of the measured conductance as shown in Fig. 8(a), \({C}_{m}\) is the corresponding measured capacitance value and \({C}_{i}\) is the interfacial capacitance.

Fig. 8
figure 8

Plots of a \(G/w-V\) and b Corresponding frequency dependent distribution of \({D}_{it}\) obtained using Hill- Coleman method for CdZnTe/p-Si diode structure

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The conductance can be considered as a measure of the interface trap density. It indicates loss mechanisms resulting from the capture of interface traps and emission of carriers [36]. To determine the distribution of density of interface trap, \(G/w\) was calculated using each \( \left( {C - V} \right) \) and \( \left( {G - V} \right) \) plots at several modulation frequencies. \(G/w-V\) is then plotted to extract the maximum value of \(G/w\) at each frequency which in turn gives rise to \({D}_{it}\).

The frequency distribution of the calculated \({D}_{it}\) values is given in Fig. 8(b) and the profile of the \({D}_{it}\) shows a decreasing behavior when the applied frequency increased. When interface traps exist at the interface, the device behavior deteriorated due to these traps and their lifetime [36]. At low frequencies, the interface traps can follow the ac signal and cause an increase in calculated \({D}_{it}\). Nevertheless, the interface traps at high frequencies cannot follow an ac signal [34].

4 Conclusion

In this study, the electrical properties of the CdZnTe/p-Si structure were investigated using temperature-dependent \( \left( {I - V} \right) \) and frequency-dependent \( \left( {C - V} \right) \) and \( \left( {G - V} \right) \) profiles. These profiles allowed us to understand the carrier conduction mechanism and the nature of the interfacial layer of the CdZnTe/p-Si structure. \( \left( {I - V} \right) \) analysis indicated that the junction behavior showed good rectification. Hence, Si material can be considered as a suitable heterojunction partner to CdZnTe. Due to the inhomogeneity of the barrier height, as the temperature of the ambient increased, \(n\) value of the diode decreased while \({\Phi}_{B0}\) was increasing. It has been confirmed that the inhomogeneity of the barrier height had a Gaussian Distribution behavior with \({\overline{\Phi}}_{B0}\) and \({\sigma }_{0}\) as 1.31 eV and 0.18, respectively. Additionally, using a modified Richardson plot, modified \({A}^{*}\) was calculated as 32.09 A cm−2 K−2 which was approximately the same as the theoretical value for p-Si. Moreover, capacitance results showed sensitivity to frequency and decreased with increasing frequency. \({R}_{s}\) value was observed to be more effective on the impedance measurements at high frequencies in the forward bias region while \({D}_{it}\) was effective at low frequencies. Such non-uniformity in CdZnTe/Si structure was expected due to the diffusion mechanism of the extrinsic impurities such as Cl and the distribution of deep level traps from the complex nature of CdZnTe deposition and processing.