Temperature and SiO₂/4H-SiC interface trap effects on the electrical characteristics of low breakdown voltage MOSFETs

Abstract

The temperature and carrier-trapping effects on the electrical characteristics of a 4H silicon carbide (4H-SiC) metal–oxide–semiconductor field effect transistor (MOSFET) dimensioned for a low breakdown voltage (BV_DS) are investigated. Firstly, the impact of the temperature is evaluated referring to a fresh device (defects-free). In particular, the threshold voltage (V_th), channel mobility (µ_ch), and on-state resistance (R_ON) are calculated in the temperature range of 300 K to 500 K starting from the device current–voltage characteristics. A defective MOSFET is then considered. A combined model of defect energy levels inside the 4H-SiC bandgap (deep and tail centers) and oxide-fixed traps is taken into account referring to literature data. The simulation results show that the SiO₂/4H-SiC interface traps act to increase R_ON, reduce µ_ch, and increase the sensitivity of V_th with temperature. In more detail, the deep-level traps in the mid-gap have a limited effect in determining R_ON once the tail traps contributions have been introduced. Also, for gate biases greater than about 2V_th (i.e., V_GS > 12 V) the increase of mobile carriers in the inversion layer leads to an increased screening of traps which enhances the MOSFET output current limiting the R_ON increase in particular at low temperatures. Finally, a high oxide-fixed trap density meaningfully influences V_th (negative shifting) and penalizes the device drain current over the whole explored voltage range.

1 Introduction

Metal–oxide–semiconductor field effect transistors (MOSFETs) in silicon carbide (SiC) are very attractive devices in modern power electronics [1]. They are widely appreciated for their high efficiency, low on-state resistance (R_ON), and noticeable switching capabilities. Typical SiC MOSFETs are designed to support high blocking voltages (BV_DS) ranging from 600 to 1700 V [2,3,4]. Recent papers, however, have also investigated low breakdown voltage 4H-SiC MOSFETs to be used for photovoltaic (PV) module-level applications enabling operation in harsh conditions with considerable lifetime [5,6,7,8,9,10]. Power optimizers in PV modules are generally rated for voltages in the order of 100–200 V.

The main technological issue of an SiC-based MOSFET is the effective quality of the silicon oxide (SiO₂) interface that could make the device much less efficient. Defects occurring at the SiO₂/4H-SiC interface, in fact, heavily affect the device current capability [11,12,13,14]. In more detail, the interface trap effects tend to decrease the carrier mobility in the channel region through the enhanced scattering mechanisms of free carriers. At the same time, traps increase the R_ON value and the sensitivity of the threshold voltage (V_th) with temperature.

In this context, the aim of the paper is to investigate, by means of a careful numerical simulation study, the electrical characteristics of a 4H-SiC MOSFET designed for low-voltage ratings (BV_DS = 150 V) over a wide range of temperatures. Without loss of generality with respect to different designs dimensioned for higher blocking voltages, explicit interface trap effects due to a detailed density of states in the inversion region and a fixed trap density in the oxide are considered referring to literature data. A preliminary study at room temperature, which neglects defect and trap effects, was presented in Refs. [5, 6] emphasizing the use of fast and rugged 100-V-class switches.

The obtained results clarify the role of interface traps in reducing carrier mobility in the channel region (µ_ch). Also, V_th decreases as a function of both trap density and temperature. In particular, a high oxide-fixed trap density meaningfully influences V_th. Finally, this analysis indicates that deep-level traps at the 4H-SiC interface have only a limited effect in determining the MOSFET R_ON once the tail traps contributions have been introduced. The R_ON value is 200 kΩ μm² for a defective device at V_GS = 10 V, V_DS = 1 V, and T = 300 K. This result is compared to the state-of-the-art of a commercial Si-MOSFET with the same BV_DS supporting the opportunity to explore the use of 4H-SiC also for low-voltage applications where efficiency, robustness, miniaturization, and temperature control are critical targets.

2 MOSFET structure

The schematic cross-section of the considered vertical n-channel 4H-SiC MOSFET single-cell is shown in Fig. 1. The different geometrical parameters are labeled as follows: W_cell is the cell width, W_G is the gate contact width, L_ch is the device channel length, W_J is the distance between the base regions, X_N+ is the n+-source junction depth, X_P is the p-base junction depth, W_drift is the n-drift region thickness, $W_{{_{\text{drift}} }}^{\prime }$ is the base-to-substrate distance, and W_sub is the starting substrate thickness. The source contact shorts the source and base regions to prevent the switch-on of the parasitic substrate(n⁺)–epilayer(n)–base(p)–source(n⁺) bipolar junction transistor. The reference geometrical and doping parameters used during the simulations are summarized in Table 1.

Fig. 1

Cross-sectional view of the n-channel 4H-SiC MOSFET single-cell. The drawing is not to scale

Table 1 MOSFET reference parameters (Fig. 1)

From Table 1, the distance between the n⁺-source region and the n-epilayer (i.e., X_P–X_N+) is 0.8 μm. The epilayer thickness ensures a BV_DS value close to 150 V.

Although simplified for simulation purposes, the proposed structure is in principle compatible with a manufacturing process based on doping by ion implantation [15,16,17].

3 Physical models

The numerical simulation analysis was performed using the Atlas-Silvaco TCAD physical simulator [18]. The device structure was fine meshed wherever appropriate and in particular around the p–n junctions and the surface channel region under the SiO₂/4H-SiC interface. The total number of mesh points was about 32,000 and the mesh spacing was scaled down to 0.5 nm at the interfaces.

The key physical models taken into account include the material bandgap temperature dependence, apparent bandgap narrowing effect, Auger and Shockley–Read–Hall recombination phenomena, incomplete doping activation, impact ionization, and carrier lifetime and carrier mobility expressions depending on temperature and doping concentration [19,20,21,22,23,24]. Moreover, Fermi–Dirac statistics and multidimensional dependent anisotropic effects as well as scattering mechanisms that degrade the channel mobility were considered during the simulations.

Parameters details about the simulation setup for 4H-SiC-based devices are reported in recent manuscripts of ours where the models prediction capabilities are also supported by experimental results obtained on implanted diodes over wide ranges of current and temperature [25,26,27,28,29,30].

In this paper, to address the defect and trap effects at the SiO₂/4H-SiC interface, we solve Poisson’s equation in the channel region in the form

$$\nabla \cdot \left( {\varepsilon \nabla \varPsi } \right) = q\left( {n - p - N_{\text{D}}^{ + } + N_{\text{A}}^{ - } } \right) - Q_{\text{T}} ,$$

(1)

where an overall trapped charge contribution Q_T is considered in addition to the ionized donor $(N_{\text{D}}^{ + } )$ and acceptor $(N_{\text{A}}^{ - } )$ impurity concentrations to describe the variation of the electrostatic potential ψ with the local (total) charge density.

According to [31], the incomplete ionization of impurities is given by

$$N_{\text{A}}^{ - } ,_{\text{D}}^{ + } = N_{\text{A,D}} \left( {\frac{{ - 1 + \sqrt {1 + 4g_{\text{v,c}} \frac{{N_{\text{A,D}} }}{{N_{\text{V,C}} (T)}}e^{{\frac{{E_{\text{A,D}} }}{kT}}} } }}{{2g_{\text{v,c}} \frac{{N_{\text{A,D}} }}{{N_{\text{V,C}} (T)}}e^{{\frac{{E_{\text{A,D}} }}{kT}}} }}} \right),$$

(2)

where N_D and N_A are the substitutional n-type and p-type doping concentrations, N_C and N_V are the electron and hole density of states varying with temperature, g_c = 2 and g_v = 4 are the degeneracy factors of the conduction and valence band, and E_D = 100 meV and E_A = 200 meV are the donor and acceptor energy levels assuming nitrogen and aluminum as doping species, respectively.

The interface density of states (DoS) in the 4H-SiC inversion layer is modeled by the following expression [32, 33]:

$$D_{it} (E) = D_{{it,{\text{T}}}} + D_{{it,{\text{M}}}} ,$$

(3)

where $D_{{it,{\text{M}}}}$ is a Gaussian distribution of deep states in the mid-gap and $D_{{it,{\text{T}}}}$ is the sum of two exponentially decaying band tail states close to the conduction and valence band-edges, respectively. In more detail, we can write

$$D_{{it,{\text{T}}}} = D_{{t,{\text{TC}}}}^{0} \exp^{{[(E - E_{\text{C}} )/U_{\text{C}} ]}} + D_{{t,{\text{TV}}}}^{0} \exp^{{[(E_{\text{V}} - E)/U_{\text{V}} ]}} ,$$

(4)

$$D_{{it,{\text{M}}}} = D_{{t,{\text{M}}}}^{0} \exp^{{[(E - E_{\text{M}} )/W_{\text{M}} ]^{2} }} ,$$

(5)

where E_C and E_V are the conduction and valence band energies, U_C and U_V are characteristic energy decays, $D_{{t,{\text{TC}}}}^{0}$ and $D_{{t,{\text{TV}}}}^{0}$ are the band edge intercept densities, W_M takes into accounts the spectral width of the mid-gap Gaussian distribution, and E_M is the energy value of the defect density peak $D_{{t,{\text{M}}}}^{0}$.

In Eq. (3) each term acts either as donor-like or acceptor-like level for free carriers [18]. In other words, a donor-like center is positively charged (ionized) when empty and neutral when filled (with an electron), while an acceptor-like center is negatively charged (ionized) when filled and becomes neutral when empty.

The total charge Q_t is therefore expressed by

$$Q_{t} = q(D_{{it,{\text{D}}}}^{ + } - D_{{it,{\text{A}}}}^{ - } ),$$

(6)

where referring to the terms $D_{{it,{\text{M}}}}$ and $D_{{it,{\text{T}}}}$ introduced above, $D_{{it,{\text{D}}}}^{ + }$ and $D_{{it,{\text{A}}}}^{ - }$ are the ionized densities for donor-like and acceptor-like traps, respectively. In particular, each ionized density depends upon the trap density and the relative probability of ionization that is in the form of

$$F_{{t,{\text{D}}}} = \frac{{v_{\text{th}} \sigma_{\text{n}} + e_{\text{p}} }}{{v_{\text{n}} (\sigma_{\text{p}} + \sigma_{\text{n}} ) + (e_{\text{n}} + e_{\text{p}} )}},$$

(7)

$$F_{{t,{\text{A}}}} = \frac{{v_{\text{th}} \sigma_{\text{p}} + e_{\text{n}} }}{{v_{\text{p}} (\sigma_{\text{p}} + \sigma_{\text{n}} ) + (e_{\text{n}} + e_{\text{p}} )}}.$$

(8)

Here, v_n and v_p are the carrier thermal velocities, and σ_n and σ_p are the trap capture cross sections for electrons and holes, respectively. Finally, e_n and e_p are the trap emission rates given by

$$e_{\text{n}} = v_{\text{n}} \sigma_{\text{n}} n_{\text{i}} \exp \left( {\frac{{E - E_{\text{i}} }}{kT}} \right),$$

(9)

$$e_{\text{p}} = v_{\text{p}} \sigma_{\text{p}} n_{\text{i}} \exp \left( {\frac{{E_{\text{i}} - E}}{kT}} \right),$$

(10)

where E_i is the intrinsic Fermi level and n_i is the intrinsic carrier concentration.

The fundamental DoS parameters used during the simulations are listed in Table 2 [18, 33, 34]. In particular, the trap density reference values are assumed as in Ref. [33].

Table 2 DoS parameters

Finally, the Caughey–Thomas expression describes the temperature-dependent carrier mobility as

$$\mu_{\text{n,p}} = \mu_{{0{\text{n,p}}}}^{\hbox{min} } \left( {\frac{T}{300}} \right)^{{\alpha_{n,p} }} + \frac{{\mu_{{0{\text{n,p}}}}^{\hbox{max} } \left( {\frac{T}{300}} \right)^{{\beta_{\text{n,p}} }} - \mu_{{0{\text{n,p}}}}^{\hbox{min} } \left( {\frac{T}{300}} \right)^{{\alpha_{\text{n,p}} }} }}{{1 + \left( {\frac{T}{300}} \right)^{{\gamma_{n,p} }} \left( {\frac{N}{{N_{\text{n,p}}^{\text{crit}} }}} \right)^{{\delta_{\text{n,p}} }} }},$$

(11)

where the µ_0n,p terms are the carrier mobilities assumed at room temperature, N is the local doping concentration, $N_{\text{n,p}}^{\text{crit}}$ is the doping concentration at which the mobility is halfway between its maximum and minimum value, and α, β, γ, and δ are process-dependent coefficients [35]. This model was experimentally validated for SiC in Ref. [36].

The expected mobility reduction due to the carrier saturated drift velocity (v_sat = 2 × 10⁷ cm/s) was modeled for high electric fields by using

$$\mu_{\text{n,p}} (E) = \frac{{\mu_{\text{n,p}} }}{{\left[ {1 + \left( {E\frac{{\mu_{\text{n,p}} }}{{v_{\text{sat}} }}} \right)^{{\kappa_{\text{n,p}} }} } \right]^{{\frac{1}{{\kappa_{\text{n,p}} }}}} }},$$

(12)

where E is the electric field in the direction of the current flow, and κ_n = 2 and κ_p= 1 [18]. In addition, mobility degradation effects that had taken place in the inversion layer can be written as

$$\mu_{\text{n,p}} (E_{ \bot } ) = \frac{{\mu_{\text{n,p}} }}{{\sqrt {1 + \frac{{E_{ \bot } }}{{E_{\text{n,p}}^{\text{crit}} }}} }},$$

(13)

where $E_{\text{n,p}}^{\text{crit}}$ is an adjustable parameter, and $E_{ \bot }$ is the perpendicular electric field component which originates different scattering mechanisms involving surface-phonons, surface-roughness, and Coulombic scattering [18].

4 Results and discussion

4.1 I–V–T characteristics in absence of trap effects

A first set of simulations was addressed to clarify the dependence of BV_DS on thickness (W_drift) and doping (N_drift) of the device epitaxial layer. In particular, with the MOSFET in off-state (V_G = 0 and grounded source) V_DS was gradually increased until the drain leakage current density reached a maximum value of 10 mA/cm². Starting from W_drift = 10 µm and N_drift = 1×10¹⁶ cm⁻³, we calculated BV_DS close to 900 V. This value corresponds to a critical electric field of 1.9 MV/cm. Then, W_drift was reduced down to 1.8 µm as summarized in Table 3. It must highlighted that BV_DS is strictly dependent on W_drift which in fact determines the effective distance $W_{{_{\text{drift}} }}^{\prime }$ between the base junction and the substrate, i.e., W_drift − X_P in Fig. 1.

Table 3 BV_DS as a function of W_drift for N_drift = 1×10¹⁶ cm⁻³

By decreasing N_drift from 1×10¹⁶ cm⁻³ to 1×10¹⁵ cm⁻³ we observed a maximum reduction of BV_DS on the order of 10%. For example, for N_drift = 3×10¹⁵ cm⁻³ we obtained BV_DS = 150 V for W_drift = 1.8 µm and BV_DS = 850 V for W_drift = 10 µm as in Ref. [6]. It is worth noting that N_drift has only a limited impact in determining BV_DS for W_drift ≤ 3 µm.

The 4H-SiC MOSFET in Table 1 is a structure considered free of interface defects and traps (fresh device). The current density curves I_D − V_DS and I_D − V_GS calculated at different temperatures for the half-cell in Fig. 1 (active area 7.5 µm²) are shown in Figs. 2 and 3, respectively.

Fig. 2

Forward I_D − V_DS characteristics for the device in Table 1 at T = 300 K, T = 400 K, and T = 500 K

Fig. 3

I_D − V_GS curves for the device in Table 1 at different temperatures

As expected, the drain current decreases harshly when increasing temperature. This effect is determined by the temperature dependence of carrier mobility in the inversion layer and the overall increase of the device on-state resistance.

In more detail, the degradation of the total carrier mobility behavior in the channel region is shown in Fig. 4. Here, the temperature dependence of the threshold voltage is also reported by imposing during the simulations a subthreshold current in the limit of 10 nA. The plot is traced by taking a cut-line of the device structure for V_GS = 15 V and V_DS = 1 V.

Fig. 4

Channel mobility and device threshold voltage as a function of the temperature

The decrease of V_th and µ_ch with temperature is due to the increase of the 4H-SiC intrinsic carrier concentration. These variations determine different values of the device transconductance which results 25 s at T = 300 K and decreases to about 10 s at T = 500 K in the considered range of V_GS.

From Fig. 3, the drain current density for V_GS = 15 V and V_DS = 1 V at T = 300 K is 7.11 μA/μm² (I_D = 53.32 μA). The corresponding MOSFET R_ON is therefore calculated as close to 140 kΩ μm². The R_ON behavior as a function of the temperature is shown in Fig. 5. Here, the R_ON increase with temperature is mainly due to the decrease of carrier mobility in the inversion layer as well as in the drift region [37]. In other words, the increased temperature limits the current components in these two regions.

Fig. 5

On-state resistance and drain current density as a function of the temperature

4.2 Analysis of trap effects at the SiO₂/4H-SiC interface

4.2.1 Tail traps

Introducing in the model a constant value of deep traps in the mid-gap, i.e., $D_{{t,{\text{M}}}}^{0} = 2. 3\times 1 0^{ 1 1} \,\,{\text{cm}}^{ - 2} \,\,{\text{eV}}^{ - 1}$ [33], Fig. 6 depicts the device I_D − V_GS characteristics in semi-logarithmic scale calculated for a different band tail trap density at T = 300 K, T = 400 K, and T = 500 K. In particular, in Eq. (4) we have assumed the band edge intercept density in the range from 10¹² cm⁻² eV⁻¹ to 10¹⁴ cm⁻² eV⁻¹ [33, 38]. In addition, it is important to note that the traps with energetic states close the valence band can be neglected once the contribution $D_{{t,{\text{TC}}}}^{0} \exp^{{[(E - E_{\text{C}} )/U_{\text{C}} ]}}$ has been considered. In this study, in fact, when the device is forward biased, even in weak inversion condition, the Fermi level increasingly moves in the upper half of the bandgap.

Fig. 6

I_D − V_GS characteristics as a function of the tail trap density at a T = 300 K, b T = 400 K, and c T = 500 K

From Fig. 6, similarly to the fresh device, V_th tends to decrease as the temperature increases. For V_GS > V_th, the saturated value of I_D is almost the same until the tail trap density is in the limit of 10¹³ cm⁻² eV⁻¹. Then, for example for $D_{{t,{\text{TC}}}}^{0}$ = 10¹⁴ cm⁻² eV⁻¹, the device current capabilities are meaningfully penalized at any V_DS bias level.

When a positive V_GS is applied, the acceptor defect states are able to trap a great number of electrons from the inversion layer, thus making them immobile and excluding them from carrier transport mechanisms. In addition, at each temperature, these filled traps cause Coulomb scattering phenomena of mobile charges that determine in turn a reduced drain current and a positive shift of the threshold voltage. The more the temperature increases, the more the number of filled traps decreases; hence V_th decreases as stated above.

The MOSFET R_ON behaviors as a function of V_GS for both a fresh and a defective device are shown in Fig. 7. The R_ON of a heavily defective device dramatically increases for increasing temperature in particular at low biases (V_GS ≤ 12 V) as a consequence of the mobility degradation induced by traps [39]. For V_GS> 12 V, however, the increase of mobile carriers leads to an increased screening of traps which supports the MOSFET output current limiting the R_ON increase especially at low temperatures.

Fig. 7

R_ON as a function of V_GS at different temperatures for fresh (open symbols) and defective (solid symbols) device. $D_{{t,{\text{T}}}}^{0}$ = 10¹⁴ cm⁻² eV⁻¹, $D_{{t,{\text{M}}}}^{0}$ = 2.3 × 10¹¹ cm⁻² eV⁻¹

4.2.2 Deep-level traps

The MOSFET I_D − V_GS characteristics for two different distributions of deep-level traps (not exceeding a peak value of 10¹² cm⁻² eV⁻¹ [38]) are shown in Fig. 8. A fixed band edge intercept density $D_{{t,{\text{T}}}}^{0}$ = 10¹³ cm⁻² eV⁻¹ was assumed during the simulations.

Fig. 8

I_D − V_GS characteristics as a function of the deep-level trap density at a T = 300 K, b T = 400 K, and c T = 500 K

In this case, the trap effects mostly occur at the beginning of the I_D curves determining, once again, an increase in the device threshold voltage. In other words, since the tail traps contribution has been introduced, the effect of the trapped charge in the deep-level traps on the slope of the I_D curves in Fig. 8 is negligible and, in fact, for V_GS> 10 V the drain current appears not affected. This result is shown in more detail in Fig. 9 by plotting the R_ON behaviors as a function of V_GS at different temperature (11 ≤ V_GS ≤ 15 V).

Fig. 9

R_ON as a function of V_GS for different deep-level trap densities in the temperature range of 300–500 K. V_DS = 1 V

4.2.3 Oxide-fixed traps

Moving from the developed analysis on the interface-trapped charges which are related to the defect energy levels inside the 4H-SiC bandgap, in order to determine the effective MOSFET current capability, in this section we have involved in the model an oxide-fixed trap effect as shown in Fig. 10. In particular, we have considered a thin film of fixed traps located in the oxide next to the SiO₂/4H-SiC interface with a charge density N_fix = 1.3 × 10¹² cm⁻² [33].

Fig. 10

I_D − V_GS characteristics for an oxide-fixed trap density at different temperatures. V_DS = 1 V

The oxide-fixed traps, which have a density strictly dependent on the 4H-SiC surface oxidation process, became scattering centers that influence the device threshold voltage as shown in Fig. 11. Here, the carrier mobility degradation in the inversion layer is also reported.

Fig. 11

Channel mobility and device threshold voltage as a function of the oxide-fixed trap density at T = 300 K

From Fig. 11, it is clear that the MOSFET threshold voltage significantly decreases in presence of an explicit oxide-fixed trap density. These centers, in fact, by acting as positive charges produce a band bending at the semiconductor interface even without the application of a positive bias voltage at the gate contact [40, 41]. In other words, the band bending for a p-type MOSFET tends to induce a depletion region (channel region) before V_GS is applied. This effect obviously reduces V_th at any operation temperature. In addition, due to the Coulombic scattering [42], the effective carrier mobility in the inversion layer is degraded as well.

The comparison of the defective device in Fig. 10 ($D_{{t,{\text{T}}}}^{0}$ = 10¹³ cm⁻² eV⁻¹, $D_{{t,{\text{M}}}}^{0}$  = 10¹² cm⁻² eV⁻¹, and N_fix = 1.3 × 10¹² cm⁻²) and the fresh one in Fig. 3 in terms of R_ON at different temperatures is shown in Fig. 12.

Fig. 12

R_ON behaviors as a function of V_GS at different temperatures

Here, the datasheet value R_ON = 216 kΩ μm² for a Si-based commercial MOSFET rated for 150 V at V_GS = 10 V and T = 300 K is also reported [43]. This value is slightly higher than that calculated for the proposed device at the same bias level, namely R_ON = 200 kΩ μm². In presence of an oxide-fixed trap effect, the R_ON behavior tends to increase over the whole explored V_GS range in particular at the higher temperatures that increasingly contribute to limit the drain current.

5 Conclusion

The temperature and carrier-trapping effects on the electrical characteristics of a 4H-SiC MOSFET have been predicted by means of numerical simulations. A combined model of defect energy levels inside the 4H-SiC bandgap (tail and deep-level traps) and oxide-fixed traps has been considered. The trap densities have been assumed referring to literature data. The device exhibits an epilayer thickness of 1.8 µm and a breakdown voltage of 150 V.

Starting from a defect-free structure we have calculated an on-state resistance close to 140 kΩ μm² (V_GS = 10 V, V_DS = 1 V, and T = 300 K), which increases up to 200 kΩ μm² for a defective device. This result is comparable to that of a commercial Si-based MOSFET rated for the same voltage range. The MOSFET threshold voltage and carrier mobility in the channel region decrease as a function of both temperature and trap density. In particular, the oxide-fixed traps have a severe impact on the threshold voltage.

The presented analysis could turn useful to support the design of low breakdown voltage 4H-SiC-based MOSFETs seeing that the pure experimental characterization of the device reliability is very expensive and time consuming.