1 Introduction

Filters are widely used in digital communication systems for noise canceling, channel equalization, signal separation and etc. Nowadays, the digital communication systems are the essential of all space missions, and therefore, digital filters play an important role in space systems [7]. All in outer space systems are faced with a harsh environment and are exposed to ionizing radiations that cause unwanted effects in microelectronics. Soft error, as most prominent effect, is a major concern for all digital circuit. Furthermore, the shrinking of technology exacerbates the failure probability of space systems. As technology shrinks, the probabilities of multiple bit errors are increased, as MBUs constitute over 50% of the upsets in recent technologies [14].

Unfortunately packing and shielding are ineffective in the presence of SEUs and MBUs since the high energetic particles easily are able to penetrate through the shield packages [15]. In the past decade, various SEU mitigation techniques to detect, mask, or modify the fault effect for FPGAs have been proposed. According to the design, the designers have utilized a type of redundancy in data layer, software layer, hardware layer, and over the time.

In order to mitigate the unwanted effects of soft errors and provide a reliable digital communication system, several design techniques are introduced for filters such as using Hamming codes, parity-based checksum, and reduced precision modular redundancy. In studies, the level of protection is range from detection of erroneous behavior to correction of faulty outputs.

A review of the literature on this topic shows that many of these protection mechanisms rely on redundancy approaches in the normal filter operation which impose a significant area overhead and increase delay time. A key problem with much of the literature regarding to reliable digital systems is the unwanted overhead costs. So, the aforementioned works attempt to introduce novel fault tolerant structures with lower overhead and more fault coverage capability. In addition, in literature, the straightforward Triple Modular Redundancy (TMR), in which three identical circuits with a voter are used to compute the specified function, has commonly employed as a benchmark for comparison. The overhead of the proposed schemes is compared to that of TMR.

In this paper, we aim to propose a new approach to detect unidirectional MEU fault in low pass FIR filter. Unidirectional errors are referred the faulty states that only flip ones into zeroes or only zeroes into ones, such as in asymmetric channels. We have developed a novel fault tolerant architecture for FIR filters based on all unidirectional error detecting (AUED) code. We specially have applied the Berger code encoder and checker in the conventional FIR structure. At first, we have considered the basics idea of applying AUED code in filters structure through the conventional encoder and checkers. With an approximate estimation, we infer that the overhead of conventional structures is unacceptable. Therefore, we have introduced an integrated form for the coder and decoder circuits. The introduced circuit, with a same functionality, provides much lower complexity and area overhead.

The previous studies have tended to focus on single faults rather than MBU faults, while MBUs are increasingly becoming a vital factor by technology shrinking. Few researchers have addressed the problem of MBUs in FIR filters. Furthermore, due to the fact that the conventional circuits for Berger code encoder and decoder, as a AUED code, impose an unacceptable area overhead, this approach has been neglected. However, in this paper, we have described an interesting solution to mitigate unidirectional MBU faults if FIR filters.

The rest of this paper is organized as follows. In next section, the related works in fault tolerant filters are reviewed. We have presented background information and considered the basics idea of applying AUED code over FIR filters in Sect. 3. In Sect. 4, we focus on the merging of encoders and decoders in a specific circuit. Results and discussions are provided in Sect. 5. Finally, the conclusions of this paper are summarized in Sect. 6.

2 Related Works

There is a considerable amount of literature on the soft error mitigation techniques for modern microcircuits in the radiation environment. Some of them are allocated to FIR filters, and innovative methods are considered to provide protection capability for filters.

As stated in Ref. [12] Triple Modular Redundancy (TMR) and Hamming Codes are the quite straightforward and successful methods for fault mitigation in digital filters. In TMR method, the design is triplicated and voting logic is added to mask errors. To protect FIR filters using Hamming codes an encoder and decoder have been added before and after each register in filter structure. Through the combining of the decoders, the shared decoder method as an enhanced implementation of fault tolerant filter based on Hamming codes have been investigated in Ref. [12].

Ref. [20] by adding a parity bit to each coefficients of adaptive digital filter speeds up the adaptation step (fast adaptation) in faulty condition. It is necessary to mention that adaptive filters by nature recover from soft errors on their coefficients, but an acceptable recovery time is critical for many applications. The proposed method in this research is depended on the operation condition which is generically described as “using the knowledge of the system.”

Also, the transform-domain fault tolerant adaptive filters have been proposed [18]. Another system knowledge approach has been applied to simple filter structures [23], in which one special type of FIR filter, the moving average filter, is analyzed. This filter fulfills with a shift operation and the filter needs only adders. For low and average protection requirements, just by a counter or decimated filter error detection capability has been achieved. However, for high protection cases, a two-dimensional parity method is proposed. According to this method, for each input value a ‘vertical’ parity and for each bit position on the input value a ‘vertical’ parity is computed. for normal condition, the actual and accumulated parity values are the same, however, in the presence of single faults we face with a discrepancy which provide fault detection capability. Moreover, the partial TMR has been applied over the stored values to correct the error. Also, the FIR protection using system knowledge has been compared with other soft error mitigation techniques like TMR and Hamming codes [22].

A structural dual modular redundancy (DMR), which uses two different implementations of the basic filter operating in parallel, has been proposed in Ref. [21]. Through the distinct error patterns at the filter output the faulty module is detected and error-free result is selected.

Algorithmic soft error-tolerance (ASET) technique [3] that employs uncomplicated estimator of a main DSP unit, M block, has been investigated on for frequency selective finite impulse response (FIR) filtering. This work is extended based on algorithmic noise tolerance (ANT) [2] in which a low-complexity unit, the estimator, computes an approximation for M block output. The Euclidean metric of the main and estimator and also the Hamming distance between two estimator units provide error detection capability.

The use of redundant residue number systems (RNSs) is another technique that has been explored for FIR filter protection [5, 17, 25]. Based on residue code method, the operands are divided by a given number and the computation is applied on reminders. The residue code has the same arithmetical and logical properties of operand; therefore, a low-complexity computation is exploited for the fault detection purposes. In some cases, to provide error masking capability, a redundant unit has been added in proposed structure [17].

General digital filters that are very similar with convolutional code structure have been adopted to protect from errors in Ref. [26], the parity check positions have been added in the code and a parallel parity channel is developed besides the original structure. Zhen Gao and co-workers [8, 9] have developed on a new method to protect parallel filters. Their approach is based on applying ECCs, especially Hamming codes, to the parallel filters outputs. For future works, they also recommend the use of more powerful multibit ECCs, such as Bose–Chaudhuri–Hocquenghem codes, to correct errors on MBUs in filters.

Here we have proposed a new hardening technique for FIR filters to protect against unidirectional MBUs based on the Berger Codes. Through the proposed an efficient scheme for data encoding and decoding, the area, power consumption, and error rate is significantly being reduced. The Berger code is the least redundant separable unidirectional error detecting code that provides an ability to detect all unidirectional errors in the telecommunication channels and arithmetic operations [1].

A unidirectional error is a multiple bit upset so that all errors have same type either \(0 \rightarrow 1\) or \(1 \rightarrow 0\). According to the Berger code, the binary representation of the number of 0’s or 1’s in the information part are utilized as the check part. For a data vector with the width of n, the Berger code requires \(K = \lceil \log _{2} (n+1)\rceil \) check bits \(C = ({c}_{{K}-1}, \ldots , {c}_{1}, {c}_{0})\). Berger check prediction (BCP) was used to handle arithmetic and logic operations [13]. In addition, some design methods of Berger code checkers were proposed in the literature [11, 19]. In the complicated cases that the Berger codes in the filter structure are intended to a multi-variable issue, for the estimation of faulty state aims, the state space model as illustrated in Ref. [10] can be applied. We aim to develop this coding methods over the communication digital signal processing units, especially FIR filters.

Fig. 1
figure 1

Direct form FIR digital filter structures (parallel)

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Fig. 2
figure 2

A single PE architecture for direct form FIR filter structure

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3 Proposed Scheme

A FIR filter equation is described by the following operation [16]:

$$\begin{aligned} y [n]=\sum \limits _{i=0}^{N}h[i]\cdot x[n-i] \end{aligned}$$

where x[n] is the input signal, y[n] is the output and h[n] is the impulse response of the filter. A common structure, the direct form, of n-tap FIR filter is illustrated in Fig. 1, where the input vector x[n] are shifted though the delay registers (D-element), at the same time, the corresponding coefficients h[n] are multiplied in the content of taps and finally the sum of these products yields the filter output y[n]. Because the implementation cost of multiplication operation is so large, in some cases a single processing element (PE), multiplier-accumulator was multiplexed among all of the filter taps [4]. As illustrated in Fig. 2 [24], the hardware complexity of this scheme is lower, and therefore the fault detection methods are feasible to be applied, however, the long execution time is a severe drawback.

Fig. 3
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Proposed coding scheme for single PE FIR filter

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Fig. 4
figure 4

Proposed coding scheme in general for direct form FIR digital filter

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The new proposed technique is based on the use of Berger code as an effective error detection mechanism. A Berger code version of the FIR filter is obtained by using the Berger code prediction (BCP) units along the basic FIR filters element. The predicted number of 1’s in the output of this filter by \({N}_{y}[n]\) is equal to the number of 1’s of the original filter. So, through a comparator the faulty state is detected. As illustrated in Figs. 3 and 4, besides the main adders and multipliers, we have placed the Adder and Multiplier Berger Code Predictor (ABCP) and (MBCP) units. These units, which are detailed in following, predict the Berger check bits of results. To perform this requirement, the number of 1’s in the input patters as preliminaries are needed. So, the Berger Code Counter (BCC) unit that calculates the number of 1’s has been provided in the proposed scheme. Moreover, the delay element is used over input checker bits to provide the number of 1’s for other filter taps. Also, the check bits of the impulse response h[n] have been stored as another input of BCP units. In following subsection, we have detailed the developed Berger check prediction units in the FIR filters.

3.1 BCC Unit

The Berger code counter or encoder unit calculates the sum all the ones in the input time-series x[n]. According to Berger code theory, if the information word consists of n bits, \(k = \log _2 \left( {{n}+1} \right) \) bits are required as check bits. The check bits can be extracted with a primitive scheme represented in Fig. 5. In this design, the half and semi half adder (H.A and \(\hbox {H}^{2}\hbox {A}\)) units are used. The Semi half adder unit are the same as H.A, with the exception that the Carry bit is unrequited in \(\hbox {H}^{2}\).A units. The logical details of these blocks are also illustrated in figure. According to this scheme, the number of H.A and \(\hbox {H}^{2}\).A blocks for n-bit information is equal to Eq. (1). A multi-operand carry save adder (MCSA) similar to the one shown in Ref. [13] is also used here to perform the summation.

$$\begin{aligned} \sum \limits _{i=0}^{m}\left( 2^{i}.(i+1)\right) +(2^{m}-n)(k+1),\qquad m=\log _{2}\lfloor {n}\rfloor \end{aligned}$$
(1)
Fig. 5
figure 5

A primitive scheme for Berger code counter

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3.2 Adders Berger Code Predictor (ABCP) Unit

The ABCP unit, based on the theorem that is detailed in the following, predicts the Berger check bits over adder results. Consider the addition of two n-bit numbers, \(A[n] = ({a}_{n}, {a}_{{n}-1}, \ldots ,{a}_{2}, {a}_{1})\) and \({B}[{n}] = ({b}_{m},\hbox { b}_{{m}-1},\ldots , {b}_{2}\), \({b}_{1})\) are the input patterns of an adder, also let N[A] and N[B] denote the number of 1’s in the input patterns, respectively. The decimal representation for i-th bits in adder could be characterized as:

$$\begin{aligned} a_i +b_i +c_{i-1} =s_i +2c_i \end{aligned}$$
(2)

\({s}_{i}\), \({c}_{i}\) and \({c}_{{i}-1}\) indicate the adder result and input/output carry bits for the i-th adder block, respectively. The bit counting over an input pattern is corresponding to adding up the bits in decimal format. So, we are able to develop following equation to find the Berger check bits.

$$\begin{aligned} N\left[ A \right] +N\left[ B \right]= & {} \sum _n {a_i } {+}\sum _n {b_i } =\sum _n {\left[ {a_i +b_i } \right] }\nonumber \\= & {} \sum _n {\left[ {(a_i +b_i )+\overbrace{c_{i-1} -c_{i-1} }^{=0}} \right] } =\sum _n {\left[ {(a_i +b_i +c_{i-1} )-c_{i-1} } \right] } \nonumber \\= & {} \sum _n {\left[ {\overbrace{a_i +b_i +c_{i-1} }^{Eq.\,2}-c_{i-1} } \right] } =\sum _n {\left[ {(2c_i +s_i )-c_{i-1} } \right] } \nonumber \\= & {} \sum _n {\left[ {s_i +(2c_i -c_{i-1} )} \right] =} \sum _n {s_i } \hbox {+}\sum _n {(2c_i -c_{i-1} } )\nonumber \\= & {} N\left[ S \right] +N\left[ C \right] \end{aligned}$$
(3)

In which, the number of 1’s in an adder result, \({N}[S] = \{{s}_{n}, {s}_{{n}-1},\ldots ,{s}_{2}, {s}_{1}\}\), could be predicted based on the Berger check bits of the inputs and carry chain, while the input carry \({c}_{0}\) is equal to 0 for all adders and \({c}_{n}\) is the output carry, we define the number of 1’s in the carry chain as:

$$\begin{aligned} N[C]= & {} \sum _{n} (2\hbox {c}_{\mathrm{i}}-{c}_{i-1})=2{c}_{n} +{c}_{n-1} +{c}_{n-2} +\cdots +{c}_{2} +{c}_1 -{c}_0 \\= & {} \left\{ 2{c}_{n} ,{c}_{n-1} ,{c}_{n-2} ,\ldots ,{c}_2 ,{c}_1 \right\} . \end{aligned}$$

Figure 6 represents a primitive scheme to realize the adder Berger predictor unit. As illustrated in figure, this unit requires two k-bit adder/subtracter and moreover an BCC unit to compute Berger check bits for carry chain. Also, the adder/subtracter are reduced in order from n to log \([n+1]\), however the area overhead of BCC unit causes that this scheme imperfect.

Fig. 6
figure 6

A primitive scheme for ABCP unit

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3.3 Multiplier Berger Code Predictor (MBCP) Unit

The multiplier architecture is constructed with adders, and therefore the aforementioned Berger checker scheme for adders can be developed over multiplier units which are used in FIR filters. Multipliers involve computing a set of partial products, \(\mathrm{PP}_{i}= A \times b_{i}\), and then summing the partial products together. The Berger check bit for partial products, \(N[\mathrm{PP}]\), simply can be calculated as Eq. (4). This Equation also represents the summation of check bits of PPs.

$$\begin{aligned} N[\mathrm{PP}_{i}]=\left\{ \begin{array}{lll} 0 &{} &{} \forall b_{i}=0\\ N[A]&{} &{}\forall b_{i}=1\\ \end{array}\right. {\Rightarrow } \sum \limits _{n}N[\mathrm{PP}_{i}]=N[A]\times N[B] \end{aligned}$$
(4)

Subsequently, the partial produces are added up to produce the final product result. Similarly, to previous subsection, the Berger check bit can be predicted for each stage based on the inputs and carry chain check bits. The check bits are added/subtracted to create the product result Berger bits. For A[n] and B[n], suppose the adder result and carry chain of the i-th stage are denoted by \(S_i[n]\) and \(C_{i}[n]\), respectively. The product result check bits, N[P], can be summarized as Eq. (5).

$$\begin{aligned} N[S_{i}]= & {} N[\mathrm{PP}_{i-1}]+N[S_{i-1}]-N[C_{i}]\nonumber \\ N[P]= & {} \sum _{n}N[C_{i}]+\sum _{n}N[\mathrm{PP}_{i}]=N[A]\times N[B]-\sum _{n}N[C_{i}] \end{aligned}$$
(5)

Similarly, to ABCP unit, the MBCP unit is constructed with size reduced k-bit adders. A primitive scheme to implement MBCP unit is illustrated in Fig. 7. In comparison with basic adders in multiplier architecture, the size of the Berger predictor adders is perfect. However, the overall area overhead which imposed by BCC units aggravates the outcome. In following section, to achieve a reasonable area overhead, we provide a specific method to eliminate primitive schemes of Berger checkers.

Fig. 7
figure 7

Multiplier architecture (right) and a primitive scheme for MBCP unit

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4 Integration of Berger Code Checkers

Although the proposed scheme is practical and effective for fault detect purposes, it is imperfect due to the fact that the BCC unit imposes an unacceptable area overhead. To solve this issue, we have developed a novel scheme based on the programmable weight threshold circuit (PWTC). The PWTC circuit, initially introduced in Ref. [11], consists of a specific arrangement of CMOS transistors that the operation of the circuit depends on the value of the input (Fig. 8). The aspect ratio W/L of transistors are designed so that the pattern inequity provides the inverter threshold voltage. More details can be found in Ref. [11]. In this paper, we have modified this circuit so that it be feasible for large Berger code checker. In the proposed scheme, integrated Berger code checker unit (IBCC) unit illustrated in Fig. 9, the complicated aspect ratio calculations are resolved. Unlike the PWTC we have utilized two programmable threshold circuits (PTCs), in which the aspect ratio of all transistors is the same. Two latched comparators along with an XOR gate subsequently are placed in the proposed scheme to detect data inequality. The threshold circuit is arranged in complementary form, so that in one’s input pattern \(Z[n] = \{\zeta _{1}, \zeta _{2},\ldots , \zeta _{n}\}\) feeds PMOS transistors and in the other one it is connected to NMOS transistors. All NMOS and PMOS transistors are supposed that have the same sizes \(W_\mathrm{nm} /L_\mathrm{nm}\) and \(W_\mathrm{pm} /L_\mathrm{pm}\).

Fig. 8
figure 8

Programmable weight threshold circuit [11]

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Fig. 9
figure 9

Integrated Berger code checker unit

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Fig. 10
figure 10

Programmable weight threshold circuit

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As we illustrated in previous section, in arithmetic operations like addition or multiplication, the Berger code aims to detect the difference in the number of 1’s in the two data patterns. We show that the proposed IBCC unit is able to satisfy this requirement. In PTCs, when \(\zeta _{\mathrm{i}}\) or \(\eta _{\mathrm{i}}\) is high and equal to \(V_{\mathrm{dd}}\), the NMOS transistor is on, while the PMOS is off. This yields the equivalent circuit that are figured in Fig. 10. When a transistor is ’on’ it is equal to a resistor that is indicated by \(R_{n}\) ad \(R_{p}\). The programmable threshold circuits are driven by \(V_\mathrm{dd}\) through the \(R_{p}\) resistors. The voltage value of PTC unit, \({V}_{\mathrm{TH}}\), can be found by superposition as the super-imposing of the effects from each of the voltage sources. Equations (6) and (7) represent the total \(V_{\mathrm{TH}}\) for each top and bottom PTCs, respectively. If we suppose \(R_{n}\approx R_{p}\), the differential voltage that is applied on comparators can be formulated as Eq. (8). As expected, when number of \(1^{{\prime }}\hbox {s}\) in data patterns are the same, \(N(\mathrm{Z}) = N (\mathrm{H})\), the applied voltage is equal to 0. An inequality, considered as a faulty state, imposes a differential voltage that is used to detect fault.

$$\begin{aligned} V_\mathrm{TH1}= & {} \frac{N(H)\cdot R_{{T}_{1}}}{R_{{T}_{1}}+R_{p}}, \quad R_{{T}_{1}}=\left( \frac{R_{n}}{{N(Z)}} || \frac{R_{p}}{N(H)-1}\right) \end{aligned}$$
(6)
$$\begin{aligned} V_\mathrm{TH2}= & {} \frac{N(H)\cdot R_{{T}_{2}}}{R_{{T}_{2}}+R_{p}}, \quad R_{{T}_{2}}=\left( \frac{R_{n}}{{N(Z)}} || \frac{R_{p}}{N(Z)-1}\right) \end{aligned}$$
(7)
$$\begin{aligned} V_\mathrm{TH1}-V_\mathrm{TH2}= & {} \frac{2N(H)}{N(H)+N(Z)}-1 \end{aligned}$$
(8)

If the number of imbalanced bits, the faulty bits, is denoted by m, the differential voltage verses the number of 1’s in information pattern, N[H], can be depicted as Fig. 11. As evident from this figure, the larger the ratio m / N[H], the better differential voltage is provided. While the number of engaged data bits, N[H], are increased, the differential voltage is dropped, for instance \(N[H] = 1000\) in millivolt order. Therefore, more sensitive comparator is required. Also the comparators can easily have designed to support microvolt orders, they may demand more challenges in area and power aspects. To resolve this requirement, we provide an independent comparator set for each array of engaged patterns. The data pattern in FIR filter taps, as illustrated in following, could be handled separately. Therefore, the conventional comparators can be applied in the fault tolerant scheme with no trouble. As mentioned, a single tap of filter just consists of one processing element (PE), the multiplication and accumulation, which the multiplier results serve as the adder input. If we suppose the Berger checker are merged for the i-th tap, the multiplier results check bits can be eliminated by the integration of Eqs. (3) and (5) and we have:

$$\begin{aligned} N[H_{i}]\times N[X_{i}]+N[S_{i-1}]=N[S_{i}]+N[C^{A}_{i}]+\sum _{n}N[C^{M}_{i}] \end{aligned}$$
(9)
Fig. 11
figure 11

Differential voltage versus number of 1’s \(\{V_\mathrm{dd} = 3.3v, R_{n}\,\approx \,R_{p}\}\)

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Fig. 12
figure 12

Single tap integrated Berger code predictor (ST-IBCP)

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in which \(H_i\) and \(X_i\) represents the number of 1’s in the impulse response, h[i], in the input pattern, \(x[n-i]\), respectively. Also, \(S_i\), \(C^{A}_{i}\) and \(C^{M}_{i}\) denote the Berger check bit in the adder result, adder’s carry chain and multiplier carry chains correspondingly. A single tap integrated Berger code predictor (ST-IBCP) unit, according to Eq. (9), is illustrated in Fig. 12. In this figure, each PE requires an IBCP unit so that the Z and H length is equal to \(n^2+2n+1\). If ST-IBCP units are combined and a multi tap integrated Berger code predictor (MT-IBCP) is used, for a data-path quantization of n bits, when T taps are merged in a MT-IBCP unit, the equivalent N[H] is calculated as:

$$\begin{aligned} \left( n^{2}+2n+1\right) \,\times \,T+2n \end{aligned}$$
(10)

Figure 13 illustrates fault detection methodology based on integrated Berger predictors. This scheme concludes ST and MT-IBCP units, which their error signals are evaluated by an OR gate. Utilizing the ST or MT IBCPs and the number of merged taps depends on the comparator resolution. Also, it is better to mention that the W / L of all transistors in IBCP unit are the same, however, if the number of 1’s in information are applied to threshold circuit instead of raw data, the W / L ratio are arranged as \({W/L}, {2W/L}, {4W/L},\ldots , 2^{k}{W/L}\).

Fig. 13
figure 13

Proposed integrated Berger coding scheme for direct form FIR digital filter

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Fig. 14
figure 14

Unidirectional MBU faults masking scheme based on Berger Code

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5 Evaluation

To evaluate the effectiveness of the proposed scheme, a number of cases are used. The quantized input data and coefficients are selected similar with previous works to compare results. Moreover, Triple Modular Redundancy (TMR), triplicates the design and adds voting logic to mask errors, is a classical fault tolerant solution that is used as the performance criterion for novel structures and the proposed methods are commonly compared with TMR. This method is able to mask single faults, so to provide an equivalent capability in proposed scheme, we have duplicated the original plan and added BC MBU detector and a multiplexer as indicated in Fig. 14. In Fig. 15, we developed the proposed scheme so that it provides 5-NMR ability in the fault mitigation. With an approximately similar fault mitigation level, the proposed technique is compared with conventional approaches and other literature. As detailed in Tables 1, 2 and 3, the results confirm that the proposed scheme can reduce the implementation cost significantly compared with the TMR. Furthermore, these results show that the IBCP-based FIR filters area overhead correlate fairly well with novel methods of other literature. However, the proposed approach not only identifies the SEU faults, but also it is able to detect all unidirectional MBUs.

Fig. 15
figure 15

MUMBU faults masking scheme based on Berger code

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Table 1 Resource comparison for 11-orders FIR filter
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Table 2 Resource comparison for 16-orders FIR filter
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Table 3 Resource improvement percentage for 16-orders FIR filter
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Although, we have focused on analyzing the effects of SEUs and MBUs to assess the effectiveness of the scheme to detect errors. The fault injection experiments have been performed and the errors have been randomly inserted in the coefficients, inputs patterns and D registers of the filters. In all cases, single errors and unidirectional MBUs were detected and are masked. According to the filter size, a number of errors on inputs and for filter coefficients were inserted in the fault simulation tool. This confirms the effectiveness of the scheme to detect and managing all single errors and multi-unidirectional errors in input patterns and coefficients.

6 Conclusion

A new method to implement fault tolerant FIR filters against single and unidirectional MBUs faults has been presented. The proposed scheme exploits the Berger code to implement an effective error detection mechanism. In comparison with previous fault tolerant filters that usually only single faults are detected and masked, in the proposed schemes not only single faults are covered but also, due to the Berger codes inherent specification, all unidirectional are handled. While the implementation results show that the Berger-based schemes impose the same area overhead.