Abstract
In this paper, a low power digital baseband to be used together with impulse-radio ultra wideband radio frequency front-end has been presented. It can provide received pulse synchronization required for burst mode and low power operation. It also overcomes clock drift issue between different transceivers. The clock and data recovery is implemented fully in digital domain without the need of conventional phase-locked loop, delay locked loop or analog-to-digital converter. The chip is designed using 0.18 μm CMOS technology. It consumes 5 mW and can recover data up to 20 Mbps.
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Abbreviations
- ADC:
-
Analog-to-digital converter
- BER:
-
Bit error rate
- CDR:
-
Carrier data recovery
- DLL:
-
Delay-locked loop
- FSM:
-
Finite state machine
- HDL:
-
Hardware description language
- IR:
-
Impulse radio
- LFSR:
-
Linear feedback shift register
- LNA:
-
Low noise amplifier
- MAC:
-
Medium access control
- MCU:
-
Micro-controller unit
- NRZ:
-
Non-return-to-zero
- OOK:
-
On-off keying
- PLL:
-
Phase-locked loop
- PN:
-
Pseudorandom number
- RF:
-
Radio frequency
- RX:
-
Receiver
- RZ:
-
Return-to-zero
- SPI:
-
Serial peripheral interface
- TX:
-
Transmitter
- UWB:
-
Ultra wideband
- VCO:
-
Voltage controlled oscillator
- WPAN:
-
Wireless personal area network
- WSN:
-
Wireless sensor network
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Toh, W.D., Zheng, Y. & Heng, CH. Low Power Digital Baseband for Impulse Radio Ultra-Wideband Transceiver. Circuits Syst Signal Process 31, 223–235 (2012). https://doi.org/10.1007/s00034-010-9249-6
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DOI: https://doi.org/10.1007/s00034-010-9249-6