Optical Quadruple Toffoli and Fredkin Gate Using SLM and Savart Plate

Abstract

Reversible computing not only reflects a fundamental law of physics, but also offers potential to achieve zero dissipation by preventing entropy loss during computation. With the demand of time, reversible logic is becoming more and more prominent to deal with modern technology. In optical computation the multi-valued logic system is the most important area where trinary and quadruple valued logic systems are demanding their uniqueness in handling big data. In this paper we have proposed the optical quadruple Toffoli and Fredkin gate using Spatial Light Modulator (SLM) and Savart Plate for realization. SLM and Savart Plate can play a significant role in the field of ultra fast optical signal processing.

1 Introduction

In recent years, the multi-valued logic (MVL) system is becoming highly praised by the scientific community for its’ inherent property of handling huge volume of data. The several inherent potential opportunities of MVL circuits may be explored further in the improvement of present VLSI circuit designs. V. Patel and K.S. Gurumurthy demonstrated the arithmetic operations like addition, subtraction and multiplications in modulo-4 arithmetic in Galois field using MVL [1]. Quaternary to binary and binary to quaternary converters [2] are also designed. The two input logic operations, half-adder, full-adder, full sub-tractor, one-bit data comparator, etc. are can be implemented optically using this architecture.

With the demand of tremendous operational speed and data processing, computing field is evolved with many new ideas. These include optical processor for switches and the logical development of MVL from binary. The parallel operation is advantageous for optical processor. MVL can also be implemented in optical system using the polarization states of light along with it’s presence or absence [3]. The signed digit number system was introduced by the pioneering works of Avizienis [4]. The modified signed digit [5,6,7] or modified trinary [8] system also suggests the carry free operation. However, Lukasiewicz [9] initiated the use of ternary logic based on three states. The modified trinary system to a quadruple-valued logic system using SLM and Savart Plate is already implemented [10, 11].

In many applications for lossless data processing the design of reversible logic is highly demanding [12, 13]. Optical and quantum computing is revolutionary computing paradigms with the help of Conservative and reversible logic gates. With this aim, we have presented optical Quadruple Toffoli Gate and optical Quadruple Fredkin Gate using SLM and Savart Plate in this paper. The simulation results confirm the described method.

The proposed paper is arranged as follows: The quadruple valued logic systems are reported in Sect. 2. Section 3 is for representation of Truth Tables in Di-bit Format. Section 4 presents the working principle of basic building block using SLM and Savart Plate. The working principle and design of Quadruple Toffoli and Fredkin Gate are presented in Sects. 5 and 6. Logical simulation results are shown in Sect. 7 and concluding remarks are given in Sect. 8.

2 Quadruple Valued Logic System

The quadruple valued logic system consists of four states. The states may be classified as the true, partly true, partly false and the false. Here we are considering four states explicitly as {0, 1, 2, 3} and their corresponding di-bit representations as {00, 01, 10, 11}. The logical states, their representations and corresponding di-bit representations and the state of polarization are given in Table 1.

Table 1. Quadruple valued logic system

3 Representation of Truth Tables in Di-bit Format

In the present system the normal logical gates e.g., OR, AND, NOT, XOR, NAND, NOR and XNOR are represented in di-bit format and the corresponding truth table is given in Table 2.

Table 2. Truth tables for (a) OR, (b) AND, (c) NOT (d) XOR, (e) NAND, (f) NOR and (g) XNOR Gates

4 The Basic Building Block

Figure 1 represents the basic building block to implement the logical operations in quadruple valued logic system and Fig. 2 represents the operation in flow chart format. The Light that is coming out from a laser source L is incident on the polarizer P. After passing through the polarizer P it is incident on the Savart Plate S₁ as shown in Figs. 1 and 2. S₁ is used to split the light into two orthogonal components (horizontal polarization and vertical polarization). The two components of input beam are controlled by the electrically addressable negative SLMs, P₁ and P₂. The negative SLM is transparent when no electric voltage is applied on it and it becomes opaque when an electric voltage is applied on it. The property of positive SLM is just opposite. The inputs are considered as in the form of di-bit format. The Savart Plate S₂ combines the outputs from SLMs and provides the final output.

Fig. 1.

The basic building block

Fig. 2.

The flow chart of basic building block

5 Quadruple Toffoli Gate: Principle and Design

Toffoli Gate is a universal reversible logic gate [14, 15]. A, B, C and X, Y, Z are the three inputs and outputs, respectively. The Boolean expression of the Toffoli Gate is given below.

$$ \begin{array}{*{20}l} {{\text{X}} = {\text{A}}} \hfill \\ {{\text{Y}} = {\text{B}}} \hfill \\ {{\text{Z}}\text{ = }{\text{A}} \cdot {\text{B}} \oplus {\text{C}}} \hfill \\ \end{array} $$

(1)

Table 3 represents the truth table of Toffoli Gate.

Table 3. Binary truth table of Toffoli Gate.

Here we are going to discuss about Quadruple Toffoli Gate with di-bit representation which is in Table 4.

Table 4. Truth table of Quadruple Toffoli Gate

The SLM and Savart Plate based circuit for Quadruple Toffoli Gate is given in Fig. 3.

Fig. 3.

SLM and Savart Plate based Quadruple Toffoli Gate

The polarized parallel beam coming from the Laser source L through polarizer P is incident on the beam splitter BS₇. The beam is splitted into two directions by BS₇ as shown Fig. 3. From the Fig. 3 it can also be seen that the output of S₁₆ gives the output X, the output of S₂₁ provides the output Y and the output of S₇ and S₁₄ combines by the beam splitter BS₅ and produce the another output Z. The functions of SLM and Savart Plate are already described in Sect. 4. From Table 4 it can be seen that total 64 cases are considered. Some cases are discussed as follows:

• When A = 0 (A₁ = 0, A₂ = 0), B = 0 (B₁ = 0, B₂ = 0) and C = 0 (C₁ = 0, C₂ = 0) then no light is present at the output of S₁₆ and S_21, hence X = 0 (X₁ = 0, X₂ = 0) and Y = 0 (Y₁ = 0, Y₂ = 0). As the input C = 0 so there will be no light at the output of S₇ and S₁₄, so the output, Z = 0 (Z₁ = 0, Z₂ = 0).

• As A = 0 (A₁ = 0, A₂ = 0), B = 3 (B₁ = 1, B₂ = 1) and C = 0 (C₁ = 0, C₂ = 0) then no light is present at the output of S₁₆, hence X = 0 (X₁ = 0, X₂ = 0). The output of S₂₁ consists of both vertical and horizontal polarized light, hence Y = 3 (Y₁ = 1, Y₂ = 1). As AB = 0 (A₁B₁ = 0, A₂B₂ = 0) and C = 0 so there will be no light at the output of S₇ and S₁₄ i.e. Z = 0 (Z₁ = 0, Z₂ = 0).

• When A = 1 (A₁ = 0, A₂ = 1), B = 1 (B₁ = 0, B₂ = 1) and C = 1 (C₁ = 0, C₂ = 1) then X = 1 (X₁ = 0, X₂ = 1) as X = A. The output of S₂₁ consists of only vertically polarized light, hence Y = 1 (Y₁ = 0, Y₂ = 1). As AB = 1 (A₁B₁ = 0, A₂B₂ = 1) and C = 1 so there will be no light at the output of S₇ and S₁₄ i.e. Z = 0 (Z₁ = 0, Z₂ = 0).

• When A = 1 (A₁ = 0, A₂ = 1), B = 2 (B₁ = 1, B₂ = 0) and C = 1 (C₁ = 0, C₂ = 1) then X = 1 (X₁ = 0, X₂ = 1) as X = A. Only horizontally polarized light is present at the output of S₂₁ i.e. Y = 2 (Y₁ = 1, Y₂ = 0). As AB = 0 (A₁B₁ = 0, A₂B₂ = 0) and C = 1 so there is no light at the output of S₇ and the output of S₁₄ consists of vertically polarized light i.e. Z = 1 (Z₁ = 0, Z₂ = 1).

• When A = 2 (A₁ = 1, A₂ = 0), B = 2 (B₁ = 1, B₂ = 0) and C = 2 (C₁ = 1, C₂ = 0) then X = 2 (X₁ = 1, X₂ = 0) as X = A. Only horizontally polarized light is present at the output of S₂₁ i.e. Y = 2 (Y₁ = 1, Y₂ = 0). As AB = 2 (A₁B₁ = 1, A₂B₂ = 0) and C = 2 so there is no light at the output of S₇ and S₁₄. The output is Z = 0 (Z₁ = 0, Z₂ = 0).

• When A = 2 (A₁ = 1, A₂ = 0), B = 3 (B₁ = 1, B₂ = 1) and C = 2 (C₁ = 1, C₂ = 0) then X = 2 (X₁ = 1, X₂ = 0) as X = A. The vertical and horizontal polarized lights are present at the output of S₂₁, hence Y = 3 (Y₁ = 1, Y₂ = 1). As AB = 2 (A₁B₁ = 1, A₂B₂ = 0) and C = 2 so there is no light at the output of S₇ and S₁₄. The output is Z = 0 (Z₁ = 0, Z₂ = 0).

• When A = 2 (A₁ = 1, A₂ = 0), B = 3 (B₁ = 1, B₂ = 1) and C = 3 (C₁ = 1, C₂ = 1) then X = 2 (X₁ = 1, X₂ = 0) as X = A. The output of S₂₁ consists of both vertical and horizontal polarized light, hence Y = 3 (Y₁ = 1, Y₂ = 1). As AB = 2 (A₁B₁ = 1, A₂B₂ = 0) and C = 3 so there is no light at the output of S₇ and the output of S₁₄ consists of vertically polarized light. The output consists of only vertically polarized light i.e. Z = 1 (Z₁ = 0, Z₂ = 1).

• When A = 3 (A₁ = 1, A₂ = 1), B = 0 (B₁ = 0, B₂ = 0) and C = 3 (C₁ = 1, C₂ = 1) then X = 3 (X₁ = 1, X₂ = 1) as X = A. No light is present at the output of S₂₁ i.e. Y = 0 (Y₁ = 0, Y₂ = 0). As AB = 0 (A₁B₁ = 0, A₂B₂ = 0) and C = 3, the output of S₁₄ consists of both vertical and horizontal polarized light. There is no light at the output of S₇. The final output is Z = 3 (Z₁ = 1, Z₂ = 1).

• When A = 3 (A₁ = 1, A₂ = 1), B = 3 (B₁ = 1, B₂ = 1) and C = 3 (C₁ = 1, C₂ = 1) then X = 3 (X₁ = 1, X₂ = 1) as X = A. The vertical and horizontal polarized lights are present at the output of S₂₁, hence Y = 3 (Y₁ = 1, Y₂ = 1). As AB = 3 (A₁B₁ = 1, A₂B₂ = 1) and C = 3 so no light is present at the output of S₂₆ and S₃₃. No light is present at the output of Z i.e. Z = 0 (Z₁ = 0, Z₂ = 0).

In the same way the other cases can be described according to the Table 4.

6 Quadruple Fredkin Gate: Principle and Design

The Fredkin gate is a computational circuit suitable for reversible computing [14]. A, B, C and X, Y, Z are the three inputs and outputs, respectively. The Boolean expression of the Fredkin Gate is given below.

$$ \left. {\begin{array}{*{20}l} {{\text{X }}\text{ = }{\text{A}}} \hfill \\ {{\text{Y }}\text{ = }\overline{\text{A}} \cdot{\text{B }} + {\text{ A}}\cdot{\text{C}}} \hfill \\ {{\text{Z }}\text{ = } {\text{A}}\cdot{\text{B }} + \, \overline{\text{A}} \cdot{\text{C}}} \hfill \\ \end{array} \quad \quad } \right\} $$

(2)

Figure 4 represents the block diagram and Table 5 shows the truth table of Fredkin Gate.

Fig. 4.

Block diagram of Fredkin Gate

Table 5. Binary truth table of Fredkin Gate

Here we are going discuss about Quadruple Fredkin Gate and the corresponding truth table is given in Table 6.

Table 6. Truth table of Quadruple Fredkin Gate

The SLM and Savart Plate based circuit for Quadruple Fredkin Gate is given in Fig. 5. The polarized parallel beam coming from the Laser source L through polarizer P is incident on the beam splitter BS₁. The beam is splitted into two directions by BS₁ as shown Fig. 5. Two parts of light from the output of BS₁ are incident on the Savart Plate S₁ and beam splitter BS₃ respectively. The incident beam is splitted into two orthogonal components - the p-polarization (horizontal polarization) and the s-polarization (vertical polarization) by the Savart Plate S₁. The input A (combination of A₁ and A₂) is used to control the positive SLMs P₁ and P₂. The outputs form P₁ and P₂ are recombined by the Savart Plate S₂ and incident on the beam splitter BS₂. From the Fig. 5 it can also be seen that we get output X = A from the output of S₂. (A · C) is the output of S_4, which is incident on S₅. The opto-electrical converters (O/E) are used in the path of the rays to convert the light signal into electric voltage. The output of S₅ is incident on the opto-electrical converters (O/E). The output from opto-electrical converter (O/E) will act as control input terminals for P₇ and P₈. Ā is the output of S₁₂, which one after passing through S₁₃ and opto-electrical converters (O/E) will act as control input terminals for P₁₃ and P₁₄. (Ā · B) is the output of S₁₉ and it is incident on S₂₀. The SLMs P₁₁ and P₁₂ are controlled by the output of S₂₀ which is again converted into electrical signal by the use of opto-electrical converters (O/E). Finally BS₅ is used to combine the outputs of S₁₀ and S₁₅ and produce the output Y = Ā · B + A · C · (Ā · C) is the output of S₂₄ and (A · B) is the output of S₂₉. By the same procedure, finally BS₁₂ is used to combine the outputs of S₃₂ and S₃₄ and produce the output Z = A · B + Ā · C. From Table 6 it can be seen that total 64 cases are there. Some cases are explained as follows:

Fig. 5.

SLM and Savart Plate based Quadruple Fredkin Gate

• When A = 0 (A₁ = 0, A₂ = 0), B = 0 (B₁ = 0, B₂ = 0) and C = 1 (C₁ = 0, C₂ = 1) then no light at the output of S₂, hence X = 0 (X₁ = 0, X₂ = 0). There is no light at the output of S₄, S₁₉, S₁₀ and S₁₅ i.e. Y = 0 (Y₁ = 0, Y₂ = 0). As the input C = 1 so there is no light at the output of S₂₉ and S₃₄ but the outputs of S₂₄ and S₃₂ consist of vertically polarized light. The vertically polarized light is present at the output of Z i.e. Z = 1 (Z₁ = 0, Z₂ = 1).

• When A = 0 (A₁ = 0, A₂ = 0), B = 0 (B₁ = 0, B₂ = 0) and C = 2 (C₁ = 1, C₂ = 0) then X = 0 (X₁ = 0, X₂ = 0) as X = A. No light is present at the output of S₄, S₁₉, S₁₀ and S₁₅ i.e. Y = 0 (Y₁ = 0, Y₂ = 0). The output of S₂₄ and S₃₂ consist of horizontally polarized light and no light is present at the output of S₂₉ and S₃₄. Hence the output is Z = 2 (Z₁ = 1, Z₂ = 0).

• When A = 0 (A₁ = 0, A₂ = 0), B = 0 (B₁ = 0, B₂ = 0) and C = 3 (C₁ = 1, C₂ = 1) then X = 0 (X₁ = 0, X₂ = 0) as X = A. No light is present at the output of S₄, S₁₉, S₁₀ and S₁₅ i.e. Y = 0 (Y₁ = 0, Y₂ = 0). As the input C = 3 so no light is present at the output of S₂₉ and S₃₄ but both vertically and horizontally polarized lights are present at the outputs of S₂₄ and S₃₂. Hence the output is Z = 3 (Z₁ = 1, Z₂ = 1).

• When A = 0 (A₁ = 0, A₂ = 0), B = 1 (B₁ = 0, B₂ = 1) and C = 0 (C₁ = 0, C₂ = 0) then X = 0 (X₁ = 0, X₂ = 0) as X = A. No light is present at the output of S₄ and S₁₀ but vertically polarized light is present at the output of S₁₉ and S₁₅ i.e. Y = 1 (Y₁ = 0, Y₂ = 1). As the input C = 0 so no light is present at the output of S₂₄, S₂₉, S₃₂ and S₃₄, hence the output is Z = 0 (Z₁ = 0, Z₂ = 0).

• When A = 1 (A₁ = 0, A₂ = 1), B = 1 (B₁ = 0, B₂ = 1) and C = 0 (C₁ = 0, C₂ = 0) then X = 1 (X₁ = 0, X₂ = 1) as X = A. No light is present at the output of S₄, S₁₉, S₁₀ and S₁₅ i.e. Y = 0 (Y₁ = 0, Y₂ = 0). As the input C = 0 so no light is present at the output of S₂₄ and S₃₂ but only vertically polarized light is present at the output of S₂₉ and S₃₄. The output of Z consists of only vertically polarized light i.e. Z = 1 (Z₁ = 0, Z₂ = 1).

• When A = 2 (A₁ = 1, A₂ = 0), B = 2 (B₁ = 1, B₂ = 0) and C = 0 (C₁ = 0, C₂ = 0) then X = 2 (X₁ = 1, X₂ = 0) as X = A. No light is present at the output of S₄, S₁₉, S₁₀ and S₁₅ i.e. Y = 0 (Y₁ = 0, Y₂ = 0). As the input C = 0 so no light is present at the output of S₂₄ and S₃₂ but only horizontally polarized light is present the output of S₂₉ and S₃₄. The output of Z consists of only horizontally polarized light i.e. Z = 2 (Z₁ = 1, Z₂ = 0).

• When A = 3 (A₁ = 1, A₂ = 0), B = 3 (B₁ = 1, B₂ = 1) and C = 0 (C₁ = 0, C₂ = 0) then both polarized lights are present the output of S₂, hence X = 3 (X₁ = 1, X₂ = 1). No light is present at the output of S₄, S₁₉, S₁₀ and S₁₅ i.e. Y = 0 (Y₁ = 0, Y₂ = 0). As the input C = 0 so no light is present at the output of S₂₄ and S₃₂ but both polarized lights are present at the output of S₂₉ and S₃₄. The horizontally and vertically polarized light is present at the output of Z i.e. Z = 3 (Z₁ = 1, Z₂ = 1).

In the similar way the other cases can be explained according to the Table 6.

7 Performance Evaluation Through Simulation and Discussion: Toffoli Gate and Fredkin Gate

The Boolean function of Toffoli gate and Fredkin Gate are verified by the simulation results using Mathcad-7. The simulated wave forms are shown in Figs. 6 (a) and (b) of Toffili and Fredkin Gates respectively. The power of the input pulse is taken A = 2.26 dBm, B = C = 1.13 dBm.

Fig. 6.

Simulation result of (a) Toffoli Gate (b) Fredkin Gate: [x-axis: time (ps) and y-axis: power dBm)]

In Fig. 6(a) upper three set waveforms of the timing instant for the occurrence of bit patterns at 0, 5, 10, 15, 20, 25, 30, 35 ps, indicate the input bit sequences, 00001111, 00110011, 01010101 for the input variables A, B, C, respectively. Whereas, the lower three waveforms denote bit sequences 00001111, 00110011, 01010110 for the output variables X, Y, Z respectively.

Now we are going to check the reversible operation from the simulation results for time instant at 15 ps of Fig. 6(a), the output signals are Z = 1, Y = 1, X = 0. From Eq. (1), we get A = 0, B = 1 and C = 1 using these specific outputs.

In Fig. 6(b), upper three set waveforms of the timing instant for the occurrence of bit patterns at 0, 5, 10, 15, 20, 25, 30, 35 ps, indicate the input bit sequences 00001111, 00110011, 01010101 for the input variables A, B, C respectively. Similarly, the lower three waveforms denote bit sequences 00001111, 00110101, 01010011, for the output variables X, Y, Z, respectively.

Now the output signals of reversible operation from the simulation results at 10 ps of Fig. 6(b) are Z = 0, Y = 1, X = 0. From Eq. (2), we have A = 0, B = 1 and C = 0 using these specific outputs.

By the same procedure the reversibility condition can be verified for different bit patterns.

8 Conclusions and Future Work

In this paper we have proposed and described SLM and Savart Plate based reversible Quadruple Toffoli Gate and Quadruple Fredkin Gate. These have wide applications in reversible logic based digital signal processing systems and optical communication systems. The theoretical models developed and the results obtained numerically are useful to future optical reversible logic computing system in four-state implementation which is possible to handle more information at a time. Future work would concentrate realization of various Boolean expressions in the form of system implementation, arithmetic and logical operations in reversible system.