Abstract
This chapter presents detailed hardware implementation results and performance metrics for the eSTREAM candidate stream ciphers remaining in the Phase 3 hardware profile. Performance assessment has been made in accordance with the eSTREAM hardware testing framework in terms of power, area and speed. An attempt has been made to quantify the flexibility and scalability dimensions of performance. The results are presented in tabular and graphical format together with summarising the utility of the candidates against two notional applications: one for 10Mbps wireless network and a second for 100kHz RFID. Where applicable to a particular cipher, guidance on any limitations on the choice of key or IV is given. The chapter concludes with a summary of the performance of each of the candidates and some general guidance for future low resource hardware stream cipher development.
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Keywords
- Shift Register
- Advance Encryption Standard
- Initialisation Vector
- Stream Cipher
- Linear Feedback Shift Register
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
ECRYPT, Call for Stream Cipher Primitives (April 12, 2005), http://www.ecrypt.eu.org/stream/call/
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Good, T., Benaissa, M. (2008). ASIC Hardware Performance. In: Robshaw, M., Billet, O. (eds) New Stream Cipher Designs. Lecture Notes in Computer Science, vol 4986. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-68351-3_19
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DOI: https://doi.org/10.1007/978-3-540-68351-3_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-68350-6
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