Abstract
This paper proposes a set of new techniques to improve the implementation of the SHA-2 hashing algorithm. These techniques consist mostly in operation rescheduling and hardware reutilization, allowing a significant reduction of the critical path while the required area also decreases. Both SHA256 and SHA512 hash functions have been implemented and tested in the VIRTEX II Pro prototyping technology. Experimental results suggest improvements to related SHA256 art above 50% when compared with commercial cores and 100% to academia art, and above 70% for the SHA512 hash function. The resulting cores are capable of achieving the same throughput as the fastest unrolled architectures with 25% less area occupation than the smallest proposed architectures. The proposed cores achieve a throughput of 1.4 Gbit/s and 1.8 Gbit/s with a slice requirement of 755 and 1667 for SHA256 and SHA512 respectively, on a XC2VP30-7 FPGA.
Chapter PDF
Similar content being viewed by others
References
Dadda, L., Macchetti, M., Owen, J.: The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512). In: DATE, pp. 70–75. IEEE Computer Society, Los Alamitos (2004)
Macchetti, M., Dadda, L.: Quasi-pipelined hash circuits. In: IEEE Symposium on Computer Arithmetic, pp. 222–229. IEEE Computer Society, Los Alamitos (2005)
Dadda, L., Macchetti, M., Owen, J.: An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512). In: Garrett, D., Lach, J., Zukowski, C.A. (eds.) ACM Great Lakes Symposium on VLSI, pp. 421–425. ACM, New York (2004)
Grembowski, T., Lien, R., Gaj, K., Nguyen, N., Bellows, P., Flidr, J., Lehman, T., Schott, B.: Comparative analysis of the hardware implementations of hash functions SHA-1 and SHA-512. In: Chan, A.H., Gligor, V.D. (eds.) ISC 2002. LNCS, vol. 2433, pp. 75–89. Springer, Heidelberg (2002)
McLoone, M., McCanny, J.V.: Efficient single-chip implementation of SHA-384 & SHA-512. In: proc. of IEEE International Conference on Field-Programmable Technology, pp. 311–314 (2002)
Sklavos, N., Koufopavlou, O.: Implementation of the SHA-2 hash family standard using FPGAs. The Journal of Supercomputing 31, 227–248 (2005)
Ting, K.K., Yuen, S.C.L., Lee, K.-H., Leong, P.H.W.: An FPGA Based SHA-256 Processor. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 577–585. Springer, Heidelberg (2002)
McEvoy, R.P., Crowe, F.M., Murphy, C.C., Marnane, W.P.: Optimisation of the SHA-2 family of hash functions on FPGAs. In: IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI 2006), pp. 317–322 (2006)
Michail, H.E., Kakarountas, A.P., Selimis, G.N., Goutis, C.E.: Optimizing SHA-1 hash function for high throughput with a partial unrolling study. In: Paliouras, V., Vounckx, J., Verkest, D. (eds.) PATMOS 2005. LNCS, vol. 3728, pp. 591–600. Springer, Heidelberg (2005)
NIST: Announcing the standard for secure hash standard, FIPS 180-1. Technical report, National Institute of Standards and Technology (1995)
NIST: The keyed-hash message authentication code (HMAC), FIPS 198. Technical report, National Institute of Standards and Technology (2002)
Omitted due to the blind review submission
Vassiliadis, S., Wong, S., Gaydadjiev, G.N., Bertels, K., Kuzmanov, G.K., Panainte, E.M.: The Molen polymorphic processor. IEEE Transactions on Computers, 1363–1375 (2004)
Sklavos, N., Koufopavlou, O.: On the hardware implementation of the SHA-2 (256,384,512) hash functions. In: proc. of IEEE International symposium on Circuits and systems (ISCAS 2003), pp. 25–28 (2003)
HELION: Fast SHA-2 (256) hash core for xilinx FPGA (2005), http://www.heliontech.com/
Lien, R., Grembowski, T., Gaj, K.: A 1 Gbit/s partially unrolled architecture of hash functions SHA-1 and SHA-512. In: Okamoto, T. (ed.) CT-RSA 2004. LNCS, vol. 2964, pp. 324–338. Springer, Heidelberg (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Chaves, R., Kuzmanov, G., Sousa, L., Vassiliadis, S. (2006). Improving SHA-2 Hardware Implementations. In: Goubin, L., Matsui, M. (eds) Cryptographic Hardware and Embedded Systems - CHES 2006. CHES 2006. Lecture Notes in Computer Science, vol 4249. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11894063_24
Download citation
DOI: https://doi.org/10.1007/11894063_24
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-46559-1
Online ISBN: 978-3-540-46561-4
eBook Packages: Computer ScienceComputer Science (R0)