Keywords

1 Introduction

The continuously rising grid-integrated distributed power generation systems (DPGS) [1] into the utility grid needs advanced controllers for appropriate operation achieved by the power electronic-based grid side converters (GSC) [2,3,4,5,6,7,8]. Therefore, correct designing of the GSC-based controlling system performs an important task for suitable operation during both abnormal and normal grid operating conditions. So, the synchronization method must perform the role of extricating the utility voltage variables information accurately in terms of phase angle, amplitude, and frequency. Generally, phase-locked loop (PLL)-based synchronization methods are utilized for achievement of proper monitoring and control of the utility voltage variables [9,10,11,12,13,14,15]. The extracted utility grid voltage variables information leads to the desirable control of the interfaced GSC. Therefore, the accuracy and robustness of the PLL perform a fundamental job in total control operation for the grid-integrated DPGS. The PLL’s performance accuracy becomes serious under adverse grid situations like during the utility voltage swells and sags, harmonics, interharmonics, unbalanced and balanced main grid faults, DC offsets, phase jumps, and frequency variations [2, 16,17,18,19,20,21]. Hence, the PLL structure must be robust enough to handle the adverse grid operating situations with an improved performance, faster dynamic response along with lower computational complexity for an efficient operation and application.

The present work compares and analyzes five numbers of recently developed advanced PLLs based on their performing abilities, design complexity, and dynamic response. The discussed PLLs are decoupled dual synchronous reference frame PLL (DDSRF PLL) [22,23,24], multi-sequence harmonic decoupling cell PLL (MSHDC PLL) [25, 26], decoupling network in αβ frame PLL (DNαβ PLL) [2, 9, 26], harmonic interharmonic DC offset PLL (HIHDO PLL) [9, 16], and the less complex disturbance rejection PLL (LCDR PLL) [26, 27]. This review paper aims to provide the detailed idea about the PLLs with their schematic diagrams, detailed description, operating principle, the performance abilities along with their respective merits and demerits. The reason behind selection of these five PLLs is that apart from the DDSRF PLL, rest are the most recently developed accurate synchronization methods for grid-integrated DPGS under abnormal and distorted grid operating conditions. The DDSRF PLL is the commonly used and referred PLL in grid-integrated DPGS under normal and faulty grid conditions. The literature studies on review of different conventional and also advanced PLLs can be found in [9, 28,29,30,31]. This paper provides a comparison among these advanced PLLs which are the extended and advanced versions of the DDSRF PLL providing an appropriate selection guide to choose the suitable PLL according to the application considering any specific grid operating conditions. The detailed discussion on each individual PLL is showcased in Sect. 2, whereas Sect. 3 presents the comparative study of the PLLs based on their performance abilities followed by the conclusion in Sect. 4.

2 Detailed Review of the Recently Developed Advanced Three-Phase PLLs

The classical αβ PLL [32,33,34] and the SRF or dq PLL [9, 35, 36] operate efficiently in balanced operating grid situations whereas estimate inaccurately under distorted grid conditions like faults, interharmonics, DC offsets, and harmonics. A DDSRF PLL is better than SRF PLL [37] that is an equivalent of DSOGI PLL [38,39,40] operates properly in unbalanced grid faults leading to accurate extraction of phase angle by rejecting the double-frequency oscillations impact. Still, the DDSRF PLL leads to higher frequency overshoots which makes it prone to the effects of interharmonics, harmonics, and the DC offsets. The hybrid dαβ PLL [41] decreases the increased overshoot effect in DDSRF PLL though having other similar problems like the DDSRF PLL.

A new multi-sequence harmonic decoupling cell PLL (MSHDC PLL) [25] mitigates the selective lower order harmonics with an improved dynamic response with a higher computational complexity because of larger numbers of the dq transformation modules. To overcome this drawback, the DNαβ PLL [2] has an equal compensation same as the MSHDC PLL but with lower computational complexity. The DNαβ PLL still has higher complexity. The foremost disadvantages of the MSHDC PLL and DNαβ PLL are that in their cases, previous knowledge about the harmonics and interharmonics aimed for compensation is required. Both of these PLLs are also sensitive to the DC offset and interharmonics. So, two recently developed advanced PLLs based on DDSRF PLL concept used for mitigation of harmonics along with interharmonics and also DC offset have been proposed as HIHDO PLL [16] and LCDR PLL [27].

2.1 Decoupled Dual SRF PLL (DDSRF PLL)

A DDSRF PLL [22] uses two numbers of SRF modules rotating at dissimilar angular speeds which are +ω speed (fundamental positive sequence SRF module) and –ω speed (negative sequence SRF module). The DDSRF PLL is represented in Fig. 1 where each SRF module transforms the utility grid voltage \(\nu_{\alpha \beta }\) to the \(\nu_{dq}^{ + 1}\) positive sequence and negative sequence \(\nu_{dq}^{ - 1}\). In the SRF transformations, input signal having more than one fundamental frequency element is converted with a definite angular speed resulting as an undesirable oscillation in the converted components as an impact of residual frequency components [9]. So, after the transformation effect on each SRFs, −2ω and +2ω oscillations are detected in the \(\nu_{dq}^{ + 1}\) and \(\nu_{dq}^{ - 1}\) grid vectors. The −2ω fluctuation of \(\nu_{dq}^{ + 1}\) is an impact of negative sequence component with +ω speed transformation and vice versa that is represented by the following equations:

$$\nu_{dq}^{ + 1} = \left[ {T_{dq}^{ + 1} } \right]\nu_{\alpha \beta } = V^+ \left[ {\begin{array}{*{20}c} 1 \\ 0 \\ \end{array} } \right] + V^- \left[ {\begin{array}{*{20}c} {\cos \left( { - 2\omega t} \right)} \\ {\sin \left( { - 2\omega t} \right)} \\ \end{array} } \right]$$
(1)
$$\nu_{dq}^{ - 1} = \left[ {T_{dq}^{ - 1} } \right]\nu_{\alpha \beta } = V^- \left[ {\begin{array}{*{20}c} 1 \\ 0 \\ \end{array} } \right] + V^+ \left[ {\begin{array}{*{20}c} {\cos \left( {2\omega t} \right)} \\ {\sin \left( {2\omega t} \right)} \\ \end{array} } \right]$$
(2)
$$\left[ {T_{dq}^n } \right] = \left[ {\begin{array}{*{20}l} {{\text{cos}}\left( {n\theta } \right)} \hfill & {{\text{sin}}\left( {n\theta } \right)} \hfill \\ { - {\text{sin}}\left( {n\theta } \right)} \hfill & {{\text{cos}}\left( {n\theta } \right)} \hfill \\ \end{array} } \right]$$
(3)
Fig. 1
A structural block diagram of D D S R F P L L illustrates various components such as; angular speeds, grid voltage, L P F, and angle theta.

Structural diagram of DDSRF PLL

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where \(\left[ {T_{dq}^n } \right]\) is the dq transformation matrix using PLL estimated angle θ as mentioned in Eq. (3) and \(\nu_{\alpha \beta }\) is also calculated from the three-phase utility grid voltage \(\nu_{abc}\) by using Eq. (4). Accordingly, the transformed grid voltage vectors (\(\nu_{dq}^{ + 1}\) and \(\nu_{dq}^{ - 1}\)) are given as an input to the decoupling cells networks (DeCs) for removing oscillations by producing oscillations-free grid voltage vectors as \(\nu_{dq}^{ + 1*}\) and \(\nu_{dq}^{ - 1*}\) as shown in Eqs. (5) and (6). The structural presentation of the DeC is portrayed in Fig. 2.

$$\nu_{\alpha \beta } = \frac{2}{3}\left[ {\begin{array}{*{20}l} 1 \hfill & { - \frac{1}{2}} \hfill & { - \frac{1}{2}} \hfill \\ 0 \hfill & {\frac{\sqrt 3 }{2}} \hfill & { - \frac{\sqrt 3 }{2}} \hfill \\ \end{array} } \right]\nu_{abc}$$
(4)
$$\nu_{dq}^{ + 1*} = \nu_{dq}^{ + 1} - \left[ {T_{dq}^{ + 2} } \right]\overline{\nu }_{dq}^{ - 1}$$
(5)
$$\nu_{dq}^{ - 1*} = \nu_{dq}^{ - 1} - \left[ {T_{dq}^{ - 2} } \right]\overline{\nu }_{dq}^{ + 1}$$
(6)
Fig. 2
A diagram of a decoupling cell depicts its internal structure with sin and cos functions of angle theta. The process removes oscillations from grid voltage vectors.

Internal structure of the single decoupling cell (DeC)

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The oscillations-deprived q component of the resultant positive sequence voltage vector \(\nu_{dq}^{ + 1*}\) is passed through the phase detector of dq PLL. The DDSRF PLL accurately performs during unbalanced and balanced grid faults, frequency variations, and phase jumps having faster system dynamics still being not immuned to voltage interharmonics, DC offset, and harmonics resulting to higher frequency overshoot during faults.

2.2 Multi-sequence Harmonic Decoupling Cell PLL (MSHDC PLL)

MSHDC PLL [25] is primarily a combination of αβ PLL and the MSHDC network which offers a better dynamic response by attenuating the undesirable oscillations. MSHDC module mitigates the oscillations present in the fundamental positive sequence grid voltage. MSHDC PLL exhibits an accurate and fast response by improving the quality of power being injected during abnormal grid conditions. It performs appropriately under both the balanced and unbalanced grid fault situations.

Abnormality in the grid conditions represents the rotating grid voltage vectors utilized to decouple for estimating the voltage vectors efficiently and accurately containing the DC and oscillatory terms. MSHDC PLL estimates the desirable DC components by attenuating the oscillations [25]. The MSHDC module basically utilizes crossfeedback deduction method making first order-based low pass filter (LPF) to ensure improved stability. The diagram of the MSHDC PLL as illustrated in Fig. 3 detects the positive sequence grid voltage component dynamically and rapidly to produce an oscillation deprived positive sequence \(\nu_{dq}^{ + 1}\) voltage signal to the αβ PLL. It cancels out the oscillations and significant harmonics as presented in Fig. 3. The DNαβ PLL [2] is a reduced version of the original extended version of DDSRF PLL that is the MSHDC PLL in dq frame with a decoupling capability that is mathematically expressed as below where n indicates desirable component, whereas m stands for all values excluding n:

$$\nu_{dq}^{*n} = \left[ {T_{dq}^n } \right]\nu_{\alpha \beta } - \sum \limits_{m \ne n} \left\{ {T_{dq}^{\left( {n - m} \right)} } \right\}\overline{\nu }_{dq}^{ *m}$$
(7)
Fig. 3
A structural flow diagram of M S H D C P L L depicts; the sin and cos functions of angle theta, grid voltage, L P F, and decoupled vector as input.

Structural diagram of MSHDC PLL

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2.3 Decoupling Network in Αβ Frame PLL (DNαβ PLL)

DNαβ PLL [2] is the extended version of DDSRF PLL for the elimination of grid harmonics employed in αβ reference frame and is presented in Fig. 4. The DNαβ PLL exhibits insensitivity to grid unbalanced faults and harmonics. The DNαβ PLL comprises of the decoupling network (DN) which consists of several decoupling cells (DeCs) which are already pre-defined to specific voltage or harmonic components for extraction and compensation. Contrasting to DDSRF PLL, the utility voltage is transformed by the selective SRFs for obtaining the fluctuations on the specified converted vectors being decoupled by respective DeCs which are attained by the mathematical Eqs. (8) and (9), where n represents the desirable sequence, whereas m indicates all other grid voltage components. As an instance, an unbalanced voltage with the +5th and −7th harmonic distortions, for getting the desirable sequence of +1, n = +1, and m = +5, −7. \(F\left( s \right)\) as shown in Eq. (10) signifies the use of LPF for removing the remaining oscillations there by feeding back the resulting filtered decoupled vectors \(\nu_{\alpha \beta }^{*m}\) to the decoupling network as presented in Fig. 2.

$$\nu_{\alpha \beta }^{*n} = \left[ {\nu_{\alpha \beta } - \sum \limits_{m \ne n} \left[ {T_{dq}^{ - m} } \right]\left[ {F\left( s \right)} \right]\left[ {T_{dq}^m } \right]\nu_{\alpha \beta }^{*m} } \right]$$
(8)
$$\nu_{dq}^{*n} = \left[ {T_{dq}^n } \right]\nu_{\alpha \beta }^{*n} = \left[ {T_{dq}^n } \right] \left[ {\nu_{\alpha \beta } - \sum \limits_{m \ne n} \left[ {T_{dq}^{ - m} } \right]\left[ {F\left( s \right)} \right]\left[ {T_{dq}^m } \right]\nu_{\alpha \beta }^{*m} } \right]$$
(9)
$$F\left( s \right) = \left[ {\begin{array}{*{20}c} {\frac{{\omega_{cf} }}{{s + \omega_{cf} }}} & 0 \\ 0 & {\frac{{\omega_{cf} }}{{s + \omega_{cf} }}} \\ \end{array} } \right]$$
(10)
Fig. 4
A flow diagram of D N alpha beta P L L depicts; the sin and cos functions of angle theta, grid frequencies, grid voltages, and decoupled vector as input.

Structural diagram of DNαβ PLL

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The suitable cut-off frequency \((\omega_c )\) selection is important to ensure proper subtraction operations. The ideal value of \(\omega_{cf}\) for negative and positive sequence components DeCs is set as \(\omega /\sqrt 2\) where ω = 2π50 rad/s is the fundamental main grid frequency. The ideal cut-off frequency range of the harmonic block is \(0.3\omega \le \omega_{cf} \le 0.7\omega\). DNαβ PLL is capable of eliminating selected lower order harmonics by pre-tuning of DeCs on the basis of prior knowledge to target specific harmonics compensation. More harmonics compensation increases complexity as more number of DeCs are needed. DNαβ PLL is also not immunized to the grid voltage DC offset and interharmonics. DNαβ PLL is a simplified version of the MSHDC PLL. Both the PLLs have same performance with DNαβ PLL having comparatively low complexity.

2.4 Harmonic Interharmonic DC Offset PLL (HIHDO PLL)

The novel HIHDO PLL [16] as presented in Fig. 5 is capable of compensating grid harmonics, DC offset, grid unbalance, and interharmonics with faster system dynamic response. It uses an innovative mathematically canceling DeC for effectively mitigating the DC offset and also the negative sequence utility voltage. Also, one more simple and effective harmonic interharmonic compensation network is utilized for high-frequency oscillations elimination generated by the grid voltage interharmonics and harmonics. The utility voltage is given as an input to the DeC for the accurate and faster elimination of the negative sequence components and also DC offset as mentioned in Eq. (11).

$$\left[ {\begin{array}{*{20}c} {V_{dq}^{* + 1} } \\ {V_{dq}^{* - 1} } \\ {V_{dq}^{*0} } \\ \end{array} } \right] = \left[ {\begin{array}{*{20}c} {\nu_{dq}^{ + 1} } \\ {\nu_{dq}^{ - 1} } \\ {\nu_{dq}^0 } \\ \end{array} } \right] - \left[ {\begin{array}{*{20}c} {\left[ 0 \right]} & {\left[ {T_{dq}^{ + 1 - \left( { - 1} \right)} } \right]} & {\left[ {T_{dq}^{ + 1 - \left( 0 \right)} } \right]} \\ {\left[ {T_{dq}^{ - 1 - \left( { + 1} \right)} } \right]} & {\left[ 0 \right]} & {\left[ {T_{dq}^{ + 1 - \left( 0 \right)} } \right]} \\ {\left[ {T_{dq}^{0 - \left( { + 1} \right)} } \right]} & {\left[ {T_{dq}^{0 - \left( { - 1} \right)} } \right]} & {\left[ 0 \right]} \\ \end{array} } \right]\left[ {\begin{array}{*{20}c} {\overline{V}_{dq}^{* + 1} } \\ {\overline{V}_{dq}^{* - 1} } \\ {\overline{V}_{dq}^{*0} } \\ \end{array} } \right]$$
(11)
Fig. 5
A block diagram depicts the structure of H I H D O P L L. It comprises a harmonic compensation cell with L P F, H P F and D C offset cancellation.

Structural diagram of HIHDO PLL

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Here, \(\overline{V}_{dq}^{*n} = F\left( s \right)V_{dq}^{*n}\) is the estimated filtered grid voltage, and cut-off frequency selection is not same for each individual component. For the negative and positive sequence components, the optimum cut-off frequency value is \(\omega /\sqrt 2\) with a lower cut-off frequency as \(\omega /4.5\) that is needed for the DC component \(V_{dq}^{*0}\) extraction [42]. The need for lower cut-off frequency is important to generate the oscillations of DC voltage vectors by the cross-coupled positive sequence and negative sequence components. The extracted positive sequence grid voltage vector \(V_{dq}^{* + 1}\) for DC offset and unbalance compensation is derived from the DeCs by passing next to the harmonic compensation network making interharmonics and harmonics mitigation effective as stated in Eq. (12). Lastly, the q component of resultant vector \(\overline{V}_{dq}^{* + 1}\) is then sent to the PLL’s phase detector for frequency and phase extraction. The suitable cut-off frequency \(\left( {\omega_H } \right)\) ranges as \(0.2\omega \le \omega_H \le 0.45\omega\) for the accurate and speedy dynamic response of high pass filter [16]. The HIHDO PLL needs no prior knowledge of the targeted harmonics and interharmonics for compensation presenting a fast system dynamic response. Any grid harmonics and interharmonics can be compensated by the HIHDO PLL but still as more numbers of Park’s transformation modules are used due to its operation in dq frame, the complexity of the controller increases.

$$\overline{V}_{dq}^{* + 1} = V_{dq}^{* + 1} - \left[ {\begin{array}{*{20}c} {\frac{{\omega_{cf} }}{s + \omega_H }} & 0 \\ 0 & {\frac{{\omega_{cf} }}{s + \omega_H }} \\ \end{array} } \right]V_{dq}^{* + 1}$$
(12)

2.5 Less Complex Disturbance Rejection PLL (LCDR PLL)

Lately, the modification of HIHDO PLL has led to generation of the LCDR PLL [27] which offers superior performance abilities with lower complexity though being same as the HIHDO PLL. The development of the LCDR PLL utilizes a less mathematically complex DC offset mitigating module in dq frame that is depicted in Fig. 6. The governing equation of the developed LCDR PLL is presented as below:

$$\overline{V}_{{\text{d}}q}^{n*} = \left[ {T_{{\text{d}}q}^{ - n} } \right]\left( {\nu_{\alpha \beta } - \sum_{m \ne n} {V_{\alpha \beta }^{ - m^{\prime}} } } \right)$$
(13)
Fig. 6
A structural diagram of L C D R P L L. It comprises a harmonic or interharmonic mitigation module, a D C offset mathematic cancellation and a phase detector part.

Structural diagram of LCDR PLL

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The \(\overline{V }_{dq}^{ + 1*}\) found from Eq. (13) is sent to the harmonic compensation module [same as (12)] for oscillations mitigation that are produced by the harmonics and interharmonics disturbances. The output \(\overline{V}_{q - p}^{ + 1*}\) is then fed to the PLL’s phase detector to extract the desirable phase angle and grid frequency. Consequently, the LCDR PLL works efficiently under various distorted grid conditions like imbalanced grid faults, interharmonics, DC offset, and grid voltage harmonics with a reduction in the computational complexity with quicker dynamic response. According to the performing capabilities, lower complexity, and faster dynamic response, LCDR PLL is concluded to be the least complex and most advanced PLL.

3 Performance Comparison of the Three-Phase Advanced PLLs

The performance abilities of various advanced PLLs have been studied, compared, and represented in Table 1. The comparative performance analysis has been done and summarized in terms of PLL’s dynamic response, complexity, operation during adverse circumstances, overshoot present in estimated frequency/phase, frequency changes, and three-phase grid blackout or faults. The DDSRF PLL needs least computation among all PLLs though not immuned to the distorted utility grid environments. The MSHDC PLL and DNαβ PLL exhibit equal performance though the MSHDC PLL has comparatively less complexity. The key demerit of the DNαβ PLL is that it has still significant complications in comparison to other PLLs as it is only immuned to selective harmonics and has higher overshoot and imprecise response during severe faults. The LCDR PLL still same as HIHDO PLL is found as the simplest, advanced, and fastest PLL with an advantage of compensating any DC offset, interharmonics, and harmonics existing in grid voltage with a faster system dynamic response without any need of prior knowledge.

Table 1 Performance comparison among the advanced PLLs
Full size table

4 Conclusion

This paper aims on providing a review of various latest PLLs based on the modification of the DDSRF PLL. Their detailed review has been studied and also compared depending on modification of each PLL’s performance, system dynamic response, and computing complication. Their detailed explanation with operational principle and system performance with the merits and demerits have been showcased. The review provides a conclusion that the LCDR PLL is the superior among all being the best-performing advanced PLL with low complexity. The grid-integrated DPGS control and operation through PLLs must be very accurate and fast (lower settling time) in response to different grid conditions like balanced or unbalanced faults, grid harmonics, DC offset, and interharmonics (Table 1). The DDSRF PLL can be preferred due to its fastest response, but the HIHDO PLL or LCDR PLL was found to be the best choice from the PLL selection guide tackling all kind of grid distortions.