Abstract
Matrix multiplication is one of the crucial operations in most of the digital signal processing applications. The number of additions and multiplications required in this operation may become quite large as the order of the matrix increases. In this paper, the design and simulation of matrix multiplication architecture using canonical signed digit representation of binary numbers have been presented. Real-time implementation of various signal processing applications like dynamic time warping (DTW) is hindered because of the speed constraints posed by the delay in multiplication operations. The speed of multiplication operation can be increased using canonical signed digit (CSD) representation of numbers instead of 2’s complement representation. In this work, comparative analysis of various binary multipliers along with CSD multiplier based on field-programmable gate array (FPGA) in Verilog Hardware Description Language has been done followed with the simulation of matrix multiplier using the proposed technique. The target device used in the work for synthesis purpose is xa6slx4-3-csg225 in Xilinx. Simulation has been performed in ModelSim.
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Koul, R., Yadav, M., Suneja, K. (2020). Novel FPGA-Based Hardware Design of Canonical Signed Digit Matrix Multiplier and Its Comparative Analysis with Other Multipliers. In: Mathur, G., Sharma, H., Bundele, M., Dey, N., Paprzycki, M. (eds) International Conference on Artificial Intelligence: Advances and Applications 2019. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-15-1059-5_8
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DOI: https://doi.org/10.1007/978-981-15-1059-5_8
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