Keywords

1 Introduction

The demand for faster cheaper and smaller devices has led to the downscaling of MOSFETs to well below 30 nm for VLSI application, and has successfully been fabricated and characterized [1, 2]. However, with a decrease in the channel length, the device performance is found to be continuously degrading, because many physical barriers arise like short-channel effects, drain-induced barrier lowering, punch through, etc. [3, 4]. One of the main technological roadblocks when we scale these devices beyond some limit is that the high mechanical leakage current penetrates through the gate oxide and it increases the power dissipation [5]. The direct tunneling current increases exponentially with the decrease in oxide thickness which is of primary concern of MOS scaling [6, 7]. From research of recent years, it is seen that the modified structures like double gate, triple structure, and gate around structures are found to be more promising than the conventional model. The structure is shown in Fig. 1.

Fig. 1
figure 1

Modified MOSFET structure of 22 nm × 60 nm

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2 Device Structure and Simulation Setup

In the n-MOSFET, the majority carriers in the channel are electrons. The drain current at a corresponding gate and drain voltage can be increased if the electron density in the channel increases, correspondingly the hole concentration decreases. In order to enhance the electron concentration in the channel, an n-type moderately doped region is inserted in the substrate [8]. The doped region in the substrate is positioned in such a way that it is below the half of source and the channel. The holes in the channel are attracted by the introduced moderately doped region in the substrate, thereby increasing the electron concentration in the channel. Since the doped region introduced is layering in the substrate, there may be some leakage. Therefore, the base of the substrate is insulated by SiO2, which is of 1 nm thickness, so that there is no possibility of leakage through the substrate [9, 10]. Figure 2 shows the structure formation.

Fig. 2
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Structure formation

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2.1 Fabrication Steps

A moderately doped region is inserted in a p-type silicon substrate using N-well process. After the formation of the SiO2 layer using oxygen ion implantation technology [11], the structure is first rotated 180° vertically [12] and horizontally. Now using the fabrication of conventional n-MOSFET, the complete structure can be developed. Figure 3 shows the fabrication steps.

Fig. 3
figure 3

Fabrication steps

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2.2 Simulation Setup

A 20 nm n-MOSFET with the doped region in the substrate is designed using the ATLAS simulator of the Silvaco TCAD, and then the same device has been also designed for the channel length of 30–40 nm to a make comparison with varying channel length. 30–40 nm conventional MOSFET is designed to find the comparison with the new doping of MOSFET. Figures 4 and 5 show the structure designed.

Fig. 4
figure 4

40 nm modified MOSFET

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Fig. 5
figure 5

40 nm conventional MOSFET

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3 Results and Discussions

3.1 Drain Biasing

The drain is biased with Vd = 0.1 V and the gate voltage is varied with 0–3 V to obtain the Id versus Vg characteristics for 20, 30, and 40 nm modified n-MOSFET. Figure 6 shows the Id–Vg characteristics.

Fig. 6
figure 6

Drain current obtained at Vg = 3 V

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The graphs show the Id–Vg characteristics of the modified n-MOSFET for 40, 30, and 20 nm channel length. On comparing them, we can observe that as channel length decreases the slope of the curve increases which follows the characteristics of the conventional MOSFET.

3.2 Gate Biasing

The gate is biased with Vg = 1.1, 2.2, and 3.3 V, and the drain voltage is varied from 0 to 3 V to obtain the Id versus Vds curve. And a comparison is done among 20, 30, and 40 nm.

The graphs showing the Id–Vd characteristics of the modified n-MOSFET for 20 nm channel length is shown in Fig. 7. On comparing them, we can observe that as channel length decreases the slope of the curve increases, thus yielding a higher drain current and it follows the characteristics of the conventional MOSFET.

Fig. 7
figure 7

Id–Vd characteristics for 20 nm channel length

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3.3 Comparison of Conventional MOSFET and Proposed MOSFET

Drain Biasing: Drain biasing is performed on both the structures and a comparison is made for 40 nm channel length. Figure 8 shows the results obtained for the comparison on the drain biasing.

Fig. 8
figure 8

Id versus Vg curve for 40 nm

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The slope of the characteristics is equal to 1/Ron. If we compare both, we can see that the new MOSFET has a greater slope than the conventional MOSFET; hence, it has a greater drain current than the conventional one.

Gate Biasing: The gate is biased with Vg = 1.1, 2.2, and 3.3 V, and the drain voltage is varied from 0 to 3 V to obtain the Id versus Vds curve. And a comparison is done among 40 nm. Both have a 40 nm channel length, which follows the characteristics of the conventional MOSFET. On comparing the characteristics of both the devices, we can see that the new MOSFET has a greater slope than the conventional MOSFET in all gate voltages of 1.1, 2.2, and 3.3 V; hence, it yields a greater drain current than the conventional one.

Leakage Current Analysis: Leakage current analysis is performed on the MOSFETS with channel length of 30 nm and 40 nm and a comparison is done between the devices at respective channel lengths. The results obtained for 30 nm are shown in Fig. 9.

Fig. 9
figure 9

Leakage current comparison at 30 nm channel length

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It is observed that the leakage current is minimized; in case of 30 nm it is 1.154 mA less, and in case of 40 nm it is 5 uA less than the conventional MOSFET.

4 Conclusion

The results obtained from the drain and gate biasing signify that the MOSFET with the newly introduced doped region obeys the characteristics of the conventional MOSFET. On comparing the drain current of modified MOSFET with the conventional MOSFET at different conditions of gate voltage, drain voltage, and channel length, the modified MOSFET has a higher value, and thus the gain will be higher. The leakage current of the modified MOSFET is found to be less than the conventional MOSFET, and hence the power consumption will be minimized.