Keywords

1 Introduction

With unrelenting advancements in the electronics domain, the demand for compact devices which can operate using comparatively lower voltage values with reduced power dissipation increase. However, the high operating frequency requirements, the complex processing involved, and the continuous scaling of devices lead to increased leakage current, which in turn lead to increased power consumption. Many researchers focus on the optimization of power by realizing enhanced control over the gate structure with the required channel current of the MOS device, even while maintaining control over the leakage current.

Conventional CMOS circuits dissipate power in the pull-up and pull-down MOS devices during the charging and discharging operations related to the nodal capacitance. This leads toward increased power dissipation in CMOS circuits while operating at high frequencies. These disadvantages point toward a new contemporary logic called as “Adiabatic Logic” or “Energy Recovery Logic.” This is accomplished by the recovery of a major portion of the energy that is expended in the nodal capacitances, and the energy so recovered is reused during the successive computations. Adiabatic logic design is categorized into two major divisions as follows: (1) Quasi-adiabatic logic circuit and (2) Fully adiabatic logic circuit. Some of the prevailing quasi-adiabatic logic circuits found in literatures are 2N2P [1], 2N-2N2P, Positive feedback adiabatic logic (PFAL) [2], Differential cascode pre-resolve adiabatic logic (DCPAL) [3], Pre-resolve and sense adiabatic logic (PSAL) [4], and Complementary pass-transistor logic (CPAL) [5].

Scaling of technology raises the leakage power dissipation. Some of the major causes of leakage power are mainly due to the sub-threshold leakage current that arises due to low threshold voltage and that due to the gate leakage current which occurs due to the thin gate-oxide material. To overcome the effect of such leakage current effects, several new devices have been suggested as an alternative to conventional MOSFFETs. Some of them are as follows: ultra-thin body devices, fully depleted silicon insulator (FDSOI), and fin-based field effect transistor (FinFET) [6].

The paper is organized as follows: Sect. 2 summarizes the operation of FinFET. Section 3 presents FinFET-based adiabatic logic circuit design. Section 4 depicts the proposed MCPAL adiabatic logic circuit. Section 5 presents the results and discussion. Section 6 concludes.

2 FinFETs

The structure of FinFET shown in Fig. 1 is derived from the folded channel MOSFET. It consists of a Fin designed using a silicon material, which acts as the body of the device. The source and drain terminals are arranged opposite to the fin in such way that it realizes efficient control over the channel, and it in reality effectively minimizes the short channel effects and leakage current, majorly felt in MOSFETs.

Fig. 1
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Structure of FinFET

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Various operating modes of the FinFET are as follows:

  1. (1)

    Shorted Gate (SG) mode, where both the front and back gates are tied together and this mode exhibits high switching speed and better resistance to short channel effects.

  2. (2)

    Reverse Bias (RB) mode, where one of the gates is kept reverse biased. Usually, the back gate is preferred as it has less V th which can be varied. This approach is, however, slow and it delivers increased area overhead.

  3. (3)

    Independent Gate (IG) mode, where both the gates operate individually. It consumes a lesser amount of area when compared with the other modes of operation.

3 Adiabatic Logic Circuits

Adiabatic logic circuits are capable of recovering a significant quantity of energy spent at the capacitive output nodes. Adiabatic logic circuits utilize the power clock (PC) sources as the energy source. Energy is supplied to the adiabatic logic circuits during the evaluation phase by the power clock signal and energy stored in the nodal capacitances is recovered back during the recovery phase. PC signals are so-called because they power up the adiabatic logic circuits and also these signals maintain the timing of adiabatic circuit stages [7]. The shape of PC enables operation of adiabatic circuits in four different phases, namely (1) Evaluation phase, where PC rises from 0 V to peak voltage, (2) Hold phase, when PC is constant for enabling next stage pipelining evaluates its input, (3) Recovery phase, when PC drops down from peak voltage to 0 V thus allowing charge recovery from output nodes back to PC, and (4) Wait phase, where PC is in 0 V level which aids in synchronization process across the stages.

Adiabatic logic circuits such as the 2N2P, 2N-2N2P, and PFAL operate with only one power clock signal whereas DCPAL and PSAL utilize two power clock signals with pre-resolving phase as its first phase followed by evaluation, hold and recovery phases. Each PC signal varies by 90°. This signal lags behind IN by 90°. A phase shift of 90° exists between input and output. This aids in cascading the pipelined stages. A 4-stage adiabatic inverter chain is shown in Fig. 2. Input, output, and PC waveforms are presented in Fig. 3. The 2N2P, 2N-2N2P, PFAL, DCPAL, and CPAL type of adiabatic circuits are shown in Fig. 4a–e, respectively. 2N2P contains a latch formed by the cross-coupled pFinFET and nFinFET, whereas 2N-2N2P and PFAL consist of two latches formed by pFinFET and nFinFET. 2N2P suffers from the floating output node problem, when OUT node cannot find a recovery path to PC. This is eliminated in 2N-2N2P, due to the additional nFinFET present in pull-down network.

Fig. 2
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Structure of a 4-stage cascaded adiabatic pipeline

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Fig. 3
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Input–output, power clock transients

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Fig. 4
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Basic adiabatic logic circuit

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DCPAL consists of a pre-resolving phase, where it pre-resolves the input which is made to reflect on the corresponding output nodes. Also, it has a footer nFin device powered by PC3 [8]. PC3 leads PC1 by 180°. A similar conception has been used in PSAL. PSAL is very much similar to DCPAL, however, with the 2P latch replaced by 2N2P latch. The operational enhancement of PSAL is its capability to of operate at very low frequency. Leakage current in PSAL is very much reduced due to the presence of the stacking footer transistor. PFAL logic circuit has its functional block in the pull-up network. CPAL utilizes CPL (complementary pass-transistor logic) as its functional unit and consumes a smaller amount of power. To discuss its operation in brief, consider when PC ramps up in evaluation phase, IN is high. Then, node X is charged to higher level than V DD-V th, and OUT node is charged to V dd and/OUT is pulled down to ground, and node Y is pulled down to ground. During recovery phase, PC ramps down and hence the charge in OUT node is recovered through MN3.

4 Proposed MCPAL Adiabatic Logic Circuit

This section presents the proposed MCPAL circuit, which employs complementary pass-transistor logic, which is efficient in reducing the leakage current from power supply to ground. If the common unit in the adiabatic logic circuit is designed well enough to reduce power, then the entire circuit operates in a state, where power is minimum when compared with its counterparts. The MCPAL is designed using 32 nm device operating in shorted gate mode. Major advantage of this method is the use of forced stack transistors to reduce the leakage current. MCPAL consists of a functional block formed by MN5, MN6, MN7, and MN8 shown in dotted blocks and load drive circuit formed by MN1-MN4 and MP1-MP2.

The Modified CPAL inverter of Fig. 5a with PC, input and output represented in Fig. 5b, operates as follows:

Fig. 5
figure 5

a Proposed MCPAL inverter circuit, b proposed MCPAL input–output transients

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  1. (i)

    Evaluation Phase: When the power clock rises from zero to peak voltage, depending upon IN and/IN either X or Y remains at HIGH voltage. Consider node X is stable at high voltage, which turns on MN1. MN3 and MN4 are biased by a high voltage and hence the OUT node is pulled down to ground. This low voltage switches ON MP2 and/OUT is pulled up to PC. Latch formations due to the cross-coupled pFin devices stabilize the outputs from the complementary pass-transistor logic. MN3 and MN4 act as stack transistors and their on/off state is similar to MN1 and MN2.

  2. (ii)

    Hold phase: During this phase, PC is high which maintains the output state for evaluation by the next adiabatic stage and IN drops to 0 V. This in turn turns off MN1. Leakage current is reduced to a greater extent by the stack transistors MN3 and MN4.

  3. (iii)

    Recovery phase: In this phase, when PC drops to zero, node X remains at zero and charge stored at the output nodal capacitances is recovered by PC through the pull-up network. Major benefit of the stacked transistor is that they recover the maximum possible charge from output nodes instead of expending it to the ground.

5 Results and Discussion

This section presents the results, and analyses are made for validating the efficiency of the proposed MCPAL. Figure 6 depicts the input–output transients along with energy recovery waveform of MCPAL-based inverter.

Fig. 6
figure 6

Input–output transients of proposed MCPAL

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Figure 7 presents energy comparison of 2N2P, 2N-2N2P, PFAL, DCPAL, and CPAL inverters at 100 MHz, incurring energy of 25.55 aJ, 26.90 aJ, 37.88 aJ, 43.10 aJ, 128.0 fJ, respectively. It can be observed that MCPAL incurs 24.28 aJ, which is very less when compared with all its counterparts. Table 1 depicts the power and energy dissipation comparison among the logic families considered. The energy spent by the 2N2P, 2N-2N2P, PFAL, DCPAL, and CPAL are 657.9 aJ, 461.3 aJ, 500.8 aJ, 773.1 aJ and 718.2 aJ, respectively, at 500 MHz, with MCPAL incurring only 243.5 aJ. Figure 8a, b shows performance comparison of MCPAL inverter designed using CMOS and FinFET operating at 1 V and 500 MHz frequency.

Fig. 7
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Energy comparison of buffers at 100 MHz frequency

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Table 1 Power and energy dissipation comparison of the adiabatic logic families
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Fig. 8
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a Power comparison of MCPAL inverters using FinFET and CMOS, b energy comparison of MCPAL inverters using FinFET and CMOS

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Table 2 shows comparative energy levels of the adiabatic logic families across the frequency range. This is graphically represented in Fig. 9. It is apparent that MCPAL consumes very less energy when compared with other adiabatic logic families. Table 3 depicts the energy dissipation incurred by adiabatic logic families with 512 cascaded inverter stages operating at 500 MHz and 1 V. From the results, it is clear that MCPAL utilizes 2.44fJ which is too less when compared against other adiabatic logic families.

Table 2 Energy dissipation of various adiabatic logic families across a range of frequency
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Fig. 9
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Frequency versus energy for FinFET-based adiabatic logic inverter circuits

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Table 3 Energy dissipation of 512 cascaded inverters designed using various adiabatic logic families
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6 Conclusion

In this paper, the FinFET-based MCPAL adiabatic logic circuit is presented. The logic is capable of operating at a wide range of frequency from KHz to MHz. Validation of the proposed logic is carried out by comparing an inverter designed using MCPAL with 2 N2P, 2 N-2N2P, PFAL, DCPAL, and CPAL inverter circuits designed using both MOSFET and FinFET. The FinFET-based MCPAL circuit dissipates 62, 47, 51, 68, and 66% lower than 2N2P, 2N-2N2P, PFAL, DCPAL, and CPAL, respectively. Furthermore, the MCPAL realizes lower power dissipation and incurs lower energy due to lower leakage current and improved charge recovery capability.