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9.1 Mixed-Mode Device and Circuit Simulation

To evaluate the physical insight into the Colpitts oscillator circuit operation, the mixed-mode device and circuit simulation using Sentaurus TCAD software [1] is adopted. In Sentaurus device simulation, Poisson’s and continuity equations with drift-diffusion transport are implemented. The Shockley–Read–Hall carrier recombination, Auger recombination, and impact ionization models are used. The physical model for impact ionization used in this work is the University of Bologna impact ionization model, based on impact ionization data generated by the Boltzmann solver [2]. It covers a wide range of electric fields (50–600 kV/cm) and temperatures (300–700 K). It is calibrated against impact ionization measurements in the whole temperature range [3]. The low field mobility is calculated by Mathiessen’s rule and incorporates the bulk and surface mobility. To account for lattice heating, Thermodynamic, Thermode, RecGenHeat, and AnalyticTEP models in Sentaurus are included. The thermodynamic model extends the drift-diffusion approach to account for electrothermal effects. A Thermode is a boundary where the Dirichlet boundary condition is set for the lattice. RecGenHeat includes generation–recombination heat sources. AnalyticTEP gives the analytical expression for thermoelectric power.

Figure 9.1 shows the Colpitts oscillator used in the mixed-mode device and circuit simulation [4]. The mixed-mode simulation provides the device physical insight and response in the practical circuit environment. In Sentaurus simulation, the MOSFET has the channel length of 65 nm and the channel width of 64 µm. The circuit parameters used are C 1 = 22 pF, C 2 = 27.2 pF, L D  = 0.15 nH, R D  = 2900 Ω, R S  = 40 Ω, V G  = 1.8 V, and V DD = 3.3 V. The simulated oscillator output response from Sentaurus is displayed in Fig. 9.2. The oscillator has a sinusoidal oscillating output waveform from 0.5 to 2.9 V. To analyze the reliability effect on the Colpitts oscillator, gate-source voltage and drain-source voltage as a function of time are depicted in Fig. 9.3. Examining the voltage waveforms in Fig. 9.3, one can define three key points a, b, and c (i.e., the bottom, middle, and top of the output voltage) to probe impact ionization and self-heating at these three critical time points. The I.I. rates, electric field, and total current density from Sentaurus mixed-mode device and circuit simulation are plotted in Figs. 9.4, 9.5, and 9.6, respectively. Note that no lattice heating of the Colpitts oscillator was observed in mixed-mode device and circuit simulation (data not shown).

Fig. 9.1
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Schematics of an oscillator used in the mixed-mode device and circuit simulation

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Fig. 9.2
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Oscillator output response from mixed-mode device and circuit simulation (© IEEE)

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Fig. 9.3
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Gate-source and drain-source voltages versus time (© IEEE)

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Fig. 9.4
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Impact ionization rates at points a, b, and c in Fig. 9.2 (© IEEE)

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Fig. 9.5
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Electric field at points a, b, and c in Fig. 9.2 (© IEEE)

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Fig. 9.6
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Total current density at points a, b, and c in Fig. 9.2 (© IEEE)

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To investigate the physical insight into hot electron injection, impact ionization rates at the three different time points are shown in Fig. 9.4. At point a the drain-source voltage reaches the minimum and its corresponding electric field is low; however, the current density is very high due to large V GS (see Fig. 9.5). At point c, the I.I. rates are high because the drain-source voltage reaches the maximum. The impact ionization rates at point b are higher than those at points a. This is attributed to relatively high drain-source voltage and drain current density at point b, as indicated in Fig. 9.3. Higher drain current enhances I.I. generated carriers under high electric field. The peak impact ionization rates at points b and c reach 1 × 1026/cm3/s, a precursor of hot carrier effect. The hot electron reliability issue becomes even more important when the channel length of the nMOSFET is decreasing and the supply voltage of the circuit is increasing.

The phase noise of Colpitts oscillator shown in Fig. 9.1 is analyzed for examining device parameter variations. The phase noise to account for MOS transistor parameter drift due to aging is expressed as [5]:

$$\begin{aligned} L(\Delta f) & = 10\log \left( {\frac{{\bar{V}_{n}^{2} }}{{2\bar{V}_\text{{tank}}^{2} }}} \right) \\ & = 10\log \left\{ {\left[ {\left( {\frac{{\left| {g_{m(1)} } \right|^{2} K_{f} }}{{4C_\text{{ox}} WL\Delta f}} + \sum\limits_{n = 1}^{\infty } {\left| {g_{m(n - 1)} + g_{m(n + 1)} } \right|^{2} \times \frac{kT\gamma }{{\bar{g}_{m} }}} } \right)\alpha + \frac{kT}{R}} \right]\left( {\frac{{Rf_{0} }}{{Q\Delta fA_{S} }}} \right)^{2} } \right\} \\ \end{aligned}$$
(9.1)

where V n is the output noise voltage, V tank is the signal voltage of the oscillator output, g m(n) is the nth Fourier coefficients of transconductance, K f is a process dependent constant on the order of 10−25 V 2 F, f 0 is the center frequency, γ is a coefficient (about 2/3 for long-channel transistors and larger for submicron MOSFETs), \(\bar{g}_{m}\) is the average transconductance of the transistor, α is the transfer parameter from nonlinear network port to linear network port (α = (1 − F)2, where F = C 1/(C 1 + C 2)), R is the parasitic resistance in the LC tank, Q is the quality factor of LC tank, and A S is the amplitude of the AC voltage at the source of the transistor.

In (9.1) \(\bar{g}{}_{m} = \beta A_{S} (\sin \theta - \theta \cos \theta )/\pi ,\) β = μ n0 C ox W/L,  θ = cos −1[(V T  − V G )/A S }, β = μ n0 C ox W/L, g m(n) = g m(−n), and

$$g{}_{m(n)} = \left\{ {\begin{array}{*{20}l} {\beta A_{S} \left[ {\frac{(\sin \theta - \theta \cos \theta )}{\pi }} \right]} \hfill & {\text{for}\,n = 0} \hfill \\ {\beta A_{S} \left[ {\frac{(\theta - \sin \theta \cos \theta )}{\pi }} \right]} \hfill & {\text{for}\,n = 1} \hfill \\ {2\beta A_{S} \left[ {\frac{\sin n\theta \cos \theta - n\cos \theta \sin \theta }{{n(n^{2} - 1)\pi }}} \right]} \hfill & {\text{for}\,n \ge 2} \hfill \\ \end{array} } \right.$$
(9.2)

The Colpitts oscillator shown in Fig. 9.1 has been simulated in ADS. To be consistent with the mixed-mode simulation condition, the same circuit element values used in mixed-mode simulation are also used in the ADS circuit simulation. The simulated output waveform as a function of time and its Spectral density versus frequency are depicted in Figs. 9.7 and 9.8. The oscillation frequency measured from Fig. 9.7 is 2.4 GHz and its fundamental signal Spectral power is −4 dBm at 2.4 GHz. The phase noise predicted by the analytical equation in (9.1) is compared with that by the ADS simulation result in Fig. 9.9. In Fig. 9.9, the solid circles represent the model predictions and the solid line represents the ADS simulation. A good agreement between the model predictions and ADS simulation results before hot electron stress is obtained. The HCI effect on the phase noise is also displayed using K f factor in (9.1). As seen in Fig. 9.9 the phase increases with increasing K f factor, which is related to the interface quality or interface states between the SiO2 and Si interface. Intuitively, the worse the process condition, the larger is the interface states. The longer the stress time, the larger is the interface trap density [6]. If the analytical equation on process and stress dependent K f factor becomes available, Eq. (9.1) can account for more process and stress effects inclusively. As hot carriers generate more interface states at the SiO2 and Si interfacial layer, the K f factor increases, thus the 1/f noise of the MOSFET and phase noise of the oscillator increase.

Fig. 9.7
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Simulated output waveform versus time

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Fig. 9.8
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Simulated output power spectrum characteristics

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Fig. 9.9
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Phase noise modeling versus offset frequency including K f effect

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9.2 Process Variability and Adaptive Body Bias

RDF [7] remains the dominant source of statistical variability and is mainly caused by silicon dopant fluctuations during fabrication process. It becomes more severe as device size shrinks. LER [8], a random deviation of line edges from gate definition, does not scale with line width. PGG [9] is attributed to gate dielectric thickness variations which contribute to threshold voltage variation. All the above mentioned process variations cause fluctuation of threshold voltage, mobility, and oxide thickness, which in turn affect the device and circuit performance. Furthermore, reliability issue could widen the standard derivation of process variation in Gaussian distribution [10].

To further examine the process variation and reliability impact on Colpitts oscillator, Monte Carlo (MC) circuit simulation has been performed. In ADS, the Monte Carlo simulation assumes statistical variations (Gaussian distribution) of transistor model parameters such as the threshold voltage, mobility, and oxide thickness. After Monte Carlo simulations with a sample size of 1000, the phase noise variation is displayed in Fig. 9.10. In this histogram plot, the x-axis shows the phase noise distribution of the oscillator without body effect and y-axis displays the probability density of occurrence. The mean value of phase noise is −121 dBc/Hz and the standard deviation is 0.71 dBc/Hz. In Monte Carlo simulation, the initial values of V T0, µ 0, and t ox are 0.42 V, 491 cm2/V s, and 1.85 nm, respectively. The statistical variations for V T0, µ 0, and t ox are set at ±10, ±5, and ±3 % from 65 nm technology node.

Fig. 9.10
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Phase noise distribution @ Δf = 400 kHz (© IEEE)

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To reduce the process variation effect on the Colpitts oscillator, an adaptive body bias scheme as shown in Fig. 9.11 is proposed. In Fig. 9.11, the body bias of M1 is determined by the adaptive body bias circuit in the dashed oval circle.

Fig. 9.11
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Colpitts oscillator with adaptive body bias (© IEEE)

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To account for the body bias effect, the threshold voltage of M1 can be written as

$$V_{T} = V{}_{T0} + \gamma {}_{b}\left( {\sqrt {2\phi_{F} - V_\text{{BS}} } - \sqrt {2\phi_{F} } } \right)$$
(9.3)

where V BS is the body-source voltage. Note that the source voltage V S in this circuit is not necessarily equal to zero, unlike the case of power amplifiers in Chap. 8.

The drain current of the MOSFET including the body bias effect can be approximated as

$$I_{DS} \approx \frac{{\mu_{n0} C_\text{{ox}} W}}{{2L[1 + \theta_{1} (V_{GS} - V_{T} ) + \theta_{2} V_\text{{BS}} ]}}(V_{GS} - V{}_{T})^{2}$$
(9.4)

The transconductance based on the derivative of drain current with respect to gate-source voltage is derived as

$$g_{m} \equiv \frac{{\partial I_{DS} }}{{\partial V_{GS} }} = \frac{{\mu_{n0} C_\text{{ox}} W}}{2L}\frac{{2(V_{GS} - V_{T} )(1 + \theta_{2} V_\text{{BS}} ) + \theta_{1} (V_{GS} - V_{T} )^{2} }}{{[1 + \theta_{1} (V_{GS} - V_{T} ) + \theta_{2} V_\text{{BS}} ]^{2} }}$$
(9.5)

The transconductance equation taking the body bias into account in (9.5) is then used in the phase noise prediction in (9.1) for the oscillator with an adaptive body bias.

The MC simulation result of the Colpitts oscillator including the body bias effect is shown in Fig. 9.12. In this histogram plot, the mean value of phase noise is −121 dBc/Hz and the standard deviation is 0.18 dBc/Hz. The phase noise is evaluated at the offset frequency of 400 kHz.

Fig. 9.12
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Phase noise distribution using the adaptive body bias scheme (Δf is at 400 kHz) (© IEEE)

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Comparing Figs. 9.10 and 9.12, the adaptive body bias clearly reduces the oscillator process sensitivity significantly. The use of adaptive body bias to reduce process variability effect on the Colpitts oscillator can be explained as follows: The threshold voltage shift including body bias effect can be expressed as

$$\Delta V_{T} =\Delta V{}_{T0} - \frac{{\gamma_{b} \times\Delta V_\text{{BS}} }}{{2\sqrt {2\phi_{F} - V_\text{{BS}} } }}$$
(9.6)

where ΔV T0 is the threshold voltage change resulting from process variations and ΔV BS is produced due to current variation and the use of body bias circuit. The minus sign of the second term in (9.6) indicates that the body bias effect provides a compensation effect for threshold voltage variations from process uncertainties. Again, when the process variations increase the threshold voltage of M1 in Fig. 9.11, the body bias V B to M1 increases due to less I D2 R B ohmic loss in the adaptive body bias circuit. This tends to decrease the V T in M1 to compensate the initial increase in V T . On the other hand, when process variability decreases the V T in M1, the adaptive body bias circuit will decrease the V B to M1. This in turn increases the V T in M1 to compensate the initial decrease in V T .