Abstract
This chapter discusses the process variation effect on power amplifier performance. Extensive analytical equations are derived. The adaptive body bias technique to reduce the process variation effect on the power amplifier performance variation is presented.
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It is clear that smaller feature size makes the MOSFET more sensitive to the process variations and stress-induced degradations. The circuit designer needs larger design margin to insure circuit robustness against such issues as yield and reliability. The process variability and reliability resilience design may reduce over design, while increase yield and circuit robustness. The resilient biasing technique aims to design reliable circuits capable of post-process adjustment and insensitive to the transistor parameter degradations over long-term stress effect.
Figure 8.1 shows a simplified variability and reliability resilient biasing design for the power amplifier, which introduces tunable adaptive body biasing.
The right branch of the circuit in Fig. 8.1 controls the body potential of the MOSFET M1. Thus, the threshold voltage of M1 can be adjusted by the body bias. The voltage source V tune is used for post-fabrication calibration. During the long-term usage, both M1 and M2 are subject to similar reliability induced threshold voltage and electron mobility shifts. When the V T of M2 increases, the branch current I R1 will decrease. The reduction in the branch current leads to an increase in the node voltage V B . Therefore, the V T of M1 will decrease due to combined reliability degradation and body effect. Similar mechanism applies to electron mobility degradation on both transistors. The drain current of M1 is thus more stable because of resilient biasing design scheme.
8.1 Analytical Model and Equations
Again, using the approach laid out in Chap. 7, the V T shift of M1 due to degradations of both M1 and M2 is given by
The mobility degradation results in a decrease in drain current also. The drain current of M1 is simplified as \(I_{D} \approx \beta (V_{\text{GS}} - V_{T} )^{2} /2,\) where \(\beta\) variation due to mobility degradation is given by
Clearly, β variation is linearly proportion to the electron mobility drift. The same relationship also applies to β′. The node voltage V B fluctuation due to mobility degradation is simplified to \(\delta V_{B} \approx \frac{{\partial V_{B} }}{{\partial \beta^{{\prime }} }}\delta \beta^{{\prime }}\) . Using (8.2) \(\frac{{\partial V_{B} }}{{\partial \beta^{{\prime }} }}\) is derived below:
From the result in (8.3), one therefore finds \(\delta V_{B}\) as
Assuming \(\beta^{{\prime }} R1(V_{\text{DD}} - V_{\text{tune}} - V_{T}^{{\prime }} ) \gg 1,\) (8.4) reduces to
The threshold voltage variation in M1 due to body voltage fluctuation resulting from the mobility degradation in M2 is approximately as
The drain current fluctuation subject to key transistor parametric drifts (\(\delta \beta\) and \(\delta V_{T}\)) is given by
In the derivation of \(\frac{{\partial I_{D} }}{\partial \beta }\) and \(\frac{{\partial I_{D} }}{{\partial V_{T} }},\) a simple drain current equation \(\left( {I_{D} \approx \frac{\beta }{2}(V_{\text{GS}} - V_{T} )^{2} } \right)\) is used. The drain current variation is thus obtained as
Using (8.7), (8.8), and (8.9) one obtains
Combining (8.2), (8.8), and (8.10), the fluctuation of drain current of M1 is expressed below
Note that the variation \(\delta \beta\) reflects the fluctuation resulting from the electron mobility degradation of M1. \(\delta \beta^{{\prime }}\)represents the fluctuation caused by the electron mobility degradation of M2. The reduction of M1’s mobility will decrease the drain current in M1, while the reduction of M2’s mobility will increase the drain current in M1. To maximize the canceling effect, larger value of R1 as well as larger size of M2 are expected.
8.1.1 Tuning for Variability
The V T shift of M1 due to V tune change is described as follows. From (8.1) the body voltage values corresponding to the two different tuning voltages are determined by the equations in (8.12) and (8.13). Here, the VT of M2 is supposed to be constant.
where \(V_{\text{tune1}}\) and \(V_{\text{tune2}}\) represent the two different tuning voltages.
The threshold voltage of M1 under the two different V tune voltages can be written as:
The difference between two tuning voltage is marked as \({\Delta } V_{T}\)
Combining (8.14) to (8.16), the sensitivity of V T in M1 due to the tuning voltage of the circuit is derived as
A complete expression of (8.17) is complicated when substituting \(V_{B1}\) and \(V_{B2}\) with (8.12) and (8.13). Using (8.17) and the PTM 65 nm nMOSFET model parameters, the relationship between the threshold voltage and tuning voltage is calculated and plotted in Fig. 8.2.
The V T of M1 decreases linearly from 4.05 to −4.76 % as Vtune increases from −0.2 to 0.2 V. This property can serve as post-fabrication calibration to compensate for the V T deviation of M1 due to process variability.
Both the fabrication process-induced fluctuation and time-dependent degradation cause the MOSFET model parameter shifts. V T is the most significant parameter for the MOSFET suffering from variability and reliability degradations. Static post-fabrication calibration and dynamic V T adjustment are considered using the resilient biasing design. Figure 8.3 shows a 24 GHz class-AB PA topology. The resilient biasing is circled in this plot. The output matching network is tuned using ADS load-pull instrument to obtain the optimum value. The 65 nm NMOS transistors are modeled by the PTM equivalent BSIM4 model card. The transistor sizes, capacitor and inductor values, and supply voltage are given in this figure.
8.1.2 ADS Monte Carlo Simulation
The simulated P sat, and ηadd of the PA without resilient biasing are 10.28 dBm, 10.96 dBm, and 34.25 %, while the corresponding values of the resilient design shown reach 10.90 dBm, 11.22 dBm, and 34.59 %, respectively. The matching network remains the same between the two PA schematics. Figure 8.4 shows 20 overlapping samples of the output power and power-added efficiency variations due to process fluctuation [1]. It is observed from the Monte Carlo simulations that a 10 % of V T spread (STD/Mean) will lead to 1.83 % P sat spread and 1.05 % ηadd spread. It is also seen from the simulation that the ±0.2 V and ±0.25 V V tune correspond to the ±1.63 % and ±2.04 % P sat deviation, respectively. So the spread fits into the compensation range of the ±0.25 V V tune for post-process calibration.
The power amplifiers with and without resilient biasing technique are compared. Figure 8.5a shows normalized power-added efficiency to normalized threshold voltage variation. The resilient biasing reduces the sensitivity of normalized power-added efficiency significantly. For the normalized P sat and P 1dB variations shown in Fig. 8.5b, the resilient biasing design reduces the sensitivity of P sat and P 1dB against the threshold voltage shift dramatically, especially for the output power at the 1dB compression point (e.g., ∆P 1dB/P 1dB reduces from about −12 to −4 % at ∆V T /V T = 21 %). So for reliability degradation induced dynamic VT shift, the resilient biasing design helps improve the reliability of the PA by cutting the sensitivity by three to four times for the normalized output power at 1dB compression point and power-added efficiency.
The reliability degradation also reduces the electron mobility, which is another important parameter for drain current characteristic. Figure 8.6a shows normalized power-added efficiency versus normalized electron mobility reduction for PA with and without resilient biasing design. The resilient biasing scheme reduces the sensitivity of normalized power-added efficiency by 25 %. Figure 8.6b presents the normalized P sat and P 1dB variations versus normalized mobility shift. The resilient design reduces the sensitivity of P sat and P 1dB by 14.3 and 26.9 %, respectively. The resilient biasing design is obviously successful in reducing the power amplifier sensitivity against process variations and reliability degradations.
8.2 Use of Current Source for Sensing Variability
An on-chip variability sensor using current source [2] is studied to detect process, supply voltage, and temperature (PVT) variations or even reliability degradation stemming from hot electron effect. The PVT variations yield a control signal from the designed current source. In Fig. 8.7, the current source circuit is made of n-channel transistors M1, M2, and M3. The transistor M1 and M2 have the same width and length and two times width of transistor M3. On the right branch in Fig. 8.1, a resistor R is used to set a control voltage V Ctrl. The reference current I ref is dependent on the PVT fluctuations. The Kirchhoff’s current law to solve for V Ctrl is given by
and I ref is the reference current and can be obtained as [3]
where K n is the transconductance factor (K n = µ n ε ox /t ox ). Subscript 1 and 3 represent the transistor M1 and M3, respectively.
The V Ctrl shift because of supply voltage variation is derived using (8.18) and (8.19)
The V Ctrl shift due to mobility fluctuation is given by
Furthermore, the V Ctrl shift resulting from fluctuation of the threshold voltage from M1 or M3 is
Combing (8.20)–(8.22) yields the overall V Ctrl variation as follows:
8.3 Tuning for Variability
The sensitivity of the class AB PA is evaluated using Fig. 8.8. The PVT variations change behaviors of the PA and also degrade the performance. In the simulation, the PVT variations are given to the PA circuit. Adaptive body biasing is used to find a range of body biasing voltage (V ABB) to compensate each variation.
V Ctrl signal is efficiently transformed to an optimal body bias signal for power amplifier application. From a range of V ABB, an operational amplifier is used as a voltage shifter and amplifier to adjust the V Ctrl to meet a required V ABB. Choosing appropriate size of resistor R 1 and R 2 using (8.31) provides a matched V ABB for PA. For example, for a reference voltage (V ref) of 0.4 V, R 1 and R 2 can be designed at 500 Ω and 1500 Ω, respectively. (See Fig. 8.9)
Due to the body effect, the threshold voltage of the power amplifier transistor is described by the following expression
The threshold voltage shift of the PA transistor is modeled by the fluctuation of V T0 and V ABB as
From (8.24), the V ABB shift is given by
Thus, the threshold voltage shift of the power amplifier input transistor due to PVT variations are summed as
The drain current fluctuation subjects to key transistor parametric drifts Δµ n , ΔV GS and ΔV T can be modeled as
Assume the VGS shift is proportional to the fluctuation of V DD.
where α is a fitting parameter.
Using (8.26)–(8.30) the fluctuation of drain current normalized to its fresh current is expressed as follows:
In the above equation, the terms beyond ΔV T0 represent the V DD , mobility, and threshold voltage compensation effects. The normalized output power degradation is related to the normalized drain current degradation as follows [4]:
8.3.1 Circuit Simulation Results
The power amplifier with the current source compensation technique is compared with the PA without compensation using ADS simulation. For the process variation effect, the output power is evaluated against threshold voltage and mobility variations as shown in Figs. 8.10 and 8.11. It is clear from Figs. 8.10 and 8.11 that the power amplifier with adaptive body bias is more robust against threshold voltage variation (see Fig. 8.10) and mobility fluctuation (Fig. 8.11).
For the process variation effect, the output power of the PA has also been evaluated using different process corner models due to inter-die variations. The simulation result of the fast–fast, slow–slow, and nominal–nominal models is shown in Fig. 8.12. Clearly, the PA using the adaptive body bias compensation exhibits better stability against process variation effect.
Figures 8.13 and 8.14 show the output power of the power amplifier versus temperature variation and supply voltage change, respectively. As seen in Figs. 8.13 and 8.14 the output power of the PA using the adaptive body bias compensation technique demonstrates less sensitivity over temperature and V DD variations.
In addition, the power-added efficiency of the power amplifier with or without adaptive body bias compensation is examined against semiconductor process variations effects. Figures 8.15 and 8.16 display the improvement of power-added efficiency of the PA with ABB compensation over that without adaptive body bias for the threshold voltage shift (see Fig. 8.15) and mobility variation (see Fig. 8.16).
For the process corner models the power-added efficiency of the PA with ABB compensation shows less process sensitivity, as evidenced by the plot in Fig. 8.17.
Then, the power-added efficiency is compared against temperature and supply voltage variations. The power-added efficiency is getting better for the PA with ABB compensation as shown in Figs. 8.18 and 8.19.
References
Liu Y, Yuan JS (2011) CMOS RF power amplifier variability and reliability resilience biasing design and analysis. IEEE Trans Electron Devices 540–546
Pappu AM, Zhang X, Harrison AV, Apsel AB (2007) Process invariant current source design: Methodology and examples. IEEE J Solid-State Circuits 2293–2302
Yuan JS, Kritchanchai E (2013) Power amplifier resilient design for process, voltage, and temperature variations. In: Microelectronics reliability, pp 856–860
Quemerais T, Moquillon L, Huard V, Fournier J-M, Benech P, Corrao N, Mescot X (2010) Hot-carrier stress effect on a CMOS 65-nm 60-GHz one-stage power amplifier. IEEE Electron Device Lett 927–929
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Yuan, JS. (2016). Power Amplifier Design for Variability. In: CMOS RF Circuit Design for Reliability and Variability. SpringerBriefs in Applied Sciences and Technology(). Springer, Singapore. https://doi.org/10.1007/978-981-10-0884-9_8
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DOI: https://doi.org/10.1007/978-981-10-0884-9_8
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