LNA Design for Variability

Abstract

This chapter discusses the low-noise amplifier process variation effect. Extensive analytical equations are derived. The adaptive substrate bias technique to reduce the process variation effect on the low-noise amplifier is presented.

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Nanoscale CMOS transistors are more susceptible to long-term electrical stress-induced reliability degradations. When those devices are used for radio frequency (RF) or microwave applications, a single transistor aging can lead to significant circuit performance degradation resulting from threshold voltage V _T shift and electron mobility μ _n drift. In addition, process variations in nanoscale transistors are another major concern in today’s circuit design. Random dopant fluctuation, oxide thickness variation, and line edge roughness result in significant threshold voltage variation of CMOS transistors at sub-20 nm technology node and beyond [1].

The design for reliability (DFR) method intends to reduce the circuit over-design, while increasing its robustness against long-term aging. Here, the adaptive substrate (or body) bias scheme is described for the LNA design for process variability and circuit reliability [2]. Figure 7.1 shows a simple adaptive body bias scheme. The adaptive body bias technique dynamically adjusts the substrate bias of the input transistor M1 to reduce impact of process variations and device aging on circuit performance.

Fig. 7.1

Adaptive body bias design (© IEEE)

7.1 Analytical Model and Equations

As seen in Fig. 7.1, the right side of the circuit controls the substrate voltage of the main transistor. By designing similar drain-source voltage and gate-source voltage for M1 and M2, both the main transistor and bias transistor may subject to similar aging effect such as threshold voltage shift and electron mobility degradation. To account for possible different stress conditions between M1 and M2, mismatch between the main transistor aging and bias transistor aging is also considered. In Fig. 7.1, when the V _T of M2 increases, the current I _R1 decreases. The reduced I _R1 results in an increased body voltage V _B . The increase in V _B of M1 will decrease the threshold voltage of the input transistor due to source-body effect. Thus, this compensates the change of V _T from device aging. Similarly, the decrease in electron mobility, which decreases the drain current of the MOS transistor, will increase V _B of M1. The drain current of M1 is also compensated. Examining Fig. 7.1, the KCL equation to solve for V _B is given as

$$I_{\text{R1}} R 1+ V_{B} = V_{\text{DD}}$$

(7.1)

$$I_{R 1} \approx \frac{{\beta^{{\prime }} }}{2}\left( {V_{B} - V_{\text{tune}} - V_{T}^{{\prime }} } \right)^{2}$$

(7.2)

where V _tune is the tuning voltage, $\beta^{{\prime }}$ is the transistor parameter ($\beta^{{\prime }} = \mu_{n} C_{\text{ox}} W/L$) of M2, and $V_{T}^{{\prime }}$ is the threshold voltage of M2. Note that V _tune can be used to adjust the stress effect on M2 due to change of effective drain-source and gate-source voltages. Combining (7.1) and (7.2) and solving for V _B one obtains

$$V_{B} = V_{\text{tune}} + V_{T}^{{\prime }} + \frac{{\sqrt {2\beta^{{\prime }} R 1(V_{\text{DD}} - V_{\text{tune}} - V_{T}^{{\prime }} ) + 1} - 1}}{{\beta^{{\prime }} R 1}}.$$

(7.3)

Using (7.3) the $\delta V_{T}^{{\prime }}$ variation yields the body voltage fluctuation as follows:

$$\begin{aligned} \delta V_{B} & \approx \frac{{\partial V_{B} }}{{\partial V_{T}^{\prime} }}\delta V_{T}^{{\prime }} \\ & = (1 + \frac{{ - 2\beta^{\prime} R1}}{{2\beta^{{\prime }} R 1\sqrt {2\beta^{{\prime }} R1(V_{\text{DD}} - V_{\text{tune}} - V_{T}^{{\prime }} ) + 1} }})\delta V_{T}^{{\prime }} \\ & = \delta V_{T}^{{\prime }} - \frac{{\delta V_{T}^{{\prime }} }}{{\sqrt {2\beta^{{\prime }} R1(V_{\text{DD}} - V_{\text{tune}} - V_{T}^{{\prime }} ) + 1} }} \\ \end{aligned}$$

(7.4)

Due to the body effect, the V _T of M1 can be described by the following expression

$$V_{T} = V_{T0} + \gamma_{b} (\sqrt {2\phi_{F} - V_{B} } - \sqrt {2\phi_{F} } )$$

(7.5)

where γ _b is the body effect factor and ϕ _F represents the Fermi potential. The V _T shift of M1 due to degradation of M1 and M2 is thus modeled by the fluctuation of $V_{T0}$ and $V_{B}$ as

$$\delta V_{T} = \delta V_{T0} - \frac{{\gamma_{b} \delta V_{B} }}{{2\sqrt {2\phi_{\text{FP}} - V_{B} } }}.$$

(7.6)

Combining (7.4) and (7.6) yields the V _T variation

$$\delta V_{T} = \delta V_{T0} - \frac{{\gamma_{b} \delta V_{T}^{{\prime }} }}{{2\sqrt {2\phi_{\text{FP}} - V_{B} } }}(1 - \frac{1}{{\sqrt {2\beta^{{\prime }} R1(V_{\text{DD}} - V_{\text{tune}} - V_{T}^{{\prime }} ) + 1} }}).$$

(7.7)

The first term in (7.7) represents the threshold voltage shift of M1, while the second term in (7.7) accomplishes the canceling effect resulting from the combination of threshold voltage shift of M2 and the body bias circuit of M1. Thus, the overall V _T shift of M1 due to process variation and reliability degradation is reduced. The level of reduction is related to $\delta V_{T}^{{\prime }}$ of M2, body effect coefficient $\gamma_{b}$, M2 transistor $\beta^{{\prime }}$, and resistor R1. To achieve an optimal resilience to the variability and reliability, it is better to choose larger R1 and wider channel width of M2.

The noise factor is a measure of the degradation in signal-to-noise ratio that a system introduces. Equation (7.8) expresses the noise factor defined in the two-port network with noise sources and a noiseless circuit [3]. The noise figure is the noise factor expressed in decibels. The noise factor is written as

$$F = \frac{{\overline{{i_{s}^{2} }} + \overline{{\left| {i_{n} + (Y_{c} + Y_{s} )e_{n} } \right|^{2} }} }}{{\overline{{i_{s}^{2} }} }} = 1 + \frac{{\overline{{i_{n}^{2} }} + |Y_{c} + Y_{s} |^{2} \overline{{e_{n}^{2} }} }}{{\overline{{i_{s}^{2} }} }}$$

(7.8)

where i _s is the noise current from the source, Y _s is the source admittance, i _n is the device noise current, e _n is the device noise voltage, and Y _c is the correlation admittance.

For n-channel MOS transistor M1 at high frequency, the small-signal equivalent circuit model with noise currents is displayed in Fig. 7.2. The 1/f flicker noise is ignored at high frequency. The nMOSFET consists of the drain current noise and gate noise. The drain current noise and gate noise in Fig. 2 can be written as [4, 5]

Fig. 7.2

nMOSFET noise model

$$\overline{{i_{{{\text{nd}}1}}^{2} }} = 4kT\gamma_{1} g_{d01}\Delta f$$

(7.9)

$$\overline{{i_{{{\text{ng}}1}}^{2} }} = 4kT\theta \frac{{\omega^{2} C_{{{\text{gs}}1}}^{2} }}{{5g_{d01} }}\Delta f$$

(7.10)

where k is the Boltzmanns’ constant, T is the absolute temperature, ω is the radian frequency, g _d01 is the output conductance of M1, C _gs1 is the gate-source capacitance of M1, γ₁ = 2/3 for long channel MOSFET and can be 2–3 times larger in short-channel devices, and θ is the gate noise coefficient.

For the DFR biasing circuit, the drain of nMOSFET M2 is shorted to its gate as seen in Fig. 7.3. Thus, the noise looking into the node B consists of the two noise sources R1 and M2 drain current noise. The resistor R1 thermal noise and M2 drain current noise are modeled as:

Fig. 7.3

DFR biasing circuit noise model (© IEEE)

$$\overline{{i_{R1}^{2} }} = 4kT\frac{1}{R1}\Delta f$$

(7.11)

$$\overline{{i_{{{\text{nd}}2}}^{2} }} = 4kT\gamma_{2} g_{d02}\Delta f$$

(7.12)

where g _d02 is the output conductance of M2. Thus, the total mean squared noise voltage is

$$\overline{{e_{B1}^{2} }} = 4kT\frac{R1}{{1 + R1\gamma_{2} g_{d02} }}\Delta f.$$

(7.13)

The reflected drain current noise due to noise voltage in the body node is determined by a ratio of body transconductance g _mb1.

$$\overline{{i_{nB1}^{2} }} = 4kT\frac{R1}{{1 + R1\gamma_{2} g_{d02} }}g_{{{\text{mb}}1}}^{2}\Delta f.$$

(7.14)

Due to the body effect of M1, the drain current noise is a combination of noise originated from the drain current and reflected from the body node B.

$$\overline{{i_{n1}^{2} }} = \overline{{i_{{{\text{nB}}1}}^{2} }} + \overline{{i_{{{\text{nd}}1}}^{2} }} = 4kT\left[ {\frac{R1}{{1 + R1\gamma_{2} g_{d02} }}g_{{{\text{mb}}1}}^{2} + \gamma_{1} g_{d01} } \right]\Delta f$$

(7.15)

The noise can be reflected back to the input gate of M1 by g _m1.

$$\overline{{e_{n1}^{2} }} = \frac{{\overline{{i_{n1}^{2} }} }}{{g_{m1}^{2} }} = 4kT\left[ {\frac{R1}{{1 + R1\gamma_{2} g_{d02} }}\frac{{g_{{{\text{mb}}1}}^{2} }}{{g_{m1}^{2} }} + \frac{{\gamma_{1} g_{d01} }}{{g_{m1}^{2} }}} \right]\Delta f$$

(7.16)

The equivalent input noise voltage is completely correlated with the drain current noise. Thus, the noise resistance is

$$R_{n1} = \frac{{\overline{{e_{n1}^{2} }} }}{{4kT\Delta f}} = \frac{R1}{{1 + R1\gamma_{2} g_{d02} }}\frac{{g_{{{\text{mb}}1}}^{2} }}{{g_{m1}^{2} }} + \frac{{\gamma_{1} g_{d01} }}{{g_{m1}^{2} }}$$

(7.17)

The equivalent input noise voltage generator by itself does not fully account for the drain current noise. A noisy drain current also flows when the input is open circuited. Under this condition, the equivalent input voltage is obtained from dividing the drain current noise by the transconductance. When multiplying the input admittance, $\overline{{e_{n1}^{2} }}$ gives an equivalent input current noise as

$$\overline{{i_{n1'}^{2} }} = \overline{{e_{n1}^{2} }} (j\omega C_{{{\text{gs}}1}} )^{2}$$

(7.18)

Here, it is assumed that the input admittance of M1 is purely capacitive, which is good approximation when the operating frequency is below the cutoff frequency.

The drain noise and gate noise of M1 are correlated with a correlation coefficient c ₁ defined as

$$c_{1} = \frac{{\overline{{i_{{{\text{ng}}1}}^{{}} \cdot i_{n1}^{*} }} }}{{\sqrt {\overline{{i_{{{\text{ng}}1}}^{2} \cdot i_{n1}^{2} }} } }}$$

(7.19)

The total equivalent input current noise consists of the reflected drain noise and the induced gate current noise. The induced gate noise current itself has two parts. One part, i _ngc1, is fully correlated with the drain current noise of M1, while the other, i _ngu1, is uncorrelated with the drain current noise. The correlation admittance is expressed as follows:

$$\begin{aligned} Y_{c} & = \frac{{i_{n1'} + i_{{{\text{ngc}}1}} }}{{e_{n1} }} = j\omega C_{{{\text{gs}}1}} + \frac{{i_{{{\text{ngc}}1}} }}{{e_{n1} }} \\ & = j\omega C_{{{\text{gs}}1}} + g_{m1} \frac{{i_{{{\text{ngc}}1}} }}{{i_{n1} }} \\ \end{aligned}$$

(7.20)

The last term must be manipulated in terms of cross-correlations by multiplying both numerator and denominator by the conjugate of the drain current noise:

$$g_{m1} \frac{{i_{{{\text{ngc}}1}} }}{{i_{n1} }} = g_{m1} \frac{{\overline{{i_{{{\text{ngc}}1}} \cdot i_{n1}^{*} }} }}{{\overline{{i_{n1} \cdot i_{n1}^{*} }} }} = g_{m1} \frac{{\overline{{i_{{{\text{ng}}1}} \cdot i_{n1}^{*} }} }}{{\overline{{i_{n1}^{2} }} }}$$

(7.21)

Using the above equation, the correlation admittance can be rewritten as

$$\begin{aligned} Y_{c} & = j\omega C_{{{\text{gs}}1}} + g_{m1} \frac{{\overline{{i_{{{\text{ng}}1}} \cdot i_{n1}^{*} }} }}{{\overline{{i_{n1}^{2} }} }} \\ & = j\omega C_{{{\text{gs}}1}} + g_{m1} \frac{{\overline{{i_{{{\text{ng}}1}} \cdot i_{n1}^{*} }} }}{{\sqrt {\overline{{i_{{{\text{ng}}1}}^{2} }} } \sqrt {\overline{{i_{n1}^{2} }} } }}\sqrt {\frac{{\overline{{i_{{{\text{ng}}1}}^{2} }} }}{{\overline{{i_{n1}^{2} }} }}} = j\omega C_{{{\text{gs}}1}} + g_{m1} c_{1} \sqrt {\frac{{\overline{{i_{{{\text{ng}}1}}^{2} }} }}{{\overline{{i_{n1}^{2} }} }}} \\ \end{aligned}$$

(7.22)

Inserting (7.10) and (7.15) into (7.22) yields the expression for Y _c . Note that the correlation coefficient c ₁ is purely imaginary [3]. Thus, G _c (the real part of Y _c ) equals zero. Using the definition of the correlation coefficient, the expression of the gate induced noise is written as

$$\overline{{i_{{{\text{ng}}1}}^{2} }} = \overline{{(i_{{{\text{ngc}}1}} + i_{{{\text{ngu}}1}} )^{2} }} = 4kT\Delta f\left( {\frac{{\uptheta \upomega ^{2} C_{{{\text{gs}}1}}^{2} |c_{1} |^{2} }}{{5g_{d01} }} + \frac{{\uptheta \upomega ^{2} C_{{{\text{gs}}1}}^{2} (1 - |c_{1} |^{2} )}}{{5g_{d01} }}} \right).$$

(7.23)

Thus, the uncorrelated portion of the gate noise is

$$G_{u1} = \frac{{\overline{{i_{u1}^{2} }} }}{{4kT\Delta f}} = \frac{{\uptheta \upomega ^{2} C_{{{\text{gs}}1}}^{2} (1 - |c_{1} |^{2} )}}{{5g_{d01} }}.$$

(7.24)

The minimum noise figure is given by

$$\begin{aligned} F_{\hbox{min} } & = 1 + 2R_{n1} \left[ {G_{\text{opt}} + G_{c} } \right] \approx 1 + 2R_{n1} \sqrt {\frac{{G_{u1} }}{{R_{n1} }}} \\ & = 1 + \frac{2}{\sqrt 5 }\frac{{\omega C_{{{\text{gs}}1}} }}{{g_{m1} }}\sqrt {\uptheta(1 - |c|^{2} )\left[ {\frac{{R1g_{{{\text{mb}}1}}^{2} }}{{(1 + R1\upgamma_{2} g_{d02} )g_{d01} }} +\upgamma_{1} } \right]} \\ \end{aligned}$$

(7.25)

Using (7.25) the minimum noise figure fluctuation is derived as

$$\begin{aligned}\Delta F_{ \hbox{min} } & = - \frac{2}{\sqrt 5 }\frac{{\upomega\,C_{{{\text{gs}}1}} }}{{g_{m1}^{2} }}\sqrt {\uptheta(1 - |c|^{2} )\left[ {\frac{{R1g_{{{\text{mb}}1}}^{2} }}{{(1 + R1\upgamma_{2} g_{d02} )g_{d01} }} +\upgamma_{1} } \right]}\Delta g_{m1} \\ & \quad + \frac{2}{\sqrt 5 }\frac{{\upomega\,C_{{{\text{gs}}1}} }}{{g_{m1} }}\frac{{\uptheta(1 - |c|^{2} )R1g_{{{\text{mb}}1}} }}{{(1 + R1\upgamma_{2} g_{d02} )g_{d01} \sqrt {\uptheta(1 - |c|^{2} )\left[ {\frac{{R1g_{{{\text{mb}}1}}^{2} }}{{(1 + R1\upgamma_{2} g_{d02} )g_{d01} }} +\upgamma_{1} } \right]} }}\Delta g_{{{\text{mb}}1}} \\ & \quad - \frac{1}{\sqrt 5 }\frac{{\upomega\,C_{{{\text{gs}}1}} }}{{g_{m1} }}\frac{{\uptheta(1 - |c|^{2} )R1g_{{{\text{mb}}1}}^{2} }}{{(1 + R1\upgamma_{2} g_{d02} )g_{d01}^{2} \sqrt {\uptheta(1 - |c|^{2} )\left[ {\frac{{R1g_{{{\text{mb}}1}}^{2} }}{{(1 + R1\upgamma_{2} g_{d02} )g_{d01} }} +\upgamma_{1} } \right]} }}\Delta g_{d01} \\ & \quad - \frac{1}{\sqrt 5 }\frac{{\upomega\,C_{{{\text{gs}}1}} }}{{g_{m1} }}\frac{{\theta (1 - |c|^{2} )R1^{2} g_{{{\text{mb}}1}}^{2} \gamma_{2} }}{{(1 + R1\upgamma_{2} g_{d02} )^{2} g_{d01} \sqrt {\uptheta(1 - |c|^{2} )\left[ {\frac{{R1g_{{{\text{mb}}1}}^{2} }}{{(1 + R1\upgamma_{2} g_{d02} )g_{d01} }} +\upgamma_{1} } \right]} }}\Delta g_{d02} \\ \end{aligned}$$

(7.26)

In (7.26), the second term leads to the reduction of minimum noise figure sensitivity due to the body effect of MOSFET M1.

Small-signal gain S ₂₁ is related to the transconductance and gate-drain capacitance of M1. A detailed derivation of small-signal model is given in the following.

$$S_{21} = \frac{{ - 2Y_{21} \sqrt {Z_{01} Z_{02} } }}{{\Delta _{1} }}$$

(7.27)

$$\Delta _{1} = (1 + Y_{11} Z_{01} )(1 + Y_{22} Z_{02} ) - Y_{21} Z_{01} Y_{12} Z_{02}$$

(7.28)

In the following discussion, one will see how Y ₂₁ fluctuates due to transconductance variation. Firstly, high frequency small-signal model for nMOSFET is shown in Fig. 7.4a. When the node D is tied to the ground terminal S, Fig. 7.4a reduces to Fig. 7.4b.

Fig. 7.4

a High frequency small-signal model of nMOSFET; b simplified equivalent circuit for Y ₂₁ derivation

Y ₂₁ for single nMOSFET without body effect is derived from Fig. 7.4b. In Fig. 7.4, V ₁ refers to V _gs in terminal 1 (between G and S) and V ₂ refers to V _gd in terminal 2 (between D and S). Using Fig. 7.4b Y ₂₁ without body biasing is given by

$$Y_{21} (f) = \frac{{i_{2} (f)}}{{V_{1} (f)}}|_{{V_{2} = 0}} = - j\omega C_{\text{gd}} + g_{m}$$

(7.29)

Thus, the transconductance fluctuation results in Y ₂₁ variation:

$$\Delta Y_{21} (f) =\Delta g_{m}$$

(7.30)

Figure 7.5a shows small-signal model for nMOSFET with body bias terminal. When D of M1 is tied to ground with S of both M1 and M2 in the substrate biasing circuit in Fig. 7.1, a simplified equivalent circuit model is displayed in Fig. 7.5b. Using Fig. 7.5b, one can write the current i ₂

Fig. 7.5

a High frequency small-signal model of nMOSFET with body terminal and b small-signal model for Y ₂₁ derivation including substrate biasing circuit (© IEEE)

$$i_{2} = g_{m} V_{1} + g_{{{\text{mb}}1}} V_{2} - V_{1} j\omega C_{{{\text{gd}}1}} .$$

(7.31)

At the node B in Fig. 7.5b, the KCL equation results in

$$V_{2} j\omega (C_{{{\text{sb}}1}} + C_{{{\text{db}}1}} ) + V_{2} j\omega (C_{{{\text{gs}}2}} + C_{{{\text{ds}}2}} ) + g_{m2} V_{2} + \frac{{V_{2} }}{{R1||r_{o2} }} = (V_{1} - V_{2} )j\omega C_{{{\text{gb}}1}}$$

(7.32)

Combining (7.31) and (7.32), Y ₂₁ is obtained:

$$Y_{21} (f) = \frac{{i_{2} (f)}}{{V_{1} (f)}}|_{{V_{2}^{{\prime }} = 0}} = - j\omega C_{{{\text{gd}}1}} + g_{m1} + \frac{{j\omega C_{{{\text{gb}}1}} g_{{{\text{mb}}1}} }}{{j\omega C_{\text{tot}} + g_{m2} + \tfrac{1}{{R1||r_{o2} }}}}$$

(7.33)

where $C_{\text{tot}} = C_{{{\text{sb}}1}} + C_{{{\text{db}}1}} + C_{{{\text{gs}}2}} + C_{{{\text{ds}}2}}$.

Note that $V_{2}^{{\prime }}$ in (7.33) represents what V ₂ means in (7.29).

From (7.33) one can derive the fluctuation of Y ₂₁ as a function of g _m1, g _mb1, and g _m2 as

$$\Delta Y_{21} (f) =\Delta g_{m1} - \frac{{j\omega C_{{{\text{gb}}1}} g_{{{\text{mb}}1}} }}{{(j\omega C_{\text{tot}} + g_{m2} + \tfrac{1}{{R1||r_{o2} }})^{2} }}\Delta g_{m2} + \frac{{j\omega C_{{{\text{gb}}1}} }}{{j\omega C_{\text{tot}} + g_{m2} + \tfrac{1}{{R1||r_{o2} }}}}\Delta g_{{{\text{mb}}1}}$$

(7.34)

The second term in (7.34) will reduce Y ₂₁ sensitivity due to M2 in the DFR design. However, the third term in (7.34) due to the body effect of M1 will increase the fluctuation of Y ₂₁. Thus, the transconductance of M2 helps reduce Y ₂₁ sensitivity, while the body transconductance of M1 may degrade Y ₂₁ sensitivity. Examining (7.26) and (7.34) together, the best sensitivity of noise figure and small-signal gain subject to body bias cannot be obtained simultaneously.

7.2 LNA Variability

A narrow-band cascode LNA designed at 24 GHz with adaptive body biasing is shown in Fig. 7.6. The main input transistor (M1) is connected with source degenerated inductor for better input matching and noise reduction. The cascode transistor (M3) provides the output to input isolation. All n-channel transistors are modeled using the PTM 65 nm technology [6]. The inductor values, MOS channel widths, and R1 are given in Fig. 7.6. V _DD = 1.0 V, V _bias = 0.7 V, and R _bias = 5 kΩ. The NF, NF_min, and S ₂₁ of the LNA without resilient biasing are 1.414, 1.226, and 12.124 dB at 24 GHz, while the corresponding values of the resilient design are 1.369, 1.327, and 11.531 dB, respectively.

Fig. 7.6

A cascode low-noise amplifier with adaptive body bias (© IEEE)

Figures 7.7 and 7.8 show ADS Monte Carlo simulation [7] of the NF, NF_min, and S ₂₁ sensitivity subject to process variability. Monte Carlo simulation results demonstrate that a 10 % of V _T spread (STD/Mean) for the LNA without substrate biasing scheme yields 6.63 % NF spread and 5.58 % NF_min spread. A 10 % of V _T spread (STD/Mean) of the LNA with adaptive substrate biasing gives 3.85 % NF spread and 3.52 % NF_min spread. Comparing Figs. 7.7 and 7.8, it is apparent that the adaptive body biasing reduces the process variation effect significantly. It is also obtained that the ±0.2 V V _tune corresponds to the +5.41 to −4.16 % NF deviation and +5.20 to −3.92 % NF_min deviation. This spread fits into the compensation range for post-process V _tune calibration.

Fig. 7.7

Monte Carlo simulation of the LNA without substrate bias (© IEEE)

Fig. 7.8

Monte Carlo simulation of the LNA with the body bias technique (© IEEE)

The reliability effect such as threshold voltage shift and mobility degradation on the LNA with or without adaptive substrate biasing is further evaluated. Figure 7.9 shows the normalized NF and NF_min to normalized threshold voltage shift for the original LNA compared to the LNA with adaptive bias design at different aging conditions. Since both drain-source voltage of main transistor M1 and substrate bias transistor M2 have the same designed drain-source voltage and similar gate-source voltage stress, M1 and M2 may have similar aging effect. However, different aging rates on M1 and M2 are also examined to account for a wide range of stress conditions. As seen in Fig. 7.9, the adaptive body biasing reduces the variation of normalized NF and NF_min significantly. In Fig. 7.9, the solid line represents the LNA without adaptive body bias and the solid lines with symbols represent the LNA with adaptive body bias, while the line with triangles corresponds to the M2 transistor’s aging effect (threshold voltage shift or mobility degradation) is half of that of M1’s, the line with empty circles is when both M1 and M2 have an identical aging degradation, and the line with inverse triangles represents that M2’s aging effect is twice of M1’s. It is seen from Fig. 7.9 that the LNA with resilient substrate bias scheme reduces the noise figure and minimum noise figure sensitivity significantly even when the M2’s aging is different from that of M1’s. It is interesting to point out that larger M2 aging in fact reduces the noise figure sensitivity even further. This is due to an additional $\delta V_{T}^{{\prime }}$ in M2 to compensate the threshold voltage shift δV _T0 in M1 as indicated in Eq. (7.7).

Fig. 7.9

Normalized a NF and b NF_min versus normalized V _T shift of the LNA without adaptive body bias compared to that with adaptive body bias (© IEEE)

Figure 7.10 shows the normalized NF and NF_min variation versus normalized mobility degradation for the original LNA compared to the LNA with adaptive body bias at different mobility degradations. The line and symbol representations are the same as those defined in Fig. 7.9. The adaptive body biasing reduces the sensitivity of normalized NF and NF_min against mobility degradation also, though its effect is not as large as that in threshold voltage shift. With larger aging degradation on M2, the resilient biasing effect is further improved slightly.

Fig. 7.10

Normalized a NF and b NF_min versus normalized μ _n degradation of the LNA without adaptive bias compared to the LNA with adaptive body bias (© IEEE)

The small-signal gain sensitivity versus V _T shift considering different aging is displayed in Fig. 7.11. Again, in this figure the solid line represents the LNA without adaptive body bias and the solid lines with symbols represent the LNA with adaptive body bias, while the triangles correspond to the M2 transistor’s aging effect is half of that of M1’s, the empty circles are when both M1 and M2 have the same aging degradation, and the inverse triangles represent M2’s aging effect twice of M1’s. In Fig. 7.11, the adaptive body biasing does not help reduce S ₂₁ sensitivity much as implied by Eq. (7.34). Figure 7.12 shows the normalized S ₂₁ sensitivity versus mobility degradation for the LNA with or without adaptive bias scheme. The adaptive body biasing increases the S ₂₁ sensitivity slightly subject to electron mobility degradation.

Fig. 7.11

Small-signal gain sensitivity versus threshold voltage shift (© IEEE)

Fig. 7.12

Small-signal gain sensitivity versus electron mobility variation (© IEEE)