Keywords

1 Introduction

With the development of high performance and high speed integrated circuits, the thermal problem in chips has attracted increasing attention [1]. The chip, particularly the power-integrated circuit with large consumption, can be permanently damaged when the internal temperature exceeds the permitted temperature [2, 3].

In order to ensure the reliability and lifetime of the circuit, a thermal protection circuit should be integrated into the chip [4, 5]. In this paper, a novel thermal circuit is proposed which consists primarily of PTAT (Proportional To Absolute Temperature) circuit, BVR (Bandgap Voltage Reference) and voltage comparator; the block diagram is shown within the dotted box in Fig. 1. The PTAT circuit beside the power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detects the internal temperature of the chip and transfers it to V PTAT, which is proportional to the absolute temperature. When the temperature exceeds the acceptable temperature, the V OUT would shut off the power MOS via the comparison of V PTAT and V BVR.

Fig. 1
figure 1

Block diagram of the thermal protection circuit

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This work proposes a CMOS thermal protection circuit based on bandgap reference sources. The simulation results of the proposed circuit in a 0.25 μm CMOS process indicates that the circuit has the characteristics of simple structure, long-term stability, low power consumption and strong portability.

2 Circuit Design

The thermal protection circuit consists of four parts, including the PTAT & BVR circuit, temperature judgment circuit, bias circuit and startup circuit. The implemented structure is presented in Fig. 2.

Fig. 2
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Schematic of proposed thermal protection circuit

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2.1 PTAT & BVR Circuit

As the core of the circuit, the PTAT & BVR circuit consists of M11–M17, R0–R4, Q1–Q2, and op amp A1. In order to increase the stability of BVR, the circuit adopts a cascade current mirror [6]. Furthermore, the output of A1 is set as the bias voltage of the casecode to introduce negative feedback while M11 and M12 have the same ratio of width and length, namely, S11 = S12. Consequently, the current I 0 is given as [7]:

$$ I_{0} = I_{1} = \frac{\ln n}{{R_{1} }}V_{\text{T}} $$
(1)

where V T is the thermal voltage, n is the ratio between the emitter areas of the Q2 and Q1 bipolar transistors, V T = (k/q)T, k is Boltzmann’s constant, T is temperature and q is the conducted charge. V T with the temperature coefficient +0.085 mV/°C at room temperature is proportional to the absolute temperature T.

It is clear that I 0 is proportional to the temperature, so that I 0, I 1, I 2 are all positive temperature coefficients. The PTAT voltage is expressed as:

$$ V_{\text{PTAT}} = \ln n\frac{{S_{15} }}{{S_{11} }}\frac{{R_{3} }}{{R_{1} }}V_{\text{T}} $$
(2)

Equation (2) implies that V PTAT is entirely independent of the power supply and process parameters. The ratio of resistances is not sensitive to temperature changes when using the same type of resistance. Therefore, V PTAT has good linearity by ignoring the effects of resistance temperature characteristic.

V BVR is the terminal voltage of R 0, and can be expressed as:

$$ V_{\text{BVR}} = \ln n\frac{{R_{0} }}{{R_{1} }}V_{\text{T}} + V_{{{\text{EB}}2}} $$
(3)

At room temperature, V EB2 has a negative temperature coefficient of approximately ‒2.2 mV/°C. Therefore, V BVR has little dependence on the power supply and process parameters by adjusting the ratio of resistor R 0 and R 1. V BVR realizes zero temperature coefficient, namely, the BVR [8].

2.2 Temperature Judgment Circuit

The temperature judgment circuit consists of a comparator A2 and two inverters. A2 adopts the classical two-stage CMOS op amp using M18–M24 is shown in Fig. 3. The first stage consists of differential amplifier PMOS transistors; the second stage consists of a common-source MOSFET, and M18, M23 provide bias currents.

Fig. 3
figure 3

Comparator circuit

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The integrated op amp A1 has the same structure. A miller compensation is adopted by connecting capacitor C1 between the outputs of two stages in order to achieve adequate phase margin (>60°) to ensure A1 working steadily [9].

At room temperature, V PTAT is less than V BVR. While the temperature rises, V PTAT increases linearly until V PTAT = V BVR. And the comparator flips at the temperature, namely thermal temperature protection T + [10]. From this relationship, T + can be expressed as:

$$ T_{ + } = \frac{q}{k}\frac{{V_{\text{BVR}} }}{\ln n}\frac{{S_{11} }}{{S_{15} }}\frac{{R_{1} }}{{R_{3} }} $$
(4)

It is shown that T + is determined by the ratio of R1 and R3. Simultaneously, the temperature characteristic of V BVR also determines the stability of T +.

V OUT is the output of the comparator shaped by two-stage inverter. Once the temperature exceeds T +, V OUT jumps to low level which can shut off the power MOS and M17. Meanwhile, V PTAT is increased by the voltage drop of R4. Once V PTAT is equal to V BVR, V OUT turns to high level and opens power MOS and M17 at the threshold temperature named T _. The hysteresis temperature ΔT can be solved as follows:

$$ {\Delta} T = T_{ + } - T_{ - } = \frac{1}{{R_{3} /R_{4} + 1}}T_{ + } $$
(5)

It is clear that ΔT is determined by R4 at certain T +. The feedback circuit composed of M17 and R4 introduces a hysteresis comparison that the risk of thermal oscillation phenomena can be avoided at the temperature T + [11].

2.3 Bias Circuit and Startup Circuit

As shown in Fig. 2, the bias circuit supplies bias current Ib0 and the bias voltages Vb1 and Vb2 for op amp A1, A2, PTAT and BVR circuit.

Once the bias circuit is unable to provide necessary voltages and currents, the entire circuit will fail to work normally [12]. So the startup circuit which consists of M0–M4 and C0 is necessary. After power is on, C0 will be charged until point a exceeds the threshold voltage of M4. After M4 is on, V b1 decreases and point b increases. Then, M3 is on, point a is much less than the threshold voltage of M4, and M4 is reliably disconnected between the startup circuit and the bias circuit. Thus far, the entire startup process is complete and the bias circuit is in normal balance.

3 Simulation Results and Discussion

The proposed circuit is implemented in a CSMC 0.25 μm 2P5M process. As shown in Fig. 4, the layout covers an area of 0.27 × 0.29 mm2. V BVR and V out can be scanned in five parameters: tt, ss, ff, sf and fs corns from −40 to 150 °C. The results of Cadence Spectre simulation is shown in Figs. 5 and 6.

Fig. 4
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Layout of the circuit

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Fig. 5
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Simulated temperature characteristic of V BVR

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Fig. 6
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Simulated temperature characteristic of the output

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Figure 5 shows that V BVR is highly overlapping at all corners. This indicates that V BVR is little influenced by the corners, in favor of the stability of the temperature of thermal protection. It is observed that the center value of V BVR is 1.205 V with a temperature coefficient of 12.84 ppm/°C.

V OUT is scanned in double direction in the range of −40 to 150 °C, the simulation results in Fig. 6 indicate that the protection temperature is 130 °C, hysteresis temperature is 20 °C, and the proposed circuit exhibits good temperature sensitivity. The maximum temperature error is 1.4 °C in different process corners, and the hysteresis temperature approximation is 20 °C in the same corner. This validates the stability and reliability of the proposed circuit.

Furthermore, the same performance was recorded from other simulation results. Table 1 lists the performance comparison with other works. It is shown that the proposed circuit in this paper has several advantages, such as the largest temperature range and power supply range, smallest circuit area, and good temperature coefficient.

Table 1 Performance comparison with other works
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4 Conclusions

A novel thermal protection circuit based on CMOS BVR is proposed. Cadence Spectre simulation results show that the thermal protection temperature is approximately 130 °C, the temperature error is less than 1.4 °C, the hysteresis temperature is nearly 20 °C, and the bandgap reference voltage is 1.205 V with a temperature coefficient 12.84 ppm/°C from −40 to 150 °C. Long-term stability, high sensitivity, small size, and high portability have been achieved by the proposed circuit which can be widely used in different application fields.