Abstract
Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.
Chapter PDF
Similar content being viewed by others
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
International Technology Roadmap for Semiconductors (ITRS), Semiconductor Industry Association (2007)
Pavlidis, V.F., Friedman, E.G.: Three Dimensional Integrated Circuit Design. Morgan Kaufmann Publishers, San Francisco (2009)
Joyner, J.W., et al.: Impact of Three-Dimensional Architectures on Interconnects in Gigascale Integration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9(6), 922–928 (2001)
Rahman, A., Reif, R.: System Level Performance Evaluation of Three-Dimensional Integrated Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8(6), 671–678 (2000)
Stroobandt, D., Van Campenhout, J.: Accurate Interconnection Lengths in Three-Dimensional Computer Systems. IEICE Transactions on Information and System, Special Issue on Physical Design in Deep Submicron 10(1), 99–105 (2000)
Joyner, J.W., Meindl, J.D.: Opportunities for Reduced Power Distribution Using Three-Dimensional Integration. In: Proceedings of the IEEE International Interconnect Technology Conference, June 2002, pp. 148–150 (2002)
Banerjee, K., Souri, S.K., Kapour, P., Saraswat, K.C.: 3-D ICs: A Novel Chip Design Paradigm for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration. Proceedings of the IEEE 89(5), 602–633 (2001)
Koyanagi, M., et al.: Future System-on-Silicon LSI Chips. IEEE Micro 18(4), 17–22 (1998)
Pavlidis, V.F., Friedman, E.G.: Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits. Proceedings of the IEEE, Special Issue on 3-D Integration Technology 97(1), 123–140 (2009)
Bernstein, K., et al.: Interconnects in the Third Dimension: Design Challenges for 3-D ICs. In: Proceedings of the IEEE/ACM Design Automation Conference, June 2007, pp. 562–567 (2007)
Patti, R.S.: Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs. Proceedings of the IEEE 94(6), 1214–1224 (2006)
Lewis, D.L., Lee, H.-H.S.: A Scan-Island Based Design Enabling Pre-Bond Testability in Die-Stacked Microprocessors. In: Proceedings of the IEEE International Test Conference, October 2007, pp. 1–8 (2007)
Cong, J., Wei, J., Zhang, Y.: A Thermal-Driven Floorplanning Algorithm for 3-D ICs. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, November 2004, pp. 306–313 (2004)
Henry, D., et al.: Low Electrical Resistance Silicon Through Vias: Technology and Characterization. In: Proceedings of the IEEE International Electronic Components and Technology Conference, June 2006, pp. 1360–1365 (2006)
Garrou, P.: Future ICs Go Vertical. Semiconductor International (February 2005)
Karnezos, M.: 3-D Packaging: Where All Technologies Come Together. In: Proceedings of IEEE/SEMI International Electronics Manufacturing Technology Symposium, July 2004, pp. 64–67 (2004)
Miettinen, J., Mantysalo, M., Kaija, K., Ristolainen, E.O.: System Design Issues for 3D System-in-Package (SiP). In: Proceedings of the IEEE International Electronic Components and Technology Conference, June 2004, pp. 610–615 (2004)
Beyne, E.: The Rise of the 3rd Dimension for System Integration. In: Proceedings of the IEEE International Interconnect Technology Conference, June 2006, pp. 1–5 (2006)
Pavlidis, V.F., Friedman, E.G.: Interconnect Delay Minimization through Interlayer Via Placement in 3-D ICs. In: Proceedings of the ACM Great Lakes Symposium on VLSI, April 2005, pp. 20–25 (2005)
FDSOI Design Guide, MIT Lincoln Laboratories, Cambridge (2006)
Burns, J.A., et al.: A Wafer-Scale 3-D Circuit Integration Technology. IEEE Transactions on Electron Devices 53(10), 2507–2515 (2006)
Bower, C.A., et al.: High Density Vertical Interconnect for 3-D Integration of Silicon Integrated Circuits. In: Proceedings of the IEEE International Electronic Components and Technology Conference, June 2006, pp. 399–403 (2006)
Jang, D.M., et al.: Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV). In: Proceedings of the IEEE International Electronic Components and Technology Conference, June 2007, pp. 847–850 (2007)
Savidis, I., Friedman, E.G.: Electrical Modeling and Characterization of 3-D Vias. In: Proceedings of the IEEE International Symposium on Circuits and Systems, May 2008, pp. 784–787 (2008)
Otten, R.H.J.M.: Automatic Floorplan Design. In: Proceedings of the IEEE/ACM Design Automation Conference, June 1982, pp. 261–267 (1982)
Yong, E.F.Y., Chu, C.C.N., Zion, C.S.: Twin Binary Sequences: A Non-Redundant Representation for General Non-Slicing Floorplan. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22(4), 457–469 (2003)
Cheng, L., Deng, L., Wong, D.F.: Floorplanning for 3-D VLSI Design. In: Proceedings of the IEEE International Asia and South Pacific Design Automation Conference, January 2005, pp. 405–411 (2005)
Li, Z., et al.: Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Transactions on Circuits and Systems I: Regular Papers 53(12), 2637–2646 (2006)
Deng, Y., Maly, W.P.: Interconnect Characteristics of 2.5-D System Integration Scheme. In: Proceedings of the IEEE International Symposium on Physical Design, April 2001, pp. 341–345 (2001)
Li, Z., et al.: Efficient Thermal Via Planning Approach and its Application in 3-D Floorplanning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(4), 645–658 (2007)
Yan, T., Dong, Q., Takashima, Y., Kajitani, Y.: How Does Partitioning Matter for 3D Floorplanning. In: Proceedings of the ACM International Great Lakes Symposium on VLSI, April/May 2006, pp. 73–76 (2006)
Healy, M., et al.: Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(1), 38–52 (2007)
Lo, W.-C., et al.: An Innovative Chip-to-Wafer and Wafer-to-Wafer Stacking. In: Proceedings of the IEEE International Electronic Components and Technology Conference, June 2006, pp. 409–414 (2006)
Goplen, B., Sapatnekar, S.: Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(4), 692–709 (2006)
Obenaus, S.T., Szymanski, T.H.: Gravity: Fast Placement for 3-D VLSI. ACM Transactions on Design Automation of Electronic Systems 8(3), 298–315 (2003)
Harter, A.: Three-Dimensional Integrated Circuit Layout. Cambridge University Press, Cambridge (1991)
Kaya, I., Olbrich, M., Barke, E.: 3-D Placement Considering Vertical Interconnects. In: Proceedings of the IEEE International SOC Conference, September 2003, pp. 257–258 (2003)
Davis, W.R., et al.: Demystifying 3D ICs: the Pros and Cons of Going Vertical. IEEE Design and Test of Computers 22(6) (November/December 2005)
Eisenmann, H., Johannnes, F.M.: Generic Global Placement and Floorplanning. In: Proceedings of the IEEE/ACM Design Automation Conference, June 1998, pp. 269–274 (1998)
Goplen, B., Sapatnekar, S.: Efficient Thermal Placement of Standard Cells in 3-D ICs using a Force Directed Approach. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, November 2003, pp. 86–89 (2003)
Enbody, R.J., Lynn, G., Tan, K.H.: Routing the 3-D Chip. In: Proceedings of the IEEE/ACM Design Automation Conference, June 1991, pp. 132–137 (1991)
Tong, C.C., Wu, C.-L.: Routing in a Three-Dimensional Chip. IEEE Transactions on Computers 44(1), 106–117 (1995)
Minz, J., Lim, S.K.: Block-Level 3-D Global Routing With an Application to 3-D Packaging. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(10), 2248–2257 (2006)
Ohtsuki, T. (ed.): Advances in CAD for VLSI. Layout Design and Verification, vol. 4. Elsevier, Amsterdam (1986)
Cong, J., Xie, M., Zhang, Y.: An Enhanced Multilevel Routing System. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, November 2002, pp. 51–58 (2002)
Cong, J., Zhang, Y.: Thermal Driven Multilevel Routing for 3-D ICs. In: Proceedings of the IEEE Asia and South Pacific Design Automation Conference, June 2005, pp. 121–126 (2005)
Pavlidis, V.F., Friedman, E.G.: Timing Driven Via Placement Heuristics in 3-D ICs. Integration, the VLSI Journal 41(4), 489–508 (2008)
Boese, K.D., et al.: Fidelity and Near-Optimality of Elmore-Based Routing Constructions. In: Proceedings of the IEEE International Conference on Computer Design, October 1993, pp. 81–84 (1993)
Löfberg, J.: YALMIP: A Toolbox for Modeling and Optimization in MATLAB. In: Proceedings of the IEEE International Symposium on Computer-Aided Control Systems Design, September 2004, pp. 284–289 (2004)
Friedman, E.G. (ed.): Clock Distribution Networks in VLSI Circuits and Systems. IEEE Press, New Jersey (1995)
Friedman, E.G.: Clock Distribution Networks in Synchronous Digital Integrated Circuits. Proceedings of the IEEE 89(5), 665–692 (2001)
Xanthopoulos, T., et al.: The Design and Analysis of the Clock Distribution Network for a 1.2 GHz Alpha Microprocessor. In: Proceedings of the IEEE International Solid-State Circuits Conference, February 2001, pp. 402–403 (2001)
Prunty, C., Gal, L.: Optimum Tapered Buffer. IEEE Journal of Solid-State Circuits 27(1), 1005–1008 (1992)
Pavlidis, V.F., Savidis, I., Friedman, E.G.: Clock Distribution Networks for 3-D Integrated Circuits. In: Proceedings of the IEEE International Conference on Custom Integrated Circuits, September 2008, pp. 651–654 (2008)
Pavlidis, V.F., Savidis, I., Friedman, E.G.: Clock Distribution Architectures for 3-D SOI Integrated Circuits. In: Proceedings of the IEEE International Silicon-on-Insulator Conference, October 2008, pp. 111–112 (2008)
Jantsch, A., Tenhunen, H.: Networks on Chip. Kluwer Academic Publishers, Dordrecht (2003)
Benini, L., De Micheli, G.: Networks on Chip: A New SoC Paradigm. IEEE Computer 31(1), 70–78 (2002)
Kumar, S., et al.: A Network on Chip Architecture and Design Methodology. In: Proceedings of the International IEEE Annual Symposium on VLSI, April 2002, pp. 105–112 (2002)
Li, F., et al.: Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. In: Proceedings of the IEEE International Symposium on Computer Architecture, June 2006, pp. 130–142 (2006)
Pavlidis, V.F., Friedman, E.G.: 3-D Topologies for Networks-on-Chip. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15(10), 1081–1090 (2007)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 IFIP
About this paper
Cite this paper
Pavlidis, V.F., Friedman, E.G. (2010). Physical Design Issues in 3-D Integrated Technologies. In: Piguet, C., Reis, R., Soudris, D. (eds) VLSI-SoC: Design Methodologies for SoC and SiP. VLSI-SoC 2008. IFIP Advances in Information and Communication Technology, vol 313. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12267-5_1
Download citation
DOI: https://doi.org/10.1007/978-3-642-12267-5_1
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-12266-8
Online ISBN: 978-3-642-12267-5
eBook Packages: Computer ScienceComputer Science (R0)