Abstract
Representing finite field elements with respect to the polynomial (or standard) basis, we consider a bit parallel multiplier architecture for the finite field GF(2m) . Time and space complexities of such a multiplier heavily depend on the field defining irreducible polynomials. Based on a number of important classes of irreducible polynomials, we give exact complexity analyses of the multiplier gate count and time delay. In general, our results match or outperform the previously known best results in similar classes. We also present exact formulations for the coordinates of the multiplier output. Such formulations are expected to be useful to efficiently implement the multiplier using hardware description languages, such as VHDL and Verilog, without having much knowledge of finite field arithmetic.
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Agnew, G.B., Mullin, R.C., Vanstone, S.A.: An Implementation of Elliptic Curve Cryptosystems Over F2 155. IEEE J. Selected Areas in Communications 11(5), 804–813 (1993)
Halbutogullari, A., Koc, C.K.: Mastrovito Multiplier for General Irreducible Polynomials. IEEE Transactions on Computers 49(5), 503–518 (2000)
Mastrovito, E.D.: VLSI Designs for Multiplication over Finite Fields GF(2m). In: Mora, T. (ed.) AAECC 1988. LNCS, vol. 357, pp. 297–309. Springer, Heidelberg (1989)
Mastrovito, E.D.: VLSI Architectures for Computation in Galois Fields. PhD thesis, Linkoping Univ., Linkoping Sweden (1991)
Menezes, A.J., Blake, I.F., Gao, X., Mullin, R.C., Vanstone, S.A., Yaghoobian, T.: Applications of Finite Fields. Kluwer Academic Publishers, Dordrecht (1993)
Reyhani-Masoleh, A., Hasan, M.A.: A New Efficient Architecture of Mastrovito Multiplier over GF(2m). In: 20th Biennial Symposium on Communications, Kingston, Ontario, Canada, May 2000, pp. 59–63 (2000)
Rodriguez-Henriquez, F., Koc, C.K.: Parallel Multipliers Based on Special Irreducible Pentanomials. IEEE Transactions on Computers (2003) (to appear), available at http://islab.oreonstate.edu/koc/Publications.html
Song, L., Parhi, K.K.: Low Complexity Modified Mastrovito Multipliers over Finite Fields GF(2M). In: Proc. IEEE International Symposium on Circuits and Systems, ISCAS 1999, pp. 508–512 (1999)
Sunar, B., Koc, C.K.: Mastrovito Multiplier for All Trinomials. IEEE Transactions on Computers 48(5), 522–527 (1999)
Wu, H.: Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis. IEEE Transactions on Computers 51(7), 750–758 (2002)
Zhang, T., Parhi, K.K.: Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials. IEEE Transactions on Computers 50(7), 734–748 (2001)
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Reyhani-Masoleh, A., Hasan, M.A. (2003). On Low Complexity Bit Parallel Polynomial Basis Multipliers. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds) Cryptographic Hardware and Embedded Systems - CHES 2003. CHES 2003. Lecture Notes in Computer Science, vol 2779. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45238-6_16
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DOI: https://doi.org/10.1007/978-3-540-45238-6_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40833-8
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