ASIC Design

Abstract

This chapter deals with the final steps for a prototype development, according to the methodology introduced in Sect. 2.1:

12 Study of a suitable architecture to be integrated into an ASIC, based on results obtained from validation of concept with discrete components electronics.

13 Design and production of a low-noise position sense interface based on a standard CMOS technology.

14 Experimental characterization of a multi-chip prototype.

This chapter deals with the final steps for a prototype development, according to the methodology introduced in Sect. 2.1:

• 12 Study of a suitable architecture to be integrated into an ASIC, based on results obtained from validation of concept with discrete components electronics.

• 13 Design and production of a low-noise position sense interface based on a standard CMOS technology.

• 14 Experimental characterization of a multi-chip prototype.

9.1 Architecture

In order to develop a final system for detection of earth magnetic field some more considerations must be taken into account to design an ASIC with respect to the first demonstrative prototype based on discrete components, as shown in Chap. 8 First set of measures followed an accurate phase of electromechanical characterization of devices useful to make a selection of fully working parts and detect their resonance frequencies. MEMS are then glued close to readout electronics and used for magnetic field measures. Thus, it is known for each device the precise frequency to be used for current excitation at resonance. This procedure works well during a research and prototyping phase but it is affordable to follow the same procedure for industrialization and mass production, due to amount of parts to be characterized and related costs.

These remarks lead to the need to evaluate whether a closed-loop or an open-loop control is preferable for the final two chips system [1]. The first control type, closed-loop, requires a feedback network to drive the driving block and adjust the driving frequency around device resonance frequency. In this way, neglecting variation which can be due to device to device quality factor variation, any device is driven at the correct frequency always providing the maximum output signal and so guaranteeing a relatively good repeatability among samples. On the other hand, in an open-loop system, driving frequency must be set directly tuning oscillator parts or, in case a digital to analog converter (DAC) is used for excitation, storing the correct value of driving frequency in a memory (i.e., with an initial calibration after production; any sensor usually has an initial calibration/self-test after production).

The choice about loop typology is mainly made according to power consumption considerations, as they represent an extremely important specification for systems to be embedded in battery powered devices. Main blocks of driving and readout electronics (at least as far as frontend is concerned) are in common for both open-loop and closed-loop control. This latter has a higher power consumption due to the feedback network to tune oscillation frequency, in addition to a larger ASIC occupied area. Taking into account this general system level remarks, an open-loop architecture is implemented (schematically shown in Fig. 9.1). The problem related to driving frequency tuning still remains.

Fig. 9.1

Simplified block diagram of an open-loop implementation. Oscillator signal is used both to drive excitation circuit and as a reference for a synchronous demodulation filtering technique

As emerged with electromechanical tests, even once the magnetometer type is chosen, it is not reliable to set a priori a driving frequency. To this problem, two possible solutions can be proposed: an auxiliary circuitry measures the device resonance frequency either after production as final test before commercialization or when the compass application is executed. Even in this second case, the additional power consumption related to self-test would not affect the overall power consumption during application execution. In this way, the main problem related to open-loop control could be overcome.

After deciding control system type, frontend electronics must be chosen. As sensors are based on a differential capacitive scheme, a differential readout electronic architecture is consequently chosen. Analysis reported in Sect. 8.2 still applies to ASIC development with the exception that a fully differential operational amplifier should be used (instead of two single-ended stages) to minimize phase shift between the two channels, to reduce noise contribution, and to avoid active gain stages mismatches which might affect the overall closed-loop transfer function of positive and negative inputs.

In case of Lorentz force magnetometers driving current signal, which is at resonance, represents a “high-frequency” carrier which is amplitude modulated by capacitance variation and so by magnetic field. With an approach based on synchronous demodulation, before analog to digital conversion, the envelope containing magnetic field information can be extracted (Fig. 9.2). Demodulation circuit depends on driving signal type: either a sine wave or a square wave. A typical demodulator for the first case is based on Gilbert cells with the main drawback of higher power consumption not negligible with respect to analog frontend. The latter, instead, can be demodulated using a set of switches to multiply by + 1 and − 1; it can be implemented using MOSFET gated by a reference signal controlled from oscillator. A sinusoid driving signal has main advantages to avoid noise folding and require a lower bandwidth in analog chain. Yet, circuitry to generate a sine wave and for related demodulation is usually more complex. Thinking of a final integrated system, the choice of a square wave based driving allows to save power consumption.

Fig. 9.2

Schematic representation of a synchronous demodulation scheme to detect carrier envelope containing magnetic field information

A final remark about system design is related to minimum and maximum magnetic field to be sensed and so the dynamic range of the system. A full scale range (FSR) of ±100 μT is requested according to given specifications (for magnetic field measurement with good linearity) but it is a good design strategy to increase further to cope with external magnetic field which may saturate the device:

$$\displaystyle{ \begin{array}{ll} &\mathrm{FSR} =\mathrm{ \pm 1.2\;\mathrm{m}\mathrm{T}} \\ &B_{\mathrm{min}} \sim \mathrm{ 1\;\mathrm{\upmu }\mathrm{T}}\end{array} }$$

(9.1)

and the corresponding dynamic range is:

$$\displaystyle{ \begin{array}{l} \mathrm{DR} = 20\,\mbox{$ \cdot$ }\,\log \left (\frac{\mathrm{2.4\;\mathrm{m}\mathrm{T}}} {\mathrm{1\;\mathrm{\upmu }\mathrm{T}}} \right ) = 67.6\,\mathrm{dB}\end{array} }$$

(9.2)

9.2 A Continuous-Time Fully Differential Transresistance Amplifier

An integrated circuit was implemented aiming at improving resolution and demonstrating the feasibility of a double-chip (MEMS + ASIC) magnetic field sensing system for consumer applications. A first prototype of VLSI, based on a topology similar to the one used for discrete components circuitry, has been designed in a standard CMOS 150 nm process. A negative feedback double-channel transresistance amplifier is designed using a fully differential operational amplifier; a simplified schematic is shown in Fig. 9.3. This choice rejects all mismatches that would occur when using two separate single-ended stages. In the differential configuration indeed offset drifts, temperature effects, and long term stability of the active component affect the two channels in the same way. In order to design the first analog stage to couple to MEMS the following blocks are required:

• high-gain, ultra-low-noise, fully differential amplifier with a suitable feedback network;

• common mode feedback network to set and stabilize both input and output biasing levels;

• output buffers to monitor signals without loading the outputs of the amplifier.

Fig. 9.3

Fully differential transresistance amplifier with MEMS modelled as a differential variable capacitor

9.2.1 ASIC Noise

As calculated in Sect. 4.3, the overall noise budget for ASIC is:

$$\displaystyle{ \begin{array}{l} \sqrt{ S_{B_{\mathrm{eln}}}} = \sqrt{S_{B_{\mathrm{mech } }}} = \sqrt{\frac{S_{B_{\mathrm{TOT } } } } {2}} =\mathrm{ 223\;\mathrm{n}\mathrm{T}/\sqrt{\mathrm{Hz}}}.\end{array} }$$

(9.3)

which must account for:

• Analog interface noise: the complete analog signal path between sensor and ADC (if it is a digital product) or output PAD (for an analog product);

• ADC quantization and thermal noise (if a digital output is needed);

• Digital post-processing noise (i.e., quantization noise).

ADC and digital post-processing will not be discussed in this manuscript but their noise must be accounted for. A possible design approach is to equally split noise budget between analog interface and ADC, under the assumption that digital noise is almost negligible. Alternatively, sensor analog interface sets the SNR of the full signal chain and ADC noise is negligible. This type of optimization depends on architectures, area, and power consumption considerations for each specific case. ASIC noise budget reported in Eq. (9.3) can be converted in terms of capacitance resolution according to:

$$\displaystyle{ \begin{array}{rcl} \sqrt{ S_{C,\mathrm{eln}}} & =&2C_{0}\,\mbox{$ \cdot$ }\,\frac{\sqrt{S_{x,\mathrm{eln }}}} {g} \\ & =&2C_{0}\,\mbox{$ \cdot$ }\,\frac{Q} {k} \,\mbox{$ \cdot$ }\,\frac{I\,\mbox{$ \cdot$ }\,L\,\mbox{$ \cdot$ }\,\sqrt{S_{B,\mathrm{eln }}}} {g} \\ & =&\mathrm{158\;\mathrm{z}\mathrm{F}/\sqrt{\mathrm{Hz}}},\end{array} }$$

(9.4)

for an optimized device.

9.2.1.1 Analog Interface Noise

The first amplifier in the signal path is typically the most important block to set the desired SNR: capacitive coupling to the sensor and the noise of the amplifier itself must be taken into account. It is now assumed that the full ASIC noise budget is accounted for the input stage, a fully differential transresistance amplifier reported in Fig. 9.3. This circuit is negative looped and so the two input pins of the operational amplifier can be considered virtual grounds whose value is fixed by a common mode feedback network (required in all fully differential schemes). Differential output voltage, V _out = V _out+ − V _out− using Laplace domain is:

$$\displaystyle{ \begin{array}{rcl} V _{\mathrm{out}+} - V _{\mathrm{out}-}& =&V _{\mathrm{BIAS}}\,\mbox{$ \cdot$ }\,\left [ \frac{1} { \frac{1} {s\left (C_{0}-\frac{\varDelta C(t)} {2} \right )} } - \frac{1} { \frac{1} {s\left (C_{0}+ \frac{\varDelta C(t)} {2} \right )} } \right ]\,\mbox{$ \cdot$ }\, \frac{R_{F}} {1+sR_{F}\,\mbox{$ \cdot$ }\,C_{F}} \\ & =& \frac{R_{F}} {1+sR_{F}\,\mbox{$ \cdot$ }\,C_{F}}\,\mbox{$ \cdot$ }\,V _{\mathrm{BIAS}}\left [sC_{0} - s\frac{\varDelta C(t)} {2} - sC_{0} - s\frac{\varDelta C(t)} {2} \right ], \end{array} }$$

(9.5)

and with some reductions output voltage vs. input differential capacitance variation transfer function is obtained:

$$\displaystyle{ \begin{array}{l} \frac{V _{\mathrm{out}}(t)} {\varDelta C(t)} = -V _{\mathrm{BIAS}}\,\mbox{$ \cdot$ }\, \frac{sR_{F}} {1+sR_{F}\,\mbox{$ \cdot$ }\,C_{F}}. \end{array} }$$

(9.6)

Ideally, output voltage does not depend on input parasitic capacitances and on MEMS rest value. This transfer function is useful to convert output noise into an equivalent input noise in terms of minimum differential capacitance variation which can be detected. The main noise sources in a fully differential continuous-time transresistance amplifier are given by feedback resistors and MOSFETs of input differential pair and related active load. These two contributions are now detailed.

9.2.1.1.1 Feedback Resistor Noise

Output voltage noise due to feedback resistors of differential transresistance amplifier is:

$$\displaystyle{ \begin{array}{l} S_{\mathrm{out},R_{F},n} = 2\,\mbox{$ \cdot$ }\,\frac{4k_{\mathrm{B}}\,\mbox{$ \cdot$ }\,T} {R_{F}} \,\mbox{$ \cdot$ }\, \frac{R_{F}^{2}} {\left (1+sR_{F}\,\mbox{$ \cdot$ }\,C_{F}\right )^{2}} \ \left [\mathrm{\;\frac{\mathrm{V}^{2}} {\mathrm{Hz}} }\right ], \end{array} }$$

(9.7)

where the factor 2 takes into account two independent noise sources from feedback resistors. Equation (9.7) can be converted into a corresponding $\varDelta C_{R_{F},n}$ using the input vs. output transfer function (Eq. (9.6)):

$$\displaystyle{ \begin{array}{l} S_{C_{R},n} = \frac{S_{\mathrm{out},R_{F},n}} {\left \vert T(j\omega )\right \vert ^{2}} = \frac{8\,\mbox{$ \cdot$ }\,k_{\mathrm{B}}T} {R_{F}} \,\mbox{$ \cdot$ }\, \frac{1} {\omega _{r}^{2}\,\mbox{$ \cdot$ }\,V _{\mathrm{BIAS}}^{2}} \ \left [\mathrm{\;\frac{\mathrm{F}^{2}} {\mathrm{Hz}}}\right ], \end{array} }$$

(9.8)

Under the hypothesis that noise due input pair transistors of the operational amplifier is negligible with respect to noise of feedback resistors (this hypothesis is verified in Sect. 9.2.1.1), at the nominal frequency of 28.3 kHz the following values of R _F are estimated to meet noise analog interface noise specifications:

• $R_{F} \approx \mathrm{ 4.6\;\mathrm{M}\Omega }$ considering a V _BIAS = 3 V;

• $R_{F} \approx \mathrm{ 18.6\;\mathrm{M}\Omega }$ considering a V _BIAS = 1.5 V;

Here comes one of the main drawbacks of choosing a transresistance amplifier in an integrated CMOS technology: the implementation of high value resistors requires large active areas and possible solutions for this implementation can be done with:

• Integrated resistors;

• MOSFET working in ohmic region or subthreshold/off condition;

• Resistors implemented using switching capacitors.

A solution based on integrated resistors, compared to the implementation of a high ohmic resistance with MOSFETs in subthreshold/off region reg has main advantages in terms of better linearity, signal full scale, and noise with the drawback of occupied active area. Considering a standard CMOS technology with the possibility to implement polysilicon resistors with a sheet resistance in the range of $\mathrm{300\;\Omega /sheet}$, a rough estimation of the required area for a resistor value of about $\mathrm{5\;\mathrm{M}\Omega }$ is:

$$\displaystyle{ \begin{array}{l} \left ( \frac{L} {W}\right )_{\mathrm{Poly-Si}} = \frac{2\,\mbox{$ \cdot$ }\,R_{F}} {R_{\mathrm{sheet}}} = \frac{2\,\mbox{$ \cdot$ }\,5\,\mbox{$ \cdot$ }\,10^{6}} {300} = 3.3\,\mbox{$ \cdot$ }\,10^{5} \end{array} }$$

(9.9)

and so with a width dimension of 1 μm, the area occupied by feedback resistors is estimated to be approximately A _Poly−Si = 190 μm × 190 μm. Width dimension must be chosen larger than minimum allowed dimension in order to have a good matching.

9.2.1.1.2 Input Stage Noise

In a typical (fully differential) operational amplifier main sources of noise are transistors of input pair and of its active load. These sources must now be compared to feedback resistor noise and, possibly, make them negligible. Voltage noise due to transistors is:

$$\displaystyle{ \begin{array}{l} S_{V,\mathrm{MOSFETs}} = \frac{2\,\mbox{$ \cdot$ }\,4\gamma \,\mbox{$ \cdot$ }\,k_{\mathrm{B}}T} {g_{m}} \quad \left [\mathrm{\;\mathrm{V}^{2}/\sqrt{\mathrm{Hz}}}\right ].\end{array} }$$

(9.10)

This voltage noise spectral density can be transferred to the output of the TIA and then converted into an equivalent resolution in terms of capacitance variation as done for R _F noise:

$$\displaystyle{ \begin{array}{rcl} S_{C,\mathrm{MOS}_{n}} & =&\frac{2\,\mbox{$ \cdot$ }\,4k_{\mathrm{B}}T\,\mbox{$ \cdot$ }\,\gamma } {g_{m}} \,\mbox{$ \cdot$ }\,\frac{1+\omega ^{2}\,\mbox{$ \cdot$ }\,R_{ F}^{2}\,\mbox{$ \cdot$ }\,(C_{ F}+C_{\mathrm{in}})^{2}} {\omega _{r}^{2}\,\mbox{$ \cdot$ }\,R_{F}^{2}\,\mbox{$ \cdot$ }\,V _{\mathrm{BIAS}}^{2}} \\ & =& \frac{2\,\mbox{$ \cdot$ }\,4k_{\mathrm{B}}T\,\mbox{$ \cdot$ }\,\gamma } {\sqrt{2\,\mbox{$ \cdot$ } \,\mu C_{\mathrm{ox } } \,\mbox{$ \cdot$ } \,\frac{W} {L} \,\mbox{$ \cdot$ }\,I_{D}}}\,\mbox{$ \cdot$ }\,\frac{1+\omega ^{2}\,\mbox{$ \cdot$ }\,R_{ F}^{2}\,\mbox{$ \cdot$ }\,(C_{ F}+C_{\mathrm{in}})^{2}} {\omega _{r}^{2}\,\mbox{$ \cdot$ }\,R_{F}^{2}\,\mbox{$ \cdot$ }\,V _{\mathrm{BIAS}}^{2}}. \end{array} }$$

(9.11)

Considering a very conservative case due to the following strict working conditions:

• Width W = 1.5 μm;

• Length L = 0.9 μm;

• μC _ox = 42 μA∕V²;

• γ = 2;

• Drain current I _D = 0.5 μA;

• Resonance frequency f _r = 28.3 kHz;

• Feedback resistance $R_{F} =\mathrm{ 5\;\mathrm{M}\Omega }$;

• Feedback capacitance C _F = 90 fF;

• Input parasitic capacitance C _in = 2 pF;

• Stators biasing voltage V _BIAS = 3 V;

an equivalent noise of about $\mathrm{76\;\mathrm{z}\mathrm{F}/\sqrt{\mathrm{Hz}}}$ is estimated which is, as previously supposed, negligible with respect to resistors noise. Noise due to the two transistor forming the active load of the input pair can be made negligible with an optimization of overdrive voltages and dimensions.

9.2.2 Fully Differential Operational Amplifier

Figure 9.4 shows the transistor level of a typical fully differential operational transconductance amplifier (OTA). The core transistors of the used technology are powered at 1.8 V which does not provide high enough swing to design a telescopic cascoded amplifier (this latter would have the main advantage of a lower power consumption). For this reason and to obtain a high open-loop gain a folded cascode amplifier is implemented.

Fig. 9.4

Transistor level schematic of the fully differential operational amplifier

In this configuration the open-loop gain of the amplifier is:

$$\displaystyle{ \begin{array}{l} A_{0} = \frac{V _{\mathrm{out},a}-V _{\mathrm{out},b}} {V _{\mathrm{in},a}-V _{\mathrm{in},b}} = g_{m_{1}}\,\mbox{$ \cdot$ }\,R_{\mathrm{out}},\end{array} }$$

(9.12)

and its bandwidth is:

$$\displaystyle{ \begin{array}{l} f_{p} = \frac{1} {2\pi \,\mbox{$ \cdot$ }\,R_{\mathrm{out}}\,\mbox{$ \cdot$ }\,C_{\mathrm{out}}}, \end{array} }$$

(9.13)

being:

$$\displaystyle{ \begin{array}{l} R_{\mathrm{out}} = \left [g_{m_{7}}\,\mbox{$ \cdot$ }\,r_{0_{7}}\,\mbox{$ \cdot$ }\,\left (r_{0_{3}} \parallel r_{0_{1}}\right )\right ] \parallel \left [g_{m_{9}}\,\mbox{$ \cdot$ }\,r_{0_{9}}\,\mbox{$ \cdot$ }\,r_{0_{1}1}\right ] \end{array} }$$

(9.14)

Below, some of the adopted design considerations to maximize the loop gain (90 dB) and minimize noise are summarized:

• a general constraint used in the design was to keep 15–20 mV of overdrive for all the transistors, to guarantee operation at least in the weak inversion region [2];

• the length of N-type input transistors pair T1 and T2 is chosen to avoid short channel effect ( ≥ 2 μm). The N-type choice is due to their higher transconductance with respect to the P-type, while holding similar 1∕f noise performances. Moreover, being the input signal modulated at > 20 kHz

• the tail current is chosen to minimize the input-referred noise and to increase the overdrive voltage of transistors T3 and T4, so that their noise is almost negligible compared to the input pair. The same is done for the noise of T10 and T11, which are the cascode current generators. Input transistor areas are further increased to reduce the flicker noise;

• the biasing voltages of the cascode transistors (VCAS,N and VCAS,P in Fig. 9.4) are chosen to symmetrically increase the output dynamic range. The current in the cascode stage and the transistors sizes are set to achieve the desired gain as described above;

• finally, an estimation of a compensation capacitance at the outputs is done to guarantee a minimum phase margin of 60° in case of a buffer feedback. This compensation capacitance value will be revised considering common mode stability too.

Figure 9.5 shows the amplitude and phase of the open-loop gain with a compensation capacitance of 400 fF. The amplifier achieves a low, frequency open-loop gain of 90 dB, a GBWP of 4.4 MHz, a phase margin of 62°, and a current consumption of 4.4 μA.

Fig. 9.5

Bode diagrams of fully differential folded cascode, with 400 fF compensation capacitance

9.2.2.1 Common Mode Feedback Network

As previously discussed, the magnetic field produces a differential signal between the input nodes; in order to reject all possible common mode contributions, that can lead to a shift in the polarization values—and can consequently change the behavior of the OTA—a common mode feedback network (CMFB) is needed.

Different solutions for the CMFB network can be implemented. The chosen solution monitors the output nodes, compares them with a reference voltage and acts on the folded cascode current generator to compensate the output DC level drift. The input nodes are DC stabilized by the feedback network. A schematic of this CMFB network is shown in Fig. 9.6.

Fig. 9.6

Transistor level schematic of common mode feedback (CMFB) network. $V _{\mathrm{in},a_{\mathrm{CMFB}}}$ and $V _{\mathrm{in},b_{\mathrm{CMFB}}}$ correspond, respectively, to the outputs V _out,a and V _out,b of the differential amplifier of Fig. 9.4

If there is a positive common mode signal on the outputs of the amplifier, both T20 and T23 gatesource voltages are reduced, so that the currents in T27 and T26 are unbalanced, with I _T, 27 < I _T, 26. The current of T26 is mirrored in the cascode current generators, reducing the current that flows on the outputs resistances. This leads in turn to a reduction of the amplifier outputs voltages, closing the negative feedback and correcting the common mode behavior of the OTA. In case of a differential signal, the sum of the currents that flows in T20 and T23 remains constant, and the same occurs in T26, so that the CMFB network circuit does not influence the differential behavior of the OTA. All the DC currents are chosen in order to have a 1:1 ratio in the folded cascode current mirror.

The CMFB compensation capacitance is connected at the outputs of the fully differential amplifier, since this is the node with the highest impedance. It is possible to separate the compensation of the amplifier and of the CMFB network by connecting multiple capacitances either differentially between the two outputs or between the outputs and V _SS. The compensation capacitances are chosen to guarantee the stability of both differential and common mode amplifiers even in case of unity gain connection. An overall current consumption of less than 1 μA is estimated for this CMFB solution.

9.3 Verilog—A Model for Cadence^Ⓡ Environment

Models to simulate magnetometers (and more generally MEMS) taking into account physics, geometry, and technological constraints are implemented in a first phase of this project using Simulink^Ⓡ tool and they turned out to be very helpful in system design. It is however not straightforward to include in Simulink simulations secondary effects such as the presence of noise, parasitic capacitances, electronics nonidealities, etc.

In order to better analyze the overall performance and power dissipation from a fully coupled-system point of view and to prepare a custom tool for ASIC design, alternative solutions for sensor modelling are analyzed with an eye on languages compatible with integrated circuits simulators. Electromechanical coupled simulations are getting of deeper interest right for the design of ASIC for MEMS: sensor modelling inside one single simulation environment (Cadence^Ⓡ) allows to optimize electronic frontend considering mechanical nonidealities and sensor vs. electronics interference. As an ASIC must be designed inevitably using the software for which technology design-kit is available, a detailed magnetometer model has been integrated directly in the VLSI simulation environment. Verilog-AMS is a derivative of Verilog hardware description language which includes analog and mixed signal extensions to describe behavior of devices. For this specific case, Verilog-A, a continuous-time subset of Verilog-AMS, is used. A Verilog project consists of a hierarchy of modules, each one with a set of inputs, outputs, and bidirectional ports called “disciplines” (real, electrical, kinematic, thermal, magnetic, etc.). Each module can be associated to a schematic symbol the parameters of which can be changed in the object properties windows. A typical Verilog-A listing consists of:

• Inclusion of files required for code compilation;

• Additional “nature” declaration or change of default settings;

• Definition of modules inputs, outputs, and parameters;

• analog begin/end block where are reported sequential instructions which describe the model.

Two main blocks are developed to describe MEMS magnetometer behavior and their corresponding two symbols are placed in a schematic as if they were embedded libraries circuit parts, as shown in Fig. 9.7:

• MEMSMAIN which includes mechanical and electrical behavior of magnetometer, based on the balance of forces acting on the moving mass;

• STOPPER which is a behavioral implementation to simulate mechanical stoppers which are implemented to avoid moving mass collapsing to stators in case of pull-in or high acceleration shocks.

Fig. 9.7

Cadence^Ⓡ schematic where symbols (one for the sensors itself and one to simulate the mechanical stopper) associated to MEMS magnetometer are placed together with other electrical components

9.3.1 MEMS MAIN Module

The first implemented block is MEMS MAIN. Bidirectional ports which define this module are:

• mma and mmb are springs ends to which moving shuttle is anchored. They represent both inputs and outputs because Lorentz current is pumped into them but it is also interesting to monitor the resulting voltage because of their resistance. They are electrical discipline and so they are associated to Voltage “V” and Current “I”;

• stata, statb are the two stators and shu is the rotor even though it does not actually have a direct connection with the package. This port is implemented to monitor the voltage of central point of flexures and so analyze effects due to springs mismatches. The two ports associated to readout electrodes are bidirectional as current due to motion must be sensed and a voltage must be forced. Also they are electrical.

• fext is an additional port to apply an external force different from Lorentz force. It is a kinematic discipline whose access functions are Pos (position) and F (force);

• acc is an input which allows to apply an external acceleration of value g = 9.8 m∕s². It is a customkinematic discipline which is not native in the language but it is implemented for the purpose of this model. Associated access function isAccel;

• xout represents moving mass displacement with respect to rest position. It is a kinematic output;

• cd is differential capacitance variation. It is a non-native Electronics discipline. The associated nature is Cap;

• monitor, monitorkin, and monitorkinv are auxiliary output for variables monitoring during design phase. They are, respectively, associated to: electrical, kinematic, and kinematicv(speed).

Parameters of this block which can be modified using the graphic interface of Cadence^Ⓡ environment (i.e., opening the object properties editor directly from the schematic) are:

• C ₀, sensor rest capacitance;

• gap, gap between rotor and stators at rest;

• damp, damping coefficient;

• mass, effective mass of the device;

• km, elastic stiffness;

• Lspring, spring length;

• B, external magnetic field;

• R1L, R2L, R1R, and R2R resistances associated to each of four suspending elements.

Each of these parameters has a default value which can be modified according to the specific device and simulation; a range of allowed values is set (Fig. 9.8).

Fig. 9.8

The MEMS device can be added in the Cadence^Ⓡ—Virtuoso simulation tool as a basic building block of the circuit and its mechanical parameters can be set in object properties window

After this preliminary phase to define variables and parameters of the model, MEMS behavioral description is implemented. After calculating electrostatic forces both due to driving signal and stators biasing, balance of forces is solved and the resulting value of xout is used for capacitance variation calculation and current flowing through stators.

9.3.2 STOPPER Module

Stopper module is defined as a block with two bidirectional ports xgnd and stopper of kinematics type. This block monitors the displacement of the moving mass and in case of an external force generating pull-in, stopper block activates and limits the displacement to the value diststop which can be set in object properties and it is set, as default, to the same distance as implemented devices.

An if/else structure is used to distinguish when the moving mass is moving, in one direction or the other, beyond the maximum allowed displacement and, if that is the case, its movement is stopped. In order to check that behavioral implementation of the stopper is correct a sinusoid force is applied to the device to generate displacements larger than diststop. Figure 9.9 shows xout with respect to simulation time and it can be seen that when the moving mass reaches diststop = 1.6 μm, the displacement is stopped and limited as long as the force gets lower and the balance of forces gives a displacement lower than diststop.

Fig. 9.9

Moving mass position with respect to time: when the maximum allowed displacement value is reached stopper module blocks the moving mass

9.3.3 Simulations and Model Verification

In order to verify a good implementation for the described Verilog-A model, a set of simulations are performed and more significant results are here reported. Simulations are based on magnetometer N = 4. As a first check, MEMS transfer function is simulated and reported in Fig. 9.10 with a correct value of resonance frequency, low-frequency value, and quality factor.

Fig. 9.10

Cadence^Ⓡ simulation using the Verilog-A magnetometer model, coupled to a CMOS frontend. The transfer function, solved by Spectre circuit simulator, is here simulated as the modulus of the differential capacitance variation vs. frequency

Further tests are executed in time domain comparing results with ones obtained by the same kind of simulation performed using Simulink^Ⓡ. For the sake of verification it is useful to compare Verilog-A model with the previously presented Simulink^Ⓡ model. Figure 9.11 reports two simulations, one performed using Simulink model and one with Verilog-A model in Cadence^Ⓡ environment, with an input acceleration. Indeed, this model is useful not only to simulate the device in presence of a magnetic field (purpose of this kind of sensor) but also in presence of other unwanted external forces, like accelerations.

Fig. 9.11

Simulink and Verilog-A simulations of the effect of an external acceleration onto a magnetometer

9.4 Magnetic Field Measures: MEMS + ASIC

Magnetic field experimental measurements are performed with the implemented circuits and first generation of devices. MEMS is glued on a ceramic carrier and the ASIC is on top of the MEMS with stators wire-bonded to ASIC inputs and moving mass electrodes wire-bonded to carrier for external current excitation.

Figure 9.12 shows the transfer function of the fully differential transresistance amplifier for four different samples: resonance peaks are right below 30 kHz in agreement with measures previously done on devices and discrete electronics. Moreover, the circuit closed-loop bandwidth is at about 200 kHz in line with the pole set by feedback network.

Fig. 9.12

Transresistance differential output voltage with respect to frequency for a fixed magnetic field. MEMS resonance peaks are close to 30 kHz and closed-loop bandwidth is at about 200 kHz in very good agreement with simulations

Sensitivity measurements are performed applying three different values of magnetic field and measuring the resulting output signal of transresistance amplifier. Figure 9.13 shows, for three samples with $\mathrm{5\;\mathrm{M}\Omega }$ feedback resistance, that the peak is proportional to magnetic field intensity and measures have a good repeatability. As a comparison, one sample with $\mathrm{20\;\mathrm{M}\Omega }$ feedback resistor is reported and its output signal is four times higher than the others, on a fixed value of magnetic field. Measured sensitivity with $\mathrm{5\;\mathrm{M}\Omega }$ feedback resistors is 100 nV∕μT in agreement with theoretical predictions and system simulations. ASIC resolution is set by feedback resistors noise and for a biasing voltage of 5 V corresponds to $\mathrm{200\;\mathrm{n}\mathrm{T}\,\mbox{$ \cdot$ }\,\mathrm{m}\mathrm{A}/\sqrt{\mathrm{Hz}}}$.

Fig. 9.13

Transresistance differential output voltage with respect to frequency. MEMS resonance peaks are close to 30 kHz and closed-loop bandwidth is at about 200 kHz in good agreement with simulations