High-Speed Analog Applications

Abstract

In Chapter 3, we obtained accurate BSIMSOI SPICE models for NMOS and PMOS silicon nanowire transistors to replicate the simulated device I–V characteristics. We also calculated voltage-dependent intrinsic gate oxide capacitance, parasitic device resistors and capacitors, including the high frequency effective gate resistance in order to generate accurate extrinsic circuit models for SNTs. This chapter presents the first application of silicon nanowire technology on analog circuits. Various small and large-signal analog circuits such as a single-stage CMOS amplifier, a differential pair amplifier, and a two-stage operational amplifier were designed and simulated using the BSIMSOI SPICE models of SNTs.

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

4.1 Introduction

In Chapter 3, we obtained accurate BSIMSOI SPICE models for NMOS and PMOS silicon nanowire transistors to replicate the simulated device I–V characteristics. We also calculated voltage-dependent intrinsic gate oxide capacitance , parasitic device resistors and capacitors, including the high frequency effective gate resistance in order to generate accurate extrinsic circuit models for SNTs. From these extrinsic models, we reproduced the realistic input and output I–V characteristics, transconductance , and output resistance curves as a function of biasing conditions, S-parameters , power gains , f_max , and f_T . This chapter presents the first application of silicon nanowire technology on analog circuits. Various small and large-signal analog circuits such as a single-stage CMOS amplifier, a differential pair amplifier, and a two-stage operational amplifier were designed and simulated using the BSIMSOI SPICE models of SNTs.

4.2 Brief Description of Transistor Design and Modeling

The optimal SNT body dimensions of 2 nm radius and 10 nm channel length are determined according to the minimum intrinsic transient time s and minimum static and dynamic power dissipation s for each NMOS and PMOS transistor discussed in Chapter 3. The BSIMSOI device models are based on these particular device dimensions and they are used for all the circuit simulations in this chapter.

4.3 Single-Stage CMOS SNT Amplifier

4.3.1 The CMOS Amplifier Design

The layout of an SNT CMOS amplifier which can be used as a large-signal inverter or a small-signal amplifier is shown in Fig. 4.1a. The biasing point of transistors is decided by the voltage level of the input signal. For 1 V supply voltage, both transistors operate in active region when the input voltage changes between 0.4 V and 0.6 V. Two PMOS transistors, Qp1 and Qp2, are used in parallel to ensure their overall ON current is almost equal to that of a single NMOS transistor , Qn. The area of the SNT amplifier is 70 × 144 nm. The gate and source contacts for each transistor in this layout are doubled to reduce ohmic losses at these terminals which, otherwise, act as a degenerative factor to decrease the voltage gain of the amplifier.

Fig. 4.1

The SNT CMOS amplifier (a) layout and (b) low frequency small-signal model

The low frequency small-signal model of the amplifier, when both transistors operate in active region, is shown in Fig. 4.1b. In this figure, R_d represents the cumulative drain resistance and R_s is the cumulative source resistance given by R_sn = R_sx + R_sy + R_nw for the NMOS SNT and R_sp = R_sx + R_sy + R_pw for the PMOS SNT. The actual values are given in Chapter 3.

According to Fig. 4.1b, the low frequency small-signal gain of the CMOS amplifier is given by Eq. 4.1.

$${\mathrm{A}}_{\mathrm{v}0}=-\left[\frac{{\mathrm{g}}_{\mathrm{mn}}{\mathrm{r}}_{\mathrm{dsn}}}{{\mathrm{R}}_{\mathrm{n}}}+\frac{{\mathrm{g}}_{\mathrm{mp}1}{\mathrm{r}}_{\mathrm{dsp}1}}{{\mathrm{R}}_{\mathrm{p}1}}+\frac{{\mathrm{g}}_{\mathrm{mp}2}{\mathrm{r}}_{\mathrm{dsp}2}}{{\mathrm{R}}_{\mathrm{p}2}}\right]\left({\mathrm{R}}_{\mathrm{n}}/ /{\mathrm{R}}_{\mathrm{p}1}/ /{\mathrm{R}}_{\mathrm{p}2}\right) $$

(4.1)

where

$$ {\mathrm{R}}_{\mathrm{n}}={\mathrm{r}}_{\mathrm{dsn}}+{\mathrm{R}}_{\mathrm{sn}}+{\mathrm{R}}_{\mathrm{dn}}\approx {\mathrm{r}}_{\mathrm{dsn}} $$

(4.2)

and

$$ {\mathrm{R}}_{\mathrm{p}1}={\mathrm{r}}_{\mathrm{dsp}1}+{\mathrm{R}}_{\mathrm{sp}1}+{\mathrm{R}}_{\mathrm{dp}1}\approx {\mathrm{r}}_{\mathrm{dsp}1} $$

(4.3)

and

$$ {\mathrm{R}}_{\mathrm{p}2}={\mathrm{r}}_{\mathrm{dsp}2}+{\mathrm{R}}_{\mathrm{sp}2}+{\mathrm{R}}_{\mathrm{dp}2}\approx {\mathrm{r}}_{\mathrm{dsp}2} $$

(4.4)

Therefore, Eq. 4.1 can be rewritten as

$$ {\mathrm{A}}_{\mathrm{v}0}\approx -\left[{\mathrm{g}}_{\mathrm{mn}}+{\mathrm{g}}_{\mathrm{mp}1}+{\mathrm{g}}_{\mathrm{mp}2}\right]\left({\mathrm{r}}_{\mathrm{dsn}}/ /{\mathrm{r}}_{\mathrm{dsp}1}/ /{\mathrm{r}}_{\mathrm{dsp}2}\right) $$

(4.5)

Here, A_V0 is approximately equal to −6.9 with g_mn = 14 μA/V and g_mp1 = g_mp2 = 8 μA/V, r_dsn = 400 kΩ and r_dsp1 = r_dsp2 = 1.1 MΩ at V_ds = 0.5 V and V_gs = 0.5 V. The simplified low frequency voltage gain of the SNT CMOS amplifier becomes similar to the MOSFET amplifier gain when R_s ≪ 1/g_m ≪ r_ds is satisfied.

4.3.2 The Characteristics of the CMOS Amplifier

The frequency bandwidth and linearity are the two important figures of merit for an amplifier. When biased at V_gs = 0.5 V, the maximum gain of the CMOS amplifier becomes 20 × log (6.5) = 17 dB and the phase becomes 180° with a unity voltage gain cutoff frequency of 20 THz at a phase angle of 60° as shown in Fig. 4.2. The 3 dB frequency bandwidth of the amplifier is approximately 500 GHz and the power dissipation becomes 1.64 μW. The output spectrum of the amplifier in response to a two-tone test with 10 GHz spacing is shown in Fig. 4.3. The 2nd and 3rd harmonic distortion s , HD2 and HD3 tones, of the amplifier are 10 dB and 20 dB below the fundamental tones, respectively. The third order intermodulation distortions , IM3 tones, are 24 dB below the fundamentals for 10 mV input signal levels.

Fig. 4.2

The amplifier small-signal frequency response

Fig. 4.3

The amplifier two-tone output spectrum

The transfer function of the SNT CMOS amplifier including all parasitic resistors is given in Fig. 4.4a. Similarly, the slope of the transfer characteristics representing the DC voltage gain is shown in Fig. 4.4b. The large-signal transient response of this amplifier acting as an inverter is shown in Fig. 4.5. Seven inverters are cascaded in a closed loop feedback configuration to be able to obtain the input and the output waveforms of a single-stage amplifier in this figure. The initial condition of the circuit ensures self-oscillation with an oscillation frequency of 30 GHz. The gate delay of each SNT inverter is 2.2 ps; the rise and fall time s are 5.4 ps and 4.7 ps, respectively. These values are obtained by considering all parasitic values of the layout .

Fig. 4.4

The amplifier large-signal (a) transfer characteristic and (b) DC gain

Fig. 4.5

The amplifier large-signal transient response

The summary of the SNT amplifier characteristics is listed in Table 4.1.

Table 4.1 Characteristics of SNTs with BSIMSOI modeling

4.4 Differential SNT Amplifier

4.4.1 A Single-Stage Differential Amplifier Design

Operational amplifiers are one of the most useful building blocks in analog integrated circuit s . Since differential amplifier s occupy the input stage of any operational amplifier , their circuit characteristics and performance become crucial in an operational amplifier design. A typical differential amplifier with a current mirror circuit and its layout is shown in Fig. 4.6. The low frequency small-signal model of the amplifier is shown in Fig. 4.7.

Fig. 4.6

Differential SNT amplifier (a) layout and (b) schematic

Fig. 4.7

Low frequency small-signal model

In Fig. 4.7, the resistor R₃ is given by

$$ {\mathrm{R}}_3={\mathrm{R}}_{\mathrm{s}3}+\left({\mathrm{r}}_{\mathrm{ds}3}/ /\frac{1}{{\mathrm{g}}_{\mathrm{m}3}}\right) $$

(4.6)

For G_s ≫ g_m ≫ g_ds, the voltage gain is approximated by

$$ \frac{{\mathrm{V}}_{\mathrm{out}}}{{\mathrm{V}}_{\mathrm{in}}}\approx {\mathrm{g}}_{\mathrm{m}2}{\mathrm{r}}_{\mathrm{ds}2} $$

(4.7)

For G_s ≫ g_m ≫ g_ds, the output resistance is approximately given by

$$ {\mathrm{R}}_{\mathrm{out}}\approx \left[{\mathrm{r}}_{\mathrm{ds}2}\left(1+\frac{{\mathrm{g}}_{\mathrm{m}2}}{{\mathrm{g}}_{\mathrm{m}1}}\right)\right]/ /{\mathrm{r}}_{\mathrm{ds}4} $$

(4.8)

The layout of the differential pair amplifier in Fig. 4.6a is implemented by three metallization layers serving as local interconnects. All interconnect parasitic components are extracted and added to amplifier netlist for post-layout circuit simulations. The PMOS transistors at the inputs of the differential amplifier are implemented by a parallel combination of two PMOS SNTs to ensure a large transconductance . The width of the metal interconnects is selected to be 14 nm to reduce their resistivity and four vias are used to connect metal 2 and metal 3 layers to minimize the ohmic loss. Each 4 nm by 4 nm via offers 400 Ω resistance . A 14 nm by 14 nm overlap capacitance between metal 1 and metal 2 layers is 0.2 aF. The layout area of the differential amplifier occupies an area of 136 nm by 190 nm.

4.4.2 The Characteristics of the Differential Amplifier

The frequency response of the SNT differential pair amplifier is shown in Fig. 4.8. The amplifier provides a gain of 16 with the first pole located at 100 GHz and the second pole located at 100 THz. To attain high accuracy in the transfer function s of various analog circuits such as switch capacitor filters and amplifiers, it may be necessary to cascade multiple such amplifier stages in nested Miller architectures to be able to achieve a voltage gain higher than 1000.

Fig. 4.8

Amplifier small-signal frequency response

The spectrum of the output waveform of the amplifier is shown in Fig. 4.9. The amplifier produces good linearity with a total harmonic distortion of about 3 % for ±233 mV output swing. Such a high linearity is due to the source resistance , R_s, acting as the degeneration resistance and thereby minimizing the harmonic distortion of the differential PMOS SNTs at the input.

Fig. 4.9

Amplifier output spectrum

The summary of the single-stage SNT amplifier is listed in Table 4.2.

Table 4.2 Characteristics of the SNT differential pair amplifier

4.5 Multi-stage SNT Operational Amplifier

4.5.1 A Two-Stage Operational Amplifier Design

Intrinsic BSIMSOI transistor models are obtained after matching the input and output I–V characteristics of NMOS and PMOS SNTs with the I–V characteristics obtained from the three-dimensional device simulations as mentioned earlier. Parasitic RC components are subsequently added to the intrinsic models to create realistic extrinsic SPICE models used for circuit simulations. Chapter 3 shows the dominant RC parasitics of an SNT superimposed on its three-dimensional structure. In this figure, the parasitic capacitance between the source contact and the metal gate is denoted as C_gs2. The parasitic capacitance between the metal gate and the concentric source contact, C_gs1, is considered the largest dominant capacitor for the SNT. The gate-drain capacitors, C_gd1 and C_gd2, and the drain-source capacitors, C_ds1 and C_ds2, can be lumped together to form C_gd and C_ds, respectively. Compared to planar bulk transistors, C_gd produces a very small value. In addition, there is no junction to bulk capacitance; therefore, C_ds becomes quite linear [1–3]. The well resistance , R_s, can be large and is a major drawback in vertical SNTs compared to planar transistors. The magnitude of this resistance can be reduced drastically by placing a concentric (ring shape) source contact in parallel with the well as discussed in Chapter 3. If the transistor is properly designed to ensure G_s ≫ g_m ≫ g_ds (g_m is the intrinsic transconductance and g_ds is the intrinsic output conductance ), the performance of the vertical SNTs surpasses those of the planar transistors for analog circuits.

The simplified parasitic RC components of the NMOS and PMOS SNTs are shown in Fig. 4.10 with lumped capacitors of C_gd and C_ds.

Fig. 4.10

Simplified parasitic components of (a) NMOS and (b) PMOS SNTs

For simplified hand calculations and the amplifier AC parameters, the small-signal model in Fig. 4.11 can be used. This model is also helpful to compute the DC voltage gain and the output resistance of various amplifier stages at low frequencies.

Fig. 4.11

Linearized small-signal model of SNT

Operational amplifiers offer differential amplifier s at the input stage followed by common-source amplifiers, cascode amplifiers and common-drain amplifiers in the later stages. The operation and the characteristics of an SNT differential amplifier were studied in the previous section. According to this study, the differential amplifier produced a gain of 16 at the first pole located at 100 GHz. However, to achieve high accuracy in the transfer function s of switch capacitor filters and amplifiers, it is important that operational amplifier s provide a voltage gain higher than 1000. Therefore, using only one differential pair at the input stage is not sufficient to implement a high-gain voltage amplifier; additional amplifying stages are most likely required. The second amplifying stage can also be used to improve the phase margin of the operational amplifier and ensure stability when using the amplifier in a closed loop configuration.

Common-source amplifiers, cascode amplifiers or common-drain amplifiers are the types of the amplifiers that follow the differential amplifier as shown in Fig. 4.12. Before designing a multi-stage SNT operational amplifier , the characteristics and the performance figures of each type need to be investigated.

Fig. 4.12

Common-source, cascode, and common-drain amplifiers

Common-source amplifiers are used in the second stage of an operational amplifier and function as the Miller compensating stage. The low frequency small-signal model of the common-source amplifier is shown in Fig. 4.13.

Fig. 4.13

Low frequency small-signal model of the common-source amplifier

The Kirchoff’s current law at output branch results in

$$ {\mathrm{G}}_{\mathrm{s}2}{\mathrm{V}}_{\mathrm{gox}2}={\mathrm{G}}_{\mathrm{s}1}\left({\mathrm{V}}_{\mathrm{in}}-{\mathrm{V}}_{\mathrm{gox}1}\right) $$

(4.9)

The output voltage V_out can be expressed by

$$ {\mathrm{V}}_{\mathrm{out}}=\left(1+{\mathrm{r}}_{\mathrm{ds}1}{\mathrm{G}}_{\mathrm{s}1}\right){\mathrm{V}}_{\mathrm{in}}-\left[1+{\mathrm{r}}_{\mathrm{ds}1}\left({\mathrm{G}}_{\mathrm{s}1}+{\mathrm{g}}_{\mathrm{m}1}\right)\right]{\mathrm{V}}_{\mathrm{g}\mathrm{ox}1} $$

(4.10)

and

$$ {\mathrm{V}}_{\mathrm{out}}=-\left[1+{\mathrm{r}}_{\mathrm{ds}2}\left({\mathrm{G}}_{\mathrm{s}2}+{\mathrm{g}}_{\mathrm{m}2}\right)\right]{\mathrm{V}}_{\mathrm{g}\mathrm{ox}2} $$

(4.11)

Then the voltage gain of the common-source amplifier is given by

$$ \frac{{\mathrm{V}}_{\mathrm{out}}}{{\mathrm{V}}_{\mathrm{in}}}=\frac{-{\mathrm{g}}_{\mathrm{m}1}{\mathrm{r}}_{\mathrm{ds}1}\left[1+{\mathrm{r}}_{\mathrm{ds}2}\left({\mathrm{G}}_{\mathrm{s}2}+{\mathrm{g}}_{\mathrm{m}2}\right)\right]}{\left[1+{\mathrm{r}}_{\mathrm{ds}2}\left({\mathrm{G}}_{\mathrm{s}2}+{\mathrm{g}}_{\mathrm{m}2}\right)\left]+\frac{{\mathrm{G}}_{\mathrm{s}2}}{{\mathrm{G}}_{\mathrm{s}1}}\right[1+{\mathrm{r}}_{\mathrm{ds}1}\left({\mathrm{G}}_{\mathrm{s}1}+{\mathrm{g}}_{\mathrm{m}1}\right)\right]} $$

(4.12)

For G_s ≫ g_m ≫ g_ds, the voltage gain is approximately given by

$$ \frac{{\mathrm{V}}_{\mathrm{out}}}{{\mathrm{V}}_{\mathrm{in}}}=-{\mathrm{g}}_{\mathrm{m}1}\left({\mathrm{r}}_{\mathrm{ds}1}//{\mathrm{r}}_{\mathrm{ds}2}\right) $$

(4.13)

The intrinsic gain, g_m.r_ds, can be as high as 15 for a common-source amplifier and it is not enough to use it for the Miller stage. SNTs have very high unity -gain cutoff frequency and very low current handling capability. Therefore, using a large Miller capacitance is not feasible to achieve frequency compensation . Therefore, other amplifier structures which can provide much larger gain need to be investigated to implement the Miller stage.

A cascode amplifier, as the second alternative, inverts the input signal as a common-source amplifier but with a much larger gain. The low frequency small-signal model of the cascode amplifier is shown in Fig. 4.14.

Fig. 4.14

Low frequency small-signal model of the cascode amplifier

The Kirchoff’s current law at output branch results in

$$ {\mathrm{G}}_{\mathrm{s}3}{\mathrm{V}}_{\mathrm{gox}3}={\mathrm{G}}_{\mathrm{s}1}\left({\mathrm{V}}_{\mathrm{in}}-{\mathrm{V}}_{\mathrm{gox}1}\right) $$

(4.14)

The output voltage V_out can be expressed by

$$ {\mathrm{V}}_{\mathrm{out}}=-\left[1+{\mathrm{r}}_{\mathrm{ds}3}\left({\mathrm{G}}_{\mathrm{s}3}+{\mathrm{g}}_{\mathrm{m}3}\right)\right]{\mathrm{V}}_{\mathrm{g}\mathrm{ox}3} $$

(4.15)

and

$$ {\mathrm{V}}_{\mathrm{out}}={\mathrm{r}}_{\mathrm{ds}2}{\mathrm{G}}_{\mathrm{s}1}{\mathrm{V}}_{\mathrm{in}}-{\mathrm{r}}_{\mathrm{ds}2}{\mathrm{G}}_{\mathrm{s}1}{\mathrm{V}}_{\mathrm{g}\mathrm{ox}1}-\left(1+{\mathrm{r}}_{\mathrm{ds}2}{\mathrm{g}}_{\mathrm{m}2}\right){\mathrm{V}}_{\mathrm{g}\mathrm{ox}2} $$

(4.16)

where

$$ {\mathrm{V}}_{\mathrm{g}\mathrm{ox}2}=-\left[1+{\mathrm{G}}_{\mathrm{s}1}\left({\mathrm{r}}_{\mathrm{ds}1}+{\mathrm{R}}_{\mathrm{s}2}\right)\right]{\mathrm{V}}_{\mathrm{in}}+\left[1+{\mathrm{G}}_{\mathrm{s}1}\left({\mathrm{r}}_{\mathrm{ds}1}+{\mathrm{R}}_{\mathrm{s}2}\right)+{\mathrm{g}}_{\mathrm{m}1}{\mathrm{r}}_{\mathrm{ds}1}\right]{\mathrm{V}}_{\mathrm{g}\mathrm{ox}1} $$

(4.17)

The voltage gain of the cascode amplifier is given by

$$ \begin{array}{l}\frac{{\mathrm{V}}_{\mathrm{out}}}{{\mathrm{V}}_{\mathrm{in}}}=\frac{-{\mathrm{G}}_{\mathrm{s}1}\left[1+{\mathrm{r}}_{\mathrm{ds}3}\left({\mathrm{G}}_{\mathrm{s}3}+{\mathrm{g}}_{\mathrm{m}3}\right)\right]\left[\left(1+{\mathrm{g}}_{\mathrm{m}2}{\mathrm{r}}_{\mathrm{ds}2}\right)\left(2{\mathrm{R}}_{\mathrm{s}1}+2{\mathrm{R}}_{\mathrm{s}2}+{\mathrm{r}}_{\mathrm{ds}1}\left(2+{\mathrm{g}}_{\mathrm{m}1}{\mathrm{R}}_{\mathrm{s}1}\right)\right)\right]}{{\mathrm{G}}_{\mathrm{s}3}\left[\left(1+{\mathrm{g}}_{\mathrm{m}2}{\mathrm{r}}_{\mathrm{ds}2}\right)\left({\mathrm{R}}_{\mathrm{s}1}+{\mathrm{R}}_{\mathrm{s}2}+{\mathrm{r}}_{\mathrm{ds}1}\left(1+{\mathrm{g}}_{\mathrm{m}1}{\mathrm{R}}_{\mathrm{s}1}\right)\right)-{\mathrm{r}}_{\mathrm{ds}2}\right]-\left[1+{\mathrm{r}}_{\mathrm{ds}3}\left({\mathrm{G}}_{\mathrm{s}3}+{\mathrm{g}}_{\mathrm{m}3}\right)\right]}\hfill \end{array} $$

(4.18)

For G_s ≫ g_m ≫ g_ds, the voltage gain is approximated as

$$ \frac{{\mathrm{V}}_{\mathrm{out}}}{{\mathrm{V}}_{\mathrm{in}}}=\frac{-2{\mathrm{g}}_{\mathrm{m}2}{\mathrm{r}}_{\mathrm{ds}1}{\mathrm{r}}_{\mathrm{ds}2}{\mathrm{r}}_{\mathrm{ds}3}{\mathrm{G}}_{\mathrm{s}1}}{{\mathrm{g}}_{\mathrm{m}1}{\mathrm{g}}_{\mathrm{m}2}{\mathrm{r}}_{\mathrm{ds}1}{\mathrm{r}}_{\mathrm{ds}2}{\mathrm{R}}_{\mathrm{s}1}-{\mathrm{r}}_{\mathrm{ds}3}} $$

(4.19)

The voltage gain can be very high due to a small value in the denominator.

The output resistance of the cascode amplifier is given by

$$ {\mathrm{R}}_{\mathrm{out}}=\left[{\mathrm{R}}_{\mathrm{s}2}+{\mathrm{g}}_{\mathrm{m}2}{\mathrm{r}}_{\mathrm{ds}1}{\mathrm{r}}_{\mathrm{ds}2}\left(1+{\mathrm{g}}_{\mathrm{m}1}{\mathrm{R}}_{\mathrm{s}1}\right)\right]/ /\left[{\mathrm{r}}_{\mathrm{ds}3}\left(1+{\mathrm{g}}_{\mathrm{m}3}{\mathrm{R}}_{\mathrm{s}3}\right)\right] $$

(4.20)

For G_s ≫ g_m ≫ g_ds, the output resistance can be approximated as

$$ {\mathrm{R}}_{\mathrm{out}}\approx {\mathrm{r}}_{\mathrm{ds}3}\left(1+{\mathrm{g}}_{\mathrm{m}3}{\mathrm{R}}_{\mathrm{s}3}\right) $$

(4.21)

The SNT operational amplifier may have to drive high capacitive load s that belong to other analog stages. Therefore, it is very important to isolate the Miller stage from the load by using a buffer stage. A common-drain amplifier can be used for this purpose. The low frequency small-signal model of a common-drain buffer amplifier is shown in Fig. 4.15.

Fig. 4.15

Low frequency small-signal model of the buffer amplifier

The Kirchoff’s current law at output branch results in

$$ {\mathrm{G}}_{\mathrm{s}3}{\mathrm{V}}_{\mathrm{g}\mathrm{ox}3}=-{\mathrm{g}}_{\mathrm{ds}1}{\mathrm{V}}_{\mathrm{in}}+\left({\mathrm{g}}_{\mathrm{ds}1}+{\mathrm{g}}_{\mathrm{m}1}\right){\mathrm{V}}_{\mathrm{g}\mathrm{ox}1} $$

(4.22)

The output voltage V_out can be expressed by

$$ {\mathrm{V}}_{\mathrm{out}}=\left(1+{\mathrm{R}}_{\mathrm{s}1}{\mathrm{g}}_{\mathrm{ds}1}\right){\mathrm{V}}_{\mathrm{in}}-\left[1+{\mathrm{R}}_{\mathrm{s}1}\left({\mathrm{g}}_{\mathrm{m}1}+{\mathrm{g}}_{\mathrm{ds}1}\right)\right]{\mathrm{V}}_{\mathrm{g}\mathrm{ox}1} $$

(4.23)

and

$$ {\mathrm{V}}_{\mathrm{out}}=-\left(1+{\mathrm{r}}_{\mathrm{ds}2}{\mathrm{g}}_{\mathrm{m}2}\right){\mathrm{V}}_{\mathrm{g}\mathrm{ox}2}-{\mathrm{G}}_{\mathrm{s}3}{\mathrm{r}}_{\mathrm{ds}2}{\mathrm{V}}_{\mathrm{g}\mathrm{ox}3} $$

(4.24)

where

$$ {\mathrm{V}}_{\mathrm{g}\mathrm{ox}2}=-\left[1+{\mathrm{G}}_{\mathrm{s}3}\left({\mathrm{r}}_{\mathrm{ds}3}+{\mathrm{R}}_{\mathrm{s}2}\right)+{\mathrm{g}}_{\mathrm{m}3}{\mathrm{r}}_{\mathrm{ds}3}\right]{\mathrm{V}}_{\mathrm{g}\mathrm{ox}3} $$

(4.25)

The voltage gain of the amplifier is given by

$$ \frac{{\mathrm{V}}_{\mathrm{out}}}{{\mathrm{V}}_{\mathrm{in}}}=\frac{{\mathrm{g}}_{\mathrm{m}1}\left[-{\mathrm{r}}_{\mathrm{ds}2}+\left(1+{\mathrm{g}}_{\mathrm{m}2}{\mathrm{r}}_{\mathrm{ds}2}\right)\left({\mathrm{r}}_{\mathrm{ds}3}+{\mathrm{R}}_{\mathrm{s}2}+{\mathrm{R}}_{\mathrm{s}3}+{\mathrm{g}}_{\mathrm{m}3}{\mathrm{r}}_{\mathrm{ds}3}{\mathrm{R}}_{\mathrm{s}3}\right)\right]}{1+\left({\mathrm{g}}_{\mathrm{m}1}+{\mathrm{g}}_{\mathrm{ds}1}\right)\left[{\mathrm{R}}_{\mathrm{s}1}-{\mathrm{r}}_{\mathrm{ds}2}+\left(1+{\mathrm{g}}_{\mathrm{m}2}{\mathrm{r}}_{\mathrm{ds}2}\right)\left({\mathrm{r}}_{\mathrm{ds}3}+{\mathrm{R}}_{\mathrm{s}2}+{\mathrm{R}}_{\mathrm{s}3}+{\mathrm{g}}_{\mathrm{m}3}{\mathrm{r}}_{\mathrm{ds}3}{\mathrm{R}}_{\mathrm{s}3}\right)\right]} $$

(4.26)

For G_s ≫ g_m ≫ g_ds, the voltage gain is approximated as

$$ \frac{{\mathrm{V}}_{\mathrm{out}}}{{\mathrm{V}}_{\mathrm{in}}}\approx \frac{{\mathrm{g}}_{\mathrm{m}1}}{{\mathrm{g}}_{\mathrm{m}1}+{\mathrm{g}}_{\mathrm{ds}1}} $$

(4.27)

and this value is very close to unity .

The output resistance of the amplifier is given by

$$ {\mathrm{R}}_{\mathrm{out}}=\left[{\mathrm{R}}_{\mathrm{s}1}+\left({\mathrm{r}}_{\mathrm{ds}1}/ /\frac{1}{{\mathrm{g}}_{\mathrm{m}1}}\right)\right]/ /\left({\mathrm{g}}_{\mathrm{m}2}{\mathrm{r}}_{\mathrm{ds}2}{\mathrm{r}}_{\mathrm{ds}3}\right) $$

(4.28)

For G_s ≫ g_m ≫ g_ds, the output resistance is approximated as

$$ {\mathrm{R}}_{\mathrm{out}}\approx \frac{1}{{\mathrm{g}}_{\mathrm{m}1}} $$

(4.29)

and this value becomes very small.

Therefore, a high performance SNT operational amplifier can be implemented by a differential amplifier at the input stage, a cascode amplifier in the second stage and a common-drain amplifier in the final buffer stage as shown in Fig. 4.16.

Fig. 4.16

The schematic of the two-stage operational amplifier

The biasing control resistance , R₀, is adjusted to create a reference current of 670 μA for I_ds13, I_ds23, I_ds43, and I_ds51, and 1.4 mA for I_ds33 in the current mirror circuit.

The overall low frequency voltage gain of the operational amplifier is given by

$$ \frac{{\mathrm{V}}_{\mathrm{out}}}{{\mathrm{V}}_{\mathrm{in}}}\approx {\mathrm{g}}_{\mathrm{m}34}{\mathrm{r}}_{\mathrm{ds}34}\frac{-2{\mathrm{g}}_{\mathrm{m}42}{\mathrm{r}}_{\mathrm{ds}41}{\mathrm{r}}_{\mathrm{ds}42}{\mathrm{r}}_{\mathrm{ds}43}{\mathrm{G}}_{\mathrm{s}41}}{\left({\mathrm{g}}_{\mathrm{m}41}{\mathrm{g}}_{\mathrm{m}42}{\mathrm{r}}_{\mathrm{ds}41}{\mathrm{r}}_{\mathrm{ds}42}{\mathrm{R}}_{\mathrm{s}41}-{\mathrm{r}}_{\mathrm{ds}43}\right)}\frac{{\mathrm{g}}_{\mathrm{m}53}}{\left({\mathrm{g}}_{\mathrm{m}53}+{\mathrm{g}}_{\mathrm{ds}53}\right)} $$

(4.30)

The location of the first pole is given by

$$ {\mathrm{f}}_{\mathrm{L}}\approx \frac{1}{2{\uppi \mathrm{C}}_1\frac{2{\mathrm{g}}_{\mathrm{m}42}{\mathrm{r}}_{\mathrm{ds}41}{\mathrm{r}}_{\mathrm{ds}42}{\mathrm{r}}_{\mathrm{ds}43}{\mathrm{G}}_{\mathrm{s}41}}{\left({\mathrm{g}}_{\mathrm{m}41}{\mathrm{g}}_{\mathrm{m}42}{\mathrm{r}}_{\mathrm{ds}41}{\mathrm{r}}_{\mathrm{ds}42}{\mathrm{R}}_{\mathrm{s}41}-{\mathrm{r}}_{\mathrm{ds}43}\right)}\left[{\mathrm{r}}_{\mathrm{ds}34}\left(1+\frac{{\mathrm{g}}_{\mathrm{m}34}}{{\mathrm{g}}_{\mathrm{m}32}}\right)/\kern-0.25em /{\mathrm{r}}_{\mathrm{ds}31}\right]} $$

(4.31)

and the location of the second pole determined by the load capacitor is given by

$$ {\mathrm{f}}_{\mathrm{H}}\approx \frac{{\mathrm{g}}_{\mathrm{m}53}}{2{\uppi \mathrm{C}}_0} $$

(4.32)

The slew rate (SR) is computed as

$$ \mathrm{S}\mathrm{R}\approx \frac{{\mathrm{I}}_{\mathrm{ds}33}}{{\mathrm{C}}_1} $$

(4.33)

4.5.2 Characteristics of the Operational Amplifier

The impact of the Miller capacitance on the location of the poles and its effect on the frequency response of the compensated and uncompensated operational amplifier s are shown in Fig. 4.17. The lead compensation produced by a series combination of a resistor, R₁, and a capacitor, C₁, helps to improve the unity voltage gain cutoff frequency of the operational amplifier without dissipating any power.

Fig. 4.17

Compensated and uncompensated (a) gain magnitude and (b) phase response of the SNT opamp

The layout of the SNT operational amplifier is shown in Fig. 4.18. The input transistors in the differential amplifier are implemented by a parallel combination of three PMOS SNTs to produce large transconductance and to be able to construct the Miller stage with NMOS SNTs. The biasing control resistor, R₀, is realized by an 8 nm wide and 320 nm long N-well. The frequency compensation is achieved by using a resistor, R₁, and a capacitor, C₁. In the compensation circuit, C₁ is implemented by 150 nm wide and 63 nm long metal 1 and metal 2 interconnect sandwich with 36 nm spacing. The resistor R₁ is implemented by 8 nm wide and 48 nm long N-well. The width of the metal interconnects is selected to be 14 nm to reduce the overall resistance , and four parallel vias are used to connect metal 1 layer to metal 2 layer to minimize the ohmic loss. Each 4 nm by 4 nm via produces 400 Ω. Each 14 nm by 14 nm overlap capacitance formed between metal 1 and metal 2 layers is 0.2 aF. The layout area of the operational amplifier including the biasing circuit and all compensation components occupies an area of 330 nm by 250 nm.

Fig. 4.18

The layout of the SNT operational amplifier

The post-layout frequency response of the SNT operational amplifier is shown in Fig. 4.19. This amplifier reveals a high unity voltage gain cutoff frequency at 5.1 THz but only dissipates 7.2 μW. The operational amplifier has a phase margin better than 90° for frequencies less than 1 THz and achieves a very stable operation.

Fig. 4.19

Frequency response of the SNT operational amplifier

The open loop transient response of the operational amplifier is shown in Fig. 4.20. The low frequency voltage gain of the amplifier is approximately 7760. For an input swing with 30 μV peak amplitude, the output of the amplifier produces 233 mV. The operational amplifier has good linearity characteristics and exhibits a total harmonic distortion of 3 % for ±233 mV output swing. This high linearity can be attributed to the source resistance , R_s, acting as the degeneration resistance, minimizing the harmonic distortions of each amplifier stage.

Fig. 4.20

Transient input and output waveforms of the operational amplifier

The Common-Mode Rejection Ratio (CMRR ) and the Power Supply Rejection Ratio (PSRR ) of the operational amplifier are shown in Fig. 4.21. The CMRR has a corner frequency at 100 GHz and the PSRR has a corner frequency at 1 GHz. The CMRR achieves 40 dB and the PSRR achieves 54 dB signal rejection.

Fig. 4.21

(a) CMRR and (b) PSRR of the operational amplifier

The post-layout characteristics of the operational amplifier are listed in Table 4.3.

Table 4.3 Post-layout characteristics of the two-stage SNT operational amplifier

4.6 Summary

The single-stage CMOS amplifier is a simple but a good circuit platform to show the capabilities of SNTs in large-signal and small-signal AC domains. In large-signal domain when the amplifier is used as an inverter , the circuit reveals 2.2 ps delay, 5.4 ps rise time and 4.7 ps fall time while oscillating at 30 GHz. In small-signal domain, the amplifier acts as a common-source amplifier if a proper DC level is introduced and a small AC source is applied to the input. When used as a single-stage common-source amplifier, the circuit dissipates 1.64 μW total power and produces a 500 GHz bandwidth with a −6.5 gain. The third order intermodulation distortion tones for a two-tone input signal become −24 dBm with 10 mV amplitude and 10 GHz frequency spacing.

Differential pair amplifiers provide unique circuit characteristics compared to all the other amplifier structures. Because there are two different AC signal paths from input to output, the gain of an amplifier in differential mode is much higher compared to the gain of an amplifier in common mode. This type also eliminates the amplification of noise and cross-talk because of the differential inputs. Besides high gain and low power, differential SNT amplifiers can achieve a very high common-mode rejection ratio which makes them good candidates for implementing operational amplifier s. The differential amplifier studied in this chapter dissipates 5 μW power and produces a 5 THz bandwidth with a voltage gain of 16. It produces a linear output voltage swing of 0.5 V and a total harmonic distortion better than 3 % from a 1.8 V power supply and a 20 aF capacitive load . The second and third order harmonic distortions of the amplifier are −40 and −52 dBm, respectively, and the third order intermodulation is −24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing.

The SNT operational amplifier consists of a differential amplifier at the input stage followed by a cascode amplifier. A common-drain amplifier can be used as a third stage in an operational amplifier to isolate the Miller stage from the load. This buffer stage also decreases the output impedance to be able to drive low resistive loads. The amplifier is frequency compensated for oscillation -free, stable operation with a 1.8 V power supply. It has a voltage gain of 40 dB and a phase margin of 42°. The current gain cutoff frequency is 5.1 THz and the amplifier produces 40 dB common-mode rejection ratio and 54 dB power supply rejection ratio with a slew rate of 2 V/ns. The layout area of a typical SNT operational amplifier is 320 nm by 250 nm.