Wideband Phase-Locked-Loop-Based Frequency Synthesis

Abstract

Frequency synthesizers in cognitive radio play a central role in providing the local oscillator (LO) signal for frequency translation and channel scanning. At the heart of the frequency synthesizer is the phase-locked loop (PLL). In this chapter, frequency synthesizer design requirements including frequency range and phase noise performance are first given. This is followed by detailed analysis of both integer-N PLL and ΣΔ fractional-N PLL. Sources of phase noise in PLL design are detailed along with a methodology to minimize the phase noise. Design details of important PLL components such as the charge pump, the voltage-controlled oscillator (VCO) and the feedback frequency divider are given.

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Frequency synthesizers in cognitive radio play a central role in providing the local oscillator (LO) signal for frequency translation and channel scanning. At the heart of the frequency synthesizer is the phase-locked loop (PLL). In this chapter, frequency synthesizer design requirements including frequency range and phase noise performance are first given. This is followed by detailed analysis of both integer-N PLL and ΣΔ fractional-N PLL. Sources of phase noise in PLL design are detailed along with a methodology to minimize the phase noise. Design details of important PLL components such as the charge pump, the voltage-controlled oscillator (VCO) and the feedback frequency divider are given.

6.1 Jitter and Phase Noise Primer

Before starting a detailed discussion on PLL design and how to optimize its performance, a few terms must first be defined. The two most prevalent terms describing the performance of PLLs are phase noise and jitter. Jitter can be defined as the statistical measure of the deviation of a periodic signal’s actual edges corrupted by noise from the ideal periodic signal. The corruption of the edges is due to amplitude noise (either external or intrinsic to the PLL circuitry) conversion into phase noise (AM–PM conversion of noise), the distinction between amplitude and phase noise is shown graphically in Fig. 6.1.

Fig. 6.1

Illustration of sine wave corrupted by a amplitude noise and b phase noise

Jitter can be deterministic or random. Deterministic jitter occurs in a predictable and periodic fashion. Random jitter at any given time is uncorrelated to any other sample. Phase noise is the frequency representation of phase fluctuations of a signal. Figure 6.2 illustrates both deterministic and random jitter in both the time and frequency domains. As the figure shows, deterministic jitter manifests itself as spurious response in the frequency domain. Random jitter manifests itself as a continuous function. The exact shape of this response is typical of a PLL phase noise plot as will be explained in Sect. 6.3.

Fig. 6.2

Time domain and frequency domain representation of a deterministic jitter and b random jitter

There are several definitions of jitter [1]. Absolute jitter is the difference between the minimum clock period corrupted by noise from the ideal clock period. This definition is useful for digital application that requires timing closure. The RMS jitter is the root mean square summation of all the phase deviations that occur in each clock cycle. This measure is useful for quantifying random jitter. Peak-to-peak jitter is the difference between the maximum clock period and minimum clock period; useful when quantifying deterministic jitter. Cycle-to-cycle jitter is the clock variation between two clock edges. This metric is useful in serial links applications.

There are many sources of jitter. Some noise sources are generated the by PLL itself. This category of noise sources is referred to as intrinsic noise sources. The voltage and current noise sources of the individual components of the PLL (transistors and resistors, for example) give rise to amplitude noise. This amplitude noise undergoes an amplitude-to-phase (AM–PM) conversion of noise. One such example of AM–PM conversion of noise in digital logic (such as frequency dividers) is the altering of zero crossings by amplitude shifts as illustrated in Fig. 6.3. In this case, amplitude noise occurring during the waveform transitions is translated into jitter. There are other mechanisms that translate amplitude noise into jitter as will be demonstrated later.

Fig. 6.3

Conversion of AM–PM noise by altering zero crossing time

The other category of noise is due to environmental disturbances around the PLL. This is known as extrinsic noise. Power supply and ground bounces that shift the internal bias operating points or digital circuit’s zero crossing point can cause phase noise. Crosstalk and noise pickup from adjacent circuitry can induce jitter. As with the case of intrinsic sources of noise, external noise source also undergo an AM–PM conversion of noise which results in jitter. External noise sources can be mitigated by improving the power supply rejection of the PLL power supplies as well as proper layout shielding.

The relationship between jitter and phase noise is important to understand. A sine wave corrupted by jitter can be given as

$$ v(t )=V\cdot \cos [{{\omega }_{0}}t+{{n}_{2}}(t ) ] $$

(6.1)

where ω₀ is the angular frequency of the LO signal. Now, consider the special case where n₂(t) is a single tone expressed as

$$ {{n}_{2}}(t )=\frac{\Delta f}{{{f}_{m}}}\sin {{\omega }_{m}}t={{\theta }_{p}}\cdot \sin {{\omega }_{m}}t $$

(6.2)

where θ_p is the frequency modulation index and ω_m is the angular frequency of the tone considered for this analysis. Substituting (6.2) into (6.1) and expanding yields

$$ v(t )=V\cdot \left\{\cos {{\omega }_{0}}t\cos [{{\theta }_{p}}\sin {{\omega }_{m}}t ]-\sin {{\omega }_{0}}t\sin [{{\theta }_{p}}\sin {{\omega }_{m}}t ] \right\} $$

(6.3)

If it is assumed that θ_p< < 1 (i.e., small phase noise), then

$$ \cos ({{\theta }_{p}}\sin {{\omega }_{m}}t )\approx 1 $$

(6.4)

and

$$ \sin [{{\theta }_{p}}\sin {{\omega }_{m}}t ]\approx {{\theta }_{p}}\sin {{\omega }_{m}}t $$

(6.5)

therefore, substituting (6.4) and (6.5) into (6.3) and expanding yields

$$ v(t )=V\cdot \left\{\cos {{\omega }_{0}}t-\frac{{{\theta }_{p}}}{2}[\cos ({{\omega }_{0}}-{{\omega }_{m}})t-\cos ({{\omega }_{0}}+{{\omega }_{m}})t ] \right\} $$

(6.6)

The analysis resulting in (6.6) shows that a frequency-modulated single-tone jitter source results in a pair of tones in the frequency domain centered around the LO frequency with amplitude ${}^{1}\!\!\diagup\!\!{}_{2}\;\cdot V\cdot {{\theta }_{p}}$. The single sideband phase noise can now be expressed as

$$ L({{f}_{m}})={{\left(\frac{{{v}_{n}}}{V} \right)}^{2}}=\frac{\theta_{p}^{2}}{4}=\frac{\theta_{rms}^{2}}{2} $$

(6.7)

The above analysis shows the relationship of a single tone in the phase noise plot to the jitter. In reality, the phase noise plot is a continuous spectrum, as shown in Fig. 6.2b. The tonal analysis resulting in (6.6) can be considered to be the impact of phase noise over a 1-Hz bandwidth. The phase noise plot can be integrated over the desired bandwidth to yield value for the jitter. Since, by definition, jitter is a statistical value and it is assumed that jitter from a phase noise plot is the result of random noise, the summation must be done in a root-mean-square fashion. This means that the rms jitter (in units of seconds), t_{j, rms}, is given as

$$ {{t}_{j,rms}}=\frac{1}{2\pi {{f}_{0}}}\sqrt{2\int_{{{f}_{1}}}^{{{f}_{2}}}{L(f )df}}$$

(6.8)

6.2 Requirements

The phase noise of the PLL is an important parameter in any wireless transceiver. It serves as the LO port in both the downconverter mixer or upconverter mixers, affecting the performance of both the transmit and receive paths. The PLL is also used as a sampling clock to both the analog-to-digital converter (ADC) in the receive path and the digital-to-analog converter (DAC) in the transmit path, affecting the performance of both paths.

There are two phenomena that determine the phase noise requirement of the PLL when it is used as an LO signal. The first of these is known as reciprocal mixing [2]. It has been demonstrated in Chap. 3 that it is possible for two blockers to cross-modulate and produce an undesired signal that lands on the receiver channel. Since there is a finite amount of phase noise at any frequency offset away from the LO frequency, there will be a component of the LO phase noise that mixes with a large blocker back into the desired receive channel. This noise translation may limit the noise floor of the receiver if the LO phase noise at a certain offset frequency is too high.

The reciprocal mixing effect is shown graphically in Fig. 6.4. The phase noise profile is simplified as a triangular shape centered around LO. An IF receiver is ­assumed in this plot, meaning that the desired channel is offset away from the LO frequency by an amount equal to IF, or Δf as shown in Fig. 6.4. An undesired blocker, located at f_bl mixes with the LO phase noise located at Δf away from the blocker to downconvert a portion of the blocker set by the phase noise level. In order for the phase noise to not cause any degradation, the maximum phase noise level must be

Fig. 6.4

The reciprocal mixing effect in a receiver

$$ PN<{{P}_{ch}}-{{P}_{bl}}-SN{{R}_{desired}}-margin-10{{\log }_{10}}BW\ (\text{dB}) $$

(6.9)

where P_ch is the channel power level, P_bl is the blocker power level, SNR_desired is the SNR required by the standard, the margin is usually set to 10 dB, and BW is the bandwidth (in Hertz). The phase noise of (6.9) is expressed in dBc, relative to the amplitude of the LO signal. The phase noise is specified at a frequency offset, Δf₁, away from the LO center frequency. All blocker profiles must be evaluated to ensure that the worst case phase noise is specified and met.

Another transceiver requirement that places a specification on the phase noise requirement on the PLL is that of the error vector magnitude (EVM) [3]. As stated in Chap. 5, the EVM can be stated as a percentage. The EVM can be a result of many sources, one being the phase noise of the LO. As a result, the EVM specification determines the rms jitter contribution of the PLL, with the phase noise integration band being the bandwidth of the output signal to be transmitted.

The PLL can also be used as a sampling clock for the data converters in the wireless transceiver. The jitter requirement in this case is called aperture jitter [4]. This jitter is also an rms jitter than is integrated over the bandwidth of the output signal to be transmitted. The jitter requirement is given as

$$ {{t}_{j,rms}}=\frac{{{10}^{-\frac{SNR}{20}}}}{2\pi {{f}_{BW}}}$$

(6.10)

where f_BW is the signal bandwidth, SNR is the desired signal-to-noise ratio in dB. The aperture jitter requirement can be derived from analyzing how much amplitude variation is due to clock phase variation (PM–AM conversion), as shown in Fig. 6.5.

Fig. 6.5

Jitter resulting in voltage variation in a data converter

In the case of a radio frequency digital-to-analog converter (RFDAC), the SNR requirement is driven by the adjacent channel power ratio (ACPR) specification. The SNR requirement for RFDAC may be in excess of 70 dB. Figure 6.6 shows the rms jitter requirement on the sampling clock. As the signal bandwidth approaches 100 MHz, the jitter requirement approaches the 100 fs barrier. The aperture jitter value, however, is a worst case analysis. In reality, the jitter number can be substantially relaxed. Although the worst case bandwidth is used in (6.10), in reality small amount of signal power may actually be present at higher frequencies of the data signal. This fact has been used extensively in wide data bandwidth applications to ease the jitter specification [5]. Realistic jitter specifications are usually obtained through simulations with typical data patterns.

Fig. 6.6

RMS jitter requirement versus input signal bandwidth and SNR

6.3 Phase-Locked Loops (PLL) Primer

The most popular method of generating an on-chip programmable frequency is through the use of a PLL. The PLL frequency synthesis is a form of indirect frequency synthesis, where a low-frequency spectrally pure clock source is used to generate an intermediate voltage than a higher-frequency clock source. The generated clock source is frequency and phase locked to the low-frequency clock source to maintain its spectral purity.

6.3.1 Integer PLL

The most popular form of PLLs used today is the single-loop charge-pump-based PLL [6], shown in Fig. 6.7. The on-chip clock source is generated by a voltage-controlled oscillator (VCO). A VCO produces an output frequency that is proportional to its input voltage level. The VCO output signal is frequency divided by a feedback divider, L, and brought down to the same frequency as the external low-frequency spectrally pure clock source. The phases of the two signals are compared by a phase-frequency detector (PFD) that generates a pair of signals, UP and DN. The UP and DN signals then turn on either a positive or negative current, respectively, for a brief amount of time to adjust the passive loop filter’s voltage. The loop filter filters the voltage excursions caused by abruptly turning the current sources on and off and loop filter output voltage is then used to control the frequency of the VCO directly.

Fig. 6.7

An charge-pump integer-N PLL

When the PLL is near lock, the phase deviations detected by the PFD are small and the loop can be linearized. Such a linear model is called the linear phase model of the PLL, where input and output phases, not frequency, are observed. The phase transfer function from input REF to the PLL output can be given as

$$ H(s )=\frac{\left(\frac{{{I}_{p}}}{2\pi } \right)(2\pi {{K}_{vco}}/s )F(s)}{1+\left(\frac{{{I}_{p}}}{2\pi } \right)(2\pi {{K}_{vco}}/s )F(s)/L} $$

(6.11)

where the linear model for the PFD and charge pump is ${{K}_{d}}=\frac{{{I}_{p}}}{2\pi }$ in units of A/rad. The linear model for the VCO gain is ${{K}_{v}}=2\pi {{K}_{vco}}/s$ in units of rad/V. Note that an integrating 1/s in K _v is necessary to translate the output frequency of the VCO into phase. F(s) is the linear transfer function of the loop filter, which is given as

$$ F(s )=\frac{s+\frac{1}{{{R}_{2}}{{C}_{2}}}}{{{C}_{1}}{{R}_{3}}{{C}_{3}}s\left[s+\frac{1}{{{R}_{2}}{{C}_{1}}}\left(1+\frac{{{C}_{1}}}{{{C}_{2}}}\right) \right]\cdot \left[s+\frac{1}{{{R}_{3}}{{C}_{3}}}\right]} $$

(6.12)

As implied by Fig. 6.7 and (6.11) and (6.12), the loop contains two integrators: one from the VCO and another from the loop filter. This means that the loop is able to correct for any phase or frequency steps with no residual error. The H(s) transfer function as shown in (6.11) is a low-pass filter response.

The additional poles introduced by C1 and the R3–C3 pair serve to remove any voltage ripples, as will be seen in Sect. 6.4. These poles are usually spaced a decade apart in order to avoid stability issues [7]. Without these branches, (6.11) becomes a second-order system. Reducing the system down to a second-order system has the advantage of providing closed-form design equations that can be used to optimize the PLL parameters. Two parameters that are used to describe a second-order system are the natural frequency and damping ratio, which for a second-order linear PLL are given as

$$ {{\omega }_{n}}=\sqrt{\frac{{{K}_{vco}}{{I}_{p}}}{NC}}$$

(6.13)

and

$$ \zeta =\frac{{{\omega }_{n}}RC}{2}, $$

(6.14)

respectively. The resulting bandwidth of the PLL (ignoring the higher order poles) becomes

$$ {{f}_{3dB}}=\frac{{{\omega }_{n}}}{2\pi }\sqrt{2{{\zeta }^{2}}+1+\sqrt{{{(2{{\zeta }^{2}}+1 )}^{2}}+1}}\ (\text{Hz}) $$

(6.15)

Using (6.14), (6.15) can be approximated as

$$ {{f}_{3dB}}\cong \frac{1}{2\pi }\frac{{{K}_{vco}}{{I}_{p}}R}{N}\ (\text{Hz}) $$

(6.16)

Another important point to note is that the PLL is a time-sampled system. More specifically, the PFD updates the loop once every reference cycle. The PLL, however, can still be treated as a continuous time system if the PFD update rate far exceeds to the loop bandwidth of the PLL. A reference frequency to PLL bandwidth ratio of greater than 10 is usually recommended.

6.3.2 ΣΔ Fractional-N PLL

The integer PLL described above is capable of producing any output frequency that is a multiple of the input frequency. The ratio of output frequency to input frequency is L. If L is a programmable parameter, then the PLL can, in theory, produce any integer multiple of the frequency of the input clock source, REF. In direct conversion receivers, if the LO is set to the desired RF frequency, then minimum step size of the LO is equal to one channel frequency. This presents two challenges. First, the input frequency to the PLL is restricted to be one channel wide. This can severely limit the performance of the PLL especially for narrow bandwidth transmissions, as is shown in Sect. 6.4. Second, the RF transceiver may be required to support multiple standards, making it nearly impossible to synthesize any output frequency from a single crystal source.

One solution to providing LO support to multiple standards is to construct a PLL that is capable of generating any output frequency, irrespective of the input frequency. One method of achieving this goal is to replace the integer-L feedback divider with a fractional divider. A fractional divider is actually an integer divider, which has a dynamic division ratio that toggles between two (or more) integer values. The toggling is performed in such a way that the average division ratio is equal to the desired fractional ratio. Consider, for example, a case where a fractional division ratio of L = 63.25 is desired. The feedback divider value will be set to {64,63,63,63} for four consecutive cycles and the sequence is repeated. The averaging operation is approximated by the low-pass response of the PLL. In general, if the denominator of the fractional ratio is equal to 2 ^N, then the PLL closed loop bandwidth must be set to less than F_REF/2^N to filter out the spurious response of the repeated sequence. Figure 6.8 shows a simulation plot of the output spectrum of PLL centered around 2.5075 GHz. The fractional ratio is equal to 3/2^3 =3/8 and the reference frequency is 20 MHz. As the figure shows fractional spurs occur at 2.5 MHz intervals apart, it corresponds to 1/2³ times the reference frequency. In this case, the denominator of the fractional ratio is small. In a more practical scenario, the value of N can easily be 20–30. This results in fractional spurs occurring much closer in frequency to the LO carrier signal.

Fig. 6.8

Output spectrum of a fractional-N PLL

The implementation of a basic fractional-N divider is fairly straightforward. ­Figure 6.9 shows a fractional-N PLL with a fractional divider [8]. The division ratio is dithered between two values: L and L + 1. The control signal to change the division ratio comes from the “carry out” port of an accumulator. If the bit width of the accumulator is N, the denominator of the fractional value is 2^N. The numerator is set by an external control word, fn. The input clock signal for the accumulator is from the output of the feedback divider itself (as opposed to the REF signal directly). This is done in order to synchronize the modification of the feedback division ratio with the feedback divider itself. This is crucial in order to avoid metastability errors in the feedback divider.

Fig. 6.9

Basic fractional-N PLL architecture

An example of how the accumulator control the feedback division ratio is shown in Fig. 6.10. In this example, 3-bit accumulator is assumed and fn = 3. In this case, the desired fractional value is 3/8. As the figure shows, as the clock is toggled, the contents of the accumulator are incremented in a modulo fashion. When the accumulator overflows, the Carry Out signal is asserted incrementing the feedback ­division ratio by 1. The sequence shown is repeated indefinitely with repetition length of 8 cycles. This gives rise to the fractional spurs appearing at intervals of f_REF/8. The average division ratio then becomes L + 3/8.

Fig. 6.10

Typical waveforms for a fractional ratio of fn = 3/8

As stated earlier, the fractional spurs can occur at very low offset frequencies from the carrier. Lowering the bandwidth to filter out the fractional spurs would be impractical and the resulting jitter performance of the PLL would be poor. An alternative method of generating a fractional divider is to use a sigma–delta (ΣΔ) modulator instead of an accumulator, as shown in Fig. 6.11 [9]. Comparing Fig. 6.9 to Fig. 6.11 shows that the L divider has been replaced by a multi-modulus divider (MMD). From a functional point of view, the main difference between an L divider and an MMD is that the MMD division ratio is dithered over a wider range. From an implementation point of view, the dividers are identical.

Fig. 6.11

ΣΔ fractional-N PLL architecture

A sigma–delta modulator randomizes the fractional sequence shown in Fig. 6.10. This randomization is done in such a way that the spurs are translated into high-frequency noise. The low-pass filter closed-loop response of the PLL then filters the high-frequency noise. To understand how this operates, consider a generic first-order sigma–delta modulator, shown in Fig. 6.12. The quantizer would be equivalent to the Carry Out signal shown in Fig. 6.10. Obtaining a closed-form expression for this loop is difficult due to the nonlinear quantizer. If it is assumed that there is sufficient activity at the output of the integrator, the toggling of the quantizer output can be approximated as a random process. In this case, the quantization error can be assumed to be a random additive error to the integrator output. This results in the linear model shown in Fig. 6.13. The term K is a gain factor associated with the integrator.

Fig. 6.12

First-order sigma–delta modulator

Fig. 6.13

Linear model of a sigma–delta modulator

The transfer function from x(t) to y(t) is called the signal-transfer function (STF) and is given as

$$ STF=\frac{K}{s+K} $$

(6.17)

and the transfer function from the quantization noise, n_q(t) to the output is known as the noise-transfer function (NTF) and is given by

$$ NTF=\frac{s}{s+K} $$

(6.18)

Analysis of (6.17) and (6.18) reveals an interesting fact. The frequency response of the STF is a low-pass filter, with a passband gain of 0 dB and cutoff frequency of K rad/s. The frequency response of the NTF is a high-pass filter with a passband gain of 0 dB and cutoff frequency of K rad/s. Since the final output y(t) is the sum of the STF and NTF, the high-frequency content of y(t) is the undesired quantization noise; whereas the low-frequency content of y(t) is the desired signal. For this reason, a sigma–delta modulator is usually followed by a low-pass filter in order to filter out the undesired quantization noise.

As stated earlier, the quantization noise is considered to be a random process that is uniformly distributed. Since the probability density function is uniformly distributed from −Δ/2 to Δ/2 (where Δ is the quantizer step size), summing the pdf over this interval yields the quantization noise level, which is given as

$$ q_{n}^{2}=\frac{1}{\Delta }\int_{-\Delta /2}^{\Delta /2}{{{x}^{2}}dx}=\frac{{{\Delta }^{2}}}{12} $$

(6.19)

A popular method of generating a high-resolution sigma–delta modulator is to cascade several first-order modulators together, as shown in Fig. 6.14. The ­configuration in Fig. 6.14 is known as a MASH111 sigma–delta modulator [10] and is a cascade of three first-order modulators. Several stages are cascaded together to improve the quantization noise floor of the sigma–delta modulator. The input fn is the input analog signal to the ΣΔ modulator. s₁ is the digital output of the first stage modulator and can be given as

Fig. 6.14

A MASH111 sigma–delta modulator

$$ {{s}_{1}}=fn+{{q}_{n1}}(1-{{z}^{-1}})a $$

(6.20)

where q_n1 is the quantization noise and is shaped by a digital high-pass filter 1−z⁻¹. The quantization error, q_n1, can be extracted by subtracting the output of the quantizer from its input. Since the output is in digital form, it must first be translated into an analog signal using a 1-bit digital-to-analog converter (DAC), as shown in Fig. 6.14. The quantization error from the first stage is now the input to the second stage modulator. The output of the second stage is given as

$$ {{s}_{2}}={{q}_{n1}}+{{q}_{n2}}(1-{{z}^{-1}}) $$

(6.21)

A similar expression is derived for s₃, the output of the third modulator stage. The output of each modulator stage is first differentiated then added to the stage preceding it. The output can then be expressed as

$$ s=fn+{{q}_{n1}}(1-{{z}^{-1}})+(1-{{z}^{-1}})[-{{q}_{n1}}+{{q}_{n2}}(1-{{z}^{-1}})+(1-{{z}^{-1}})[-{{q}_{n2}}+{{q}_{n3}}(1-{{z}^{-1}}) ] ] $$

(6.22)

which can be simplified to

$$ s=fn+{{q}_{n3}}{{(1-{{z}^{-1}})}^{3}}$$

(6.23)

As (6.23) shows, what effectively was done with a MASH111 sigma–delta modulator is that the quantization noise is now shaped by a third-order digital high-pass filter. This is a general result, where an nth order sigma–delta modulator would have n^th order shaping of the quantization noise. The quantization noise of a second-order modulator is compared to a third order modulator in Fig. 6.15. As the figure shows, the low-frequency noise is significantly less for a third order modulator.

Fig. 6.15

Comparison of noise shaping between a second-order and third-order sigma–delta modulator.

In the context of a sigma–delta PLL, the input signal fn is a DC signal representing the desired fractional frequency value. The low-pass filter following the sigma–delta modulator is the low-pass closed loop response of the PLL. The quantization noise is the dithering of the feedback division ratio. The step size of the quantizer is equal to a VCO period.

Figure 6.16 shows a schematic diagram of a digital sigma–delta modulator. Each accumulator represents an integrator stage. The “Carry Out” is equivalent to the output of the quantizer. The quantization error is then the difference between the accumulated value minus the “Carry Out” bit, if the “Carry Out” bit is considered to be the MSB of the accumulated value. In other words, if the accumulated value is represented as ACC, the quantization error is

Fig. 6.16

A digital sigma–delta modulator

$$ {{e}_{q,i}}=AC{{C}_{i}}-{{y}_{i}}=-SU{{M}_{i}}$$

(6.24)

where SUM_i is the sum value of the accumulator of the ith accumulator. In other words, a digital sigma–delta modulator does not require an explicit DAC or analog subtractor as was needed in the analog equivalent of Fig. 6.14. Instead, the SUM output of one accumulator (which is equal to -e_q as per (6.24)) can be simply fed into the input of the next accumulator. As in the analog equivalent of Fig. 6.14, the “Carry Out” terminals of each accumulator stage are first digitally differentiated by a 1−z⁻¹ operator before adding to the previous stage, resulting in the expression given by (6.23).

One consequence of using a MASH type of modulator is that the output dithering range of the modulator increases with each cascaded stage. More specifically, this can be seen by analyzing Fig. 6.16 more carefully. If the range of the binary y_i outputs is [0,1], the output of the first differentiator associated with the y₃ output is [− 1,0,1]. When added to y₂, the dynamic range becomes [− 1,0,1,2]. When this output is differentiated, the output dynamic range becomes [− 3,− 2,− 1,0,1,2,3]. Finally, when adding the y₁ output, the final dynamic range is the integer range of [− 3,+ 4], requiring a 3-bit output.

There are wide variety of other higher-order sigma–delta topologies that employ feedforward and feedback techniques. One motivation of using such techniques is to reduce the output dithering range of the sigma–delta modulator to one bit. Table 6.1 summarizes the trade-off between single bit and multibit MASH sigma–delta modulators.

Table 6.1 Comparison of multibit and single bit ΣΔ modulators

As stated earlier, a sigma–delta modulator dithers the division ratio of the feedback divider. The frequency divider is usually modeled as a 1/L scaling factor in the phase domain model of the PLL. This is, however, true if the input is from the VCO. The phase domain model from the sigma–delta modulator to the frequency divider output is different. The phase deviation at the output of the frequency divider depends on the sum of all previous phase deviations that the frequency divider experienced. This is because the new L count of the feedback frequency divider does not start until the previous count has completed. In other words, the phase output of the frequency divider depends on the sum of all the phases of all the previous divider counts plus the VCO phase. In the case of an integer PLL, the phase deviation at the output of the divider is proportional to $\text{k}\cdot \text{L}+{{\theta }_{\text{vco}}}$, or $\text{k}+{{\theta }_{\text{vco}}}/\text{L}$ when referred to the PLL output. In the case of a sigma–delta modulated frequency divider, the phase error (normalized to the PLL output) is equal to [11].

$$ {{\theta }_{div}}[k] = \frac{1}{L_{nom}} \left(-2\pi \sum\nolimits_{m-1}^{k} {n[m-1]+{\theta }_{vco}} [k] \right) $$

(6.25)

where n[m− 1] is the frequency divider value at time step m− 1, which is equal to L plus the output of the sigma–delta modulator, and L_nom is the average division ratio which is L plus fn. What (6.25) reveals is that the output of the sigma–delta modulator is summed, or integrated, before appearing as phase at the frequency divider output. In other words, in the z-domain, the phase output of the frequency divider (referred to the PLL output) is given as

$$ {{\theta }_{div}}[k ]=\frac{2\pi }{{{L}_{nom}}}\frac{{{z}^{-1}}}{1-{{z}^{-1}}}$$

(6.26)

Another way of validating the presence of an integration term as shown in (6.25) and (6.26) is to examine the units at each point. The input to the sigma–delta modulator is the desired fractional frequency. Since the PLL model is a phase domain model, the output of the sigma–delta modulator must undergo an integration operation in order to be compatible with the unit at the output of the frequency divider, which is phase.

One final word regarding this point is with regard to using a PLL as a phase path in a polar modulator as was shown in Fig. 5.9. The I and Q signals at baseband were converted into polar form: amplitude and phase. The digital phase word produced by the I/Q-to-polar converter would then be used to modulate the feedback division ratio in a PLL. As was shown by (6.26), the phase would undergo an integration operation and would lead to incorrect phase modulation of the signal. To counteract this effect, the digital phase word must undergo a digital differentiation operation, 1−z⁻¹, as shown in Fig. 5.9. After the integration operation of the feedback divider, this would reproduce the phase signal back into the PLL loop, and the phase is correctly modulated.

6.4 PLL Phase Noise Optimization

One critical metric in PLLs is its phase noise performance, or jitter. The jitter performance of the PLL is the weighted sum of the jitter performance of all the various components of the PLL. Figure 6.17 shows a linear model of a PLL showing the jitter contribution of each PLL. As the figure shows, the jitter component of each block is modeled as additive jitter added to the output of each block. Transfer function from each noise source to the output of the PLL is known as the jitter transfer function. Note that the noise contribution of the crystal oscillator (XO) buffer is the same as the linear transfer function of the PLL, which was given by (6.11). The only noise contribution of the sigma–delta modulator is assumed to be the frequency-shaped quantization noise, the rest are assumed to be composed of thermal and flicker noise components.

Fig. 6.17

Linear model of PLL showing jitter contributions

The noise-transfer functions illustrated in Fig. 6.17 are given by (6.27)–(6.33).

$$ {{H}_{1}}(s)={{H}_{xo}}(s )=\frac{{{I}_{p}}{{K}_{vco}}F(s)}{s+{{I}_{p}}{{K}_{vco}}F(s)/L} $$

(6.27)

$$ {{H}_{2}}(s)={{H}_{pfd}}(s )=\frac{2\pi {{I}_{p}}{{K}_{vco}}F(s)}{s+{{I}_{p}}{{K}_{vco}}F(s)/L} $$

(6.28)

$$ {{H}_{3}}(s)={{H}_{cp}}(s )=\frac{2\pi {{K}_{vco}}F(s)}{s+{{I}_{p}}{{K}_{vco}}F(s)/L} $$

(6.29)

$$ {{H}_{4}}(s)={{H}_{lf}}(s )=\frac{{{I}_{p}}{{K}_{vco}}}{s+{{I}_{p}}{{K}_{vco}}F(s)/L} $$

(6.30)

$$ {{H}_{5}}(s)={{H}_{vco}}(s )=\frac{s}{s+{{I}_{p}}{{K}_{vco}}F(s)/L} $$

(6.31)

$$ {{H}_{6}}(s)={{H}_{fbdiv}}(s )=\frac{{{I}_{p}}{{K}_{vco}}F(s)}{s+{{I}_{p}}{{K}_{vco}}F(s)/L} $$

(6.32)

$$ {{H}_{7}}(s)={{H}_{\Sigma \Delta }}(s )=\frac{{{I}_{p}}{{K}_{vco}}F(s)}{s+{{I}_{p}}{{K}_{vco}}F(s)/L} $$

(6.33)

As (6.27)–(6.33) show, the filtering response of the PLL to noise injection differs depending on where the noise is injected. Noise generated by the sigma–delta modulator, feedback divider, crystal oscillator buffer, and PFD and charge pump are all low-pass filtered. These noise contributors are often referred to as in-band noise contributors. Note that the magnitude of the various low-pass filters vary. Noise injected into the loop filter is bandpass filtered, whereas noise generated by the VCO is high-pass filtered. Also, note that the noise-transfer function of the feedback divider and the crystal oscillator buffer are the same.

Special attention must be paid to the noise-transfer function of the sigma–delta modulator. Equation (6.33) shows the transfer function of the quantization noise shaped by the sigma–delta modulator and the feedback divider integration operation as it appears at the final PLL output. This means that (6.33) can be expanded into

$$ {{H}_{\Sigma \Delta }}(s )=\frac{{{I}_{p}}{{K}_{vco}}F(s)}{s+{{I}_{p}}{{K}_{vco}}F(s)/L}\cdot \frac{{{z}^{-1}}}{1-{{z}^{-1}}}\cdot {{(1-{{z}^{-1}})}^{m}}$$

(6.34)

Considering the magnitude of (6.34), it can be simplified to

$$ {{H}_{\Sigma \Delta }}(f )=(2\pi)\left| \frac{{{I}_{p}}{{K}_{vco}}F(j2\pi f)}{j2\pi f+{{I}_{p}}{{K}_{vco}}F(j2\pi f)/L} \right|\cdot {{\left| 2\sin \left(\frac{\pi f}{{{F}_{ref}}}\right) \right|}^{m-1}}$$

(6.35)

where F_ref is the reference frequency of the PLL. Since the quantization noise of the sigma–delta modulator is assumed to be uniformly distributed over F_ref, its phase noise contribution as seen at the output is given as

$$ \theta_{n,\Sigma \Delta }^{2}(f )=\frac{{{(2\pi)}^{2}}}{12{{F}_{ref}}}\cdot {{\left| \frac{{{I}_{p}}{{K}_{vco}}F(j2\pi f)}{j2\pi f+{{I}_{p}}{{K}_{vco}}F(j2\pi f)/L} \right|}^{2}}\cdot {{\left| 2\sin \left(\frac{\pi f}{{{F}_{ref}}}\right) \right|}^{2(m-1 )}}$$

(6.36)

The varying filtering characteristics of the PLL noise-transfer functions leads to an optimal point for choosing a closed-loop bandwidth for minimum PLL integrated ­jitter. More specifically, a bandwidth is chosen such that the noise contributors of the in-band noise sources are equal to that of the VCO noise (and the ΣΔ modulator in the case of a fractional-N PLL). The noise contribution of the resistor noise in the loop filter is assumed to be small in this analysis. Mathematically stated, the PLL bandwidth optimization problem then becomes selecting the PLL loop parameters (namely charge pump current, VCO gain and loop filter components) such that the PLL ­integrated noise is minimized. The PLL integrated phase noise function is given as

$$ \theta_{rms}^{2}(f )=\sum\nolimits_{i=1}^{7}{\int_{{{f}_{1}}}^{{{f}_{2}}}{N_{i}^{2}(f)\cdot {{\left| {{H}_{i}}(f) \right|}^{2}}df}}$$

(6.37)

where H_i(f) is given by (6.27)–(6.33) and $N_{i}^{2}(f)$ is the power spectral density of the noise of the ith component in the loop, f₁ and f₂ are the integration filter ranges (f₁ is the minimum frequency offset from the carrier and f₂ is the maximum frequency offset over which phase noise is a concern).

The choice of PLL bandwidth can now be viewed as an optimization problem where (6.37) is minimized given constraints on the ranges of the PLL parameters: K_v, I_cp and loop filter values. Figure 6.18 shows the normalized optimal PLL ­bandwidth as the normalized VCO phase noise is increased for an integer PLL. As the figure shows, the optimal PLL bandwidth shrinks as the VCO phase noise is increased.

Fig. 6.18

Optimal PLL bandwidth as in-band and VCO noise are varied

6.5 Charge Pump Circuit Implementation

Phase-Frequency Detector (PFD)

Two important components in an analog PLL is the phase-frequency detector (PFD) and charge pump. A conventional PFD is shown in Fig. 6.19 [12]. The PFD operates as a three-state machine. Although there are two digital outputs (UP and DN) and there are theoretically four states, the fourth state (UP = DN = 1) is disallowed by the feedback AND gate. The feedback AND gate detects this condition and resets both flip-flops to the zero state. The R signal is the signal from the clock reference source (typically a crystal oscillator buffer) and the V signal is the divided down VCO signal from the feedback divider. If the R signal leads the V signal, this means that the VCO phase is too slow and the PFD instructs the VCO to advance its phase by asserting the UP signal. On the other hand, if the V signal leads the R signal, this means that the VCO phase is faster than the reference phase and the PFD instructs the VCO to retard its phase by asserting the DN signal. When both the R and V signals are in phase, the UP and DN signals remain in the zero-state.

Fig. 6.19

A conventional 3-state phase-frequency detector (PFD)

One issue with the three-state phase detector is that it suffers from what is known as the dead zone issue [13]. Consider the locked condition where the R signal is equal in phase and frequency to the V signal. It is possible, in this case, that the path formed by the feedback AND gate along with the reset delay in the flip-flops is faster than the time required to fully settle the phase detector, causing partial toggling of the UP and DN signals. In this case, the effective charge pump current may be significantly less than what was predicted by from DC simulations. This results in a drastic reduction in closed loop bandwidth and can seriously alter the predicted overall phase noise performance. This singularity, or dead zone, near zero phase of the charge pump versus input phase error is illustrated graphically in Fig. 6.20.

Fig. 6.20

Charge pump versus input phase error using a 3-state PFD

One common method of resolving the dead zone issue is to use what is known as a 4-state PFD, shown in Fig. 6.21. A fourth state is now allowed in a PFD by inserting a delay after the feedback AND gate. This fourth state allows for the UP = DN = 1 state. This state allows sufficient time for both the UP and DN currents in the charge pump to fully settle to their required values, avoiding the deadzone issue discussed above. One on hand, the delay through the AND gate should be sufficiently long to allow proper settling of the UP and DN charge pump currents. On the other hand, the delay through the AND gate should be minimized in order to reduce noise due to the charge pump current (as will be seen later). The remaining three states of the 4-state PFD shown in Fig. 6.21 are the same as the 3-state PFD shown in Fig. 6.19. The valid states of a 4-state PFD are summarized in Table 6.2.

Fig. 6.21

A 4-state phase-frequency detector (PFD)

Table 6.2 Valid states of a 4-state PFD

Charge-Pump

A basic current steering charge pump is shown in Fig. 6.22. In this type of charge pump, two current sources are used. The I_UP current source is used to convert positive phase error into charge integrated on the loop filter. I_DN current source is used to convert negative phase error into charge integrated on the loop filter. The amount of time that either I_UP or I_DN currents are integrated onto the loop filter is controlled by the M1 and M2 devices, which act as switches. Transistors M3 and M4 steer the current through an alternate branch to prevent the current sources from completely turning off. The operation of the unity gain buffer will be explained shortly.

Fig. 6.22

A current steering charge pump

There are a number of nonidealities that arise from the charge pump shown in Fig. 6.22. First, there may be a static current mismatch between the I_UP and I_DN currents. In order for the PLL to lock, the average charge introduced by the I_UP current source into the loop filter must be equal to the amount of charge introduced by the I_DN current source into the loop filter. In mathematical terms,

$$ {{Q}_{up}}={{Q}_{dn}}~~~~\overset{{}}{\mathop{\Rightarrow }}\,~~~{{I}_{UP}}\cdot \Delta {{t}_{up}}={{I}_{DN}}\cdot \Delta {{t}_{dn}}$$

(6.38)

where Q_up is the total charge introduced by the I_UP current source over one reference period, Q_dn is the total charge introduced by the I_DN current source over one reference period, Δt_up is the pulse width of the UP signal, and Δt_dn is the pulse width of the DN signal. In the presence of current mismatch between I_UP and I_DN currents, a static phase offset develops in the loop to compensate for this mismatch. If the charge pump mismatch is merged into the I_DN current such that I_DN = I + ΔI and I_UP = I, the resulting static phase error between the input and output of the PLL is given as

$$ \Delta {{t}_{offset}}=\frac{\Delta I}{I}{{t}_{on}}$$

(6.39)

where t_on is the minimum pulse width set the delay element in the feedback path of the PFD.

Another impairment of the charge pump shown in Fig. 6.22 is known as charge sharing. When either the UP or DN signal undergoes a low-to-high transition I_UP or I_DN current, respectively, it is pumped into the loop filter. At the moment before this occurs, the voltage potential at node X or Y matches that of node D (ignoring the “on” resistance of the M3 and M4 switches); whereas, the loop filter voltage at this time instant can be different from the voltage potential at node D. At the moment, when the current source is switched over, the X or Y nodes are shorted with the loop filter. Since these nodes have different voltages, charge transfer or sharing, occurs between the nodes. More specifically, if we consider charge sharing between node X and the loop filter node, F, the transferred charge is equal to

$$ {{q}_{err,cs}}={{C}_{x}}{{V}_{x}}-{{C}_{x}}{{V}_{f}}=\frac{{{C}_{x}}{{C}_{LF}}({{V}_{x}}-{{V}_{LF}})}{{{C}_{x}}{{C}_{LF}}}$$

(6.40)

where V_X is the voltage at node X, V_f is the final settling voltage after charge sharing between node X and the loop filter node, C_X is the parasitic capacitance at node X, C_LF is the total loop filter capacitance. The charge can be regarded as an input phase error independent charge error term that is integrated at every reference cycle.

One way to reduce the effect of charge sharing is to ensure that the voltage at node X or Y is equal to the loop filter voltage. This is the primary function of the unity gain buffer. The loop filter is sensed and the other node in the current steering differential pair, typically called the dummy node, is forced to be equal to the loop filter node through the unity gain buffer. The current source and sink of the buffer should be large enough to absorb the I_DN and I_UP currents, respectively.

An opamp that is typically used to implement the unity gain buffer is shown in Fig. 6.23. A rail-to-rail input folded cascode opamp is shown. The speed of the opamp should be sufficiently large that it is much larger than the closed-loop bandwidth of the PLL and can recover reasonably well within one reference cycle from any glitches that can occur on the dummy node as a result of switching activity. Also, the rail-to-rail input stage is useful for low-voltage operation. The output stage of the folded cascode structure is single-ended, as the figure shows.

Fig. 6.23

Opamp used in charge pump

The second charge impairment in the current steering charge pump shown in Fig. 6.22 is charge injection. Charge injection is caused by the mobile charge in the metal–oxide–semiconductor field-effect transistor’s (MOSFET) inversion layer, which is forced to leave the channel when the gate voltage changes. Any inversion charge that escapes to the loop filter node is an additional charge error term. When the M1 and/or the M2 transistor turns off, half of the charge in the channel goes to the X or Y node, respectively, and the other half goes to the loop filter capacitors. The charge in the channel is given as [14]

$$ {{Q}_{ch}}={{C}_{ox}}[{{V}_{GS}}-{{V}_{T}}] $$

(6.41)

where C_ox is the gate oxide capacitance, V_GS is the gate to source voltage, and V_T is the MOSFET device threshold voltage. Since it is assumed that the device V_DS is nearly zero (i.e., no horizontal electric field across the MOSFET channel), half the charge escapes through the drain, while the other half escapes through the source. This is somewhat of an approximation since the resistive nature of the channel forces a voltage gradient to develop within the channel as the charge attempts to escape. If this voltage becomes lower than the substrate voltage, it can cause charge to escape through the substrate. This effect is known as charge pumping and was first discovered by Brugler and Jesper [15]. From a circuit design perspective, this effect is desirable since it minimizes the charge error term appearing at the loop filter terminal. Also note that there are two devices at the loop filter node injecting charge in different directions (the p-type field effect transistor (PFET) injects hole whereas the n-type field effect transistor (NFET) inject electrons). The total charge error introduced by charge injection at the loop filter node then becomes

$$ {{q}_{ci,err}}=\frac{{{C}_{ox}}\cdot [-{{V}_{DD}}+{{V}_{T}}]}{2} $$

(6.42)

where V_DD is the supply voltage, V_T is the (MOSFET) threshold voltage, and it was assumed that the PFET switch is sized twice that of the NFET switch. This indicates that the circuit design parameters affecting charge injection are the area of the device (C_ox) and the power supply voltage.

The third type of charge impairment is clock feedthrough [16]. Clock feedthrough is caused by the sharp rising and falling edges of the UP and DN signals coupling through the gate parasitics capacitors of the switching onto the loop filter. This scenario is illustrated in Fig. 6.24. The sharp rise and fall time through the last inverter stage in a PFD causes a current flow through to the output capacitance seen at that inverter stage. The output load capacitance can be split into two capacitors, C_gd, the gate-to-drain capacitance of the switch in the charge pump, and C_p which is all other parasitics capacitances at the output load of the inverter. The current flowing through the C_gd capacitor gives rise to the charge error term due to clock feedthrough. More specifically, the charge error appearing at the loop filter can be given as

Fig. 6.24

Clock feedthrough scenario in a charge pump switch

$$ {{q}_{err,clk}}=\int_{0}^{{{T}_{ref}}}{\left[\frac{{{C}_{gd}}}{{{C}_{gd}}+{{C}_{p}}}\left({{C}_{gd}}+{{C}_{p}}\right)\cdot \frac{dv(t)}{dt} \right]dt} $$

(6.43)

where v(t) is the output voltage of the last inverter stage in the PFD and T_ref is the reference period (equal to 1/F_ref). As Fig. 6.24 shows, the simplifiying assumption is that the loop filter can be treated as short. Since in reality the impedance of the loop filter is higher, (6.43) can be treated as an upper bound on charge error due to clock feedthrough.

The optimization of the output noise of a charge pump and PFD are also important. The AC noise analysis of a charge pump is fairly straight forward. The current noise density of all the devices can be referred to the output, then multiplied by the square of the impedance seen at the output. Since the noise is low-pass filtered by the loop filter, minimizing noise only at low frequencies would be important. The noise of a PFD + charge pump, however, is complicated by the fact that the operating of PFD is periodic at steady state. This causes a finite amount of sampling of the charge pump noise. This sampling causes alias terms to appear. For example, if the PFD is operating at 100 MHz and there is a noise source at 1 MHz, due to the sampled and periodic nature of the PFD during locked condition, an alias noise term will appear at 99 MHz, 101 MHz and at ± 1 MHz around all harmonics of the PFD sampling rate (100 MHz). Moreover, the amplitude of the harmonic samples is shaped by the sinc function introduced by the t_on pulse width of the PFD output signals UP and DN, as shown in Fig. 6.25. The implication of the phenomenon is that the wider the UP and DN pulse widths, the tighter the sinc function resulting in more noise filtering prior to the charge pump (i.e., more filtering of PFD or XO noise). Wider UP and DN pulse widths, however, result in more noise due to the charge pump itself (since noise is integrated over a longer period of time).

Fig. 6.25

Periodic UP and DN signals lead to a sampled sinc function to appear in the frequency domain

It can be shown that the power spectral density of device noise from the charge pump shaped by this sampling response is given by

$$ {{S}_{Y}}(f )=\sum_{n=-\infty }^{\infty }{{{\left| \frac{{{T}_{on}}}{{{T}_{ref}}}sinc\left(\frac{n\cdot {{T}_{on}}}{{{T}_{ref}}}\right) \right|}^{2}}\cdot {{S}_{x}}(f)} $$

(6.44)

where S_x(f) is the power spectral density of the device noise sources in the charge pump. This shows that the power spectral noise density is reduced for smaller T_on pulse widths of the UP and DN signals.

Another important issue is the effect of nonlinear charge pump output characteristic. As seen in Sect. 6.3.2, the quantization noise in a sigma–delta modulator can be modeled as uniformly distributed additive noise source. This is under two ­assumptions. First, there is sufficient activity at the output of the integrator preceding the quantizer such that it can be treated as a random process. Second, the step sizes in a multibit quantizer are equal to one another. This second assumption is necessary to maintain an equiprobable, and hence uniform, noise density of the quantization noise. The step size in a ΣΔ PLL is ultimately equal to the unit amount of charge dumped to the loop filter for unit step size in the ΣΔ modulator.

Due to the three charge impairments listed earlier, the charge error near zero phase error has the largest deviation from the ideal linear charge pump characteristic. Figure 6.26 shows an example of how the average current integrated over one reference cycle per phase error changes as the input phase error to the PFD is swept from − 1 ns to + 1 ns. The reference period was 50 MHz in this simulation. The phase error is expressed as a percentage deviation from the ideal linear charge pump. Note that at larger phase error, the static phase error settles to a ­nonzero value. This is due to both DC current mismatch between the I_UP and I_DN currents as well as a residual net charge error from the three charge impairments listed ­earlier. As the sigma–delta modulator dithers the phase from the feedback divider, the phase ­detector is ­dithered around the nonlinear region shown in Fig. 6.26. Each phase dither step is equal to a sigma–delta quantizer phase step size. Since the phase step size is converted to charge by integrating the curve in Fig. 6.26 over the phase step size, nonlinear charge quantization step sizes result at the output of the charge pump.

Fig. 6.26

Average current integrated over one reference period per phase error versus phase error

The effect of nonlinear step sizes is twofold. First, it causes noise folding. Noise folding is a phenomenon where high-frequency quantization noise is folded back to lower frequency. This can be explained by considering the sigma–delta quantization frequency spectrum as individual closely spaced tones. These tones are then multiplied by the charge pump transfer function, which is a nonlinear function. The charge pump nonlinear function can be approximated by a polynomial containing second- and third-order terms. This means that the sigma–delta quantization noise spectrum undergoes both second-order and third-order distortion. Considering two high-frequency tones within the sigma–delta noise spectrum, f₁ and f₂, the second-order intermodulation terms land on f₁ − f₂ and f₁ + f₂ frequencies. The f₁ − f₂ component results in low-frequency noise. Now, considering the full range of the quantization noise spectrum, there are several combinations of f₁ and f₂ that can potentially land within the PLL closed-loop bandwidth. These intermodulation terms are then aggregated to produce an increase in in-band phase noise. As similar argument holds for third-order distortion. Although higher-order distortion terms are possible, they usually have less effect than second- and third-order distortion. An example of noise folding in a sigma–delta PLL is shown in Fig. 6.27. Two plots are overlaid. One with a nonlinearity in the charge pump (the curve with the higher in-band phase noise) and the other with the nonlinearity in the charge pump corrected. It is important to note that this noise folding mechanism occurs before the filtering action of the PLL’s low-pass filter following the charge pump.

Fig. 6.27

Noise folding in a sigma–delta PLL

6.6 Voltage-Controlled Oscillator Implementation

The VCO is a central component of the PLL. Its performance determines the tuning range of the PLL and to a large degree its overall phase noise, or jitter performance. Most integrated VCOs for wireless applications rely on an LC tank that is excited by a negative transconductance element to provide oscillation. In this section, VCO phase noise theory is first reviewed, followed by design trade-offs involved in determining the frequency tuning range and phase noise of the oscillator.

6.6.1 VCO Phase Noise Theory

In its most general form, an oscillator may be represented by the positive feedback system shown in Fig. 6.28. The transfer function of this system is

Fig. 6.28

A generic positive feedback system

$$ H(j\omega)=\frac{F(j\omega)}{1-F(j\omega)} $$

(6.45)

where F(jω) is the open-loop transfer function of the oscillator, and H(jω) is the closed-loop transfer function of the oscillator. Since it is a positive feedback system, the amplitude of oscillation will grow until a nonlinearity in the oscillator causes its amplitude to saturate. Such nonlinearities include power supply limitations or transistor saturation. At large amplitudes, circuit nonlinearities become so severe that the gain of F(jω) becomes 1 and the total phase shift around the feedback loop is 0° ± 360⋅n°, where n is a positive integer. These two requirements constitute what is known as the Barkhausen’s criteria for oscillation [17]. When F(jω_o) = 1, the oscillator’s frequency is ω_o rad/s.

Another way of viewing the system representing an oscillator is by looking at the root locus of the system in Fig. 6.28 while varying F(jω). Initially, F(jω) is much greater than one. As the voltage swing grows, circuit nonlinearities cause the magnitude of F(jω) to quickly decrease up until the poles of the system are on the imaginary axis. At this point, stable oscillation is sustained at a certain frequency ω_o. At this point, the steady-state magnitude of the system is exactly one. Any perturbation in the magnitude would cause the poles to shift to the right or left causing a frequency or phase shift. This translation of magnitude error to frequency or phase error is what causes jitter. The root locus plot of the system in Fig. 6.28 is shown in Fig. 6.29.

Fig. 6.29

Root locus of positive feedback system

An important parameter of an oscillator’s performance is its open-loop Q factor. Simply stated, the open-loop Q factor is a measure of how much the closed-loop feedback system opposes variation in oscillation frequency. One commonly used equation for open-loop Q factor is

$$ Q=\frac{{{\omega }_{0}}}{{}\Delta{}\omega } $$

(6.46)

where ω_o is the oscillation frequency and Δω is the double sided frequency offset where the spectral density of the transfer function is one-half its peak value at ω_o as shown in Fig. 6.30. Using this definition and considering only one-side of the energy of the H(jω) transfer function, the magnitude of H(jω) at ω_o + Δω is

Fig. 6.30

Bode plot of closed-loop transfer function of oscillator

$$ \left| H(j\omega) \right|=\frac{{{R}_{p}}}{2}=\frac{{{R}_{p}}}{2}\left(\frac{{{\omega }_{0}}}{Q\cdot \Delta \omega } \right) $$

(6.47)

where R_p is the maximum amplitude of H(jω).

Assuming that the dominant component of noise is thermal noise of R_p, the power spectral density of the thermal noise shaped by the oscillator transfer function is

$$ \frac{\overline{v_{n}^{2}}}{\Delta f}=\frac{\overline{i_{n}^{2}}}{\Delta f}\cdot {{\left| H(j\omega) \right|}^{2}}=4kT{{R}_{p}}\cdot {{\left(\frac{{{\omega }_{0}}}{2Q\Delta \omega } \right)}^{2}}$$

(6.48)

Equation (6.48) gives the total output spectrum including the amplitude as well as phase spectrum. Using the equipartition theorem of thermodynamics [18], the total spectrum is split evenly between phase noise spectrum and amplitude noise spectrum. However, since the oscillator nonlinearities provide an indirect form of amplitude control, the total output spectrum of the oscillator is given as only half of equation (6.48). Also, phase noise is normally reported as relative to the carrier signal at ω_o. Using these two facts, the phase noise spectrum of an oscillator dominated by thermal noise is given as

$$ L\left\{\Delta \omega\right\}=\frac{2kT}{{{P}_{c}}}\cdot {{\left(\frac{{{\omega }_{0}}}{2Q\Delta \omega } \right)}^{2}}$$

(6.49)

where P_c is the amplitude power of the oscillator. This formula is known as Leeson’s formula [19]. Given this expression, the rms phase error can be found by summing (6.49) over the entire noise bandwidth. Since much of the power of the phase noise lies within a frequency bandwidth of Δω around ω_o, the rms phase error can be found as

$$ {{\theta }_{e,rms}}=\int_{-\frac{{{\omega }_{0}}}{2Q}}^{\frac{{{\omega }_{0}}}{2Q}}{\frac{2kT}{{{P}_{c}}}\cdot {{\left(\frac{{{\omega }_{0}}}{2Q\Delta \omega } \right)}^{2}}d(\Delta \omega)} $$

(6.50)

Evaluating this integral yields the following result:

$$ {{\theta }_{e,rms}}=\frac{kT}{{{P}_{c}}}\cdot \left(\frac{{{\omega }_{0}}}{Q} \right)\text{rads} $$

(6.51)

Converting radians to time, the rms jitter T_{j, rms} is given as

$$ {{T}_{j,rms}}=\frac{kT}{2{{P}_{c}}}\cdot \left(\frac{1}{Q} \right)\ \sec$$

(6.52)

This is a very significant result. It clearly shows that for a given VCO topology (fixed Q), the rms jitter varies only with the power level of the oscillator output signal. This means that there is a direct trade-off between power consumption and jitter in oscillators.

The above analysis assumes that the noise of the oscillator depends only on the thermal noise of the devices used to build the oscillator. Such an assumption leads to the conclusion that the phase noise decreases at a rate of 20 dB/decade indefinitely. In practice, the phase noise floor is limited by the VCO output buffers, where the device noise is not shaped by the VCO phase noise shaping function. Also, at small frequency offsets Δω, flicker noise is more dominant. A more accurate plot of phase noise spectrum of an oscillator is shown in Fig. 6.31.

Fig. 6.31

More realistic phase noise spectrum of an oscillator

An equation representing the graph in Fig. 6.31 can be given as

$$ L\left\{\Delta \omega\right\}=\frac{2kTF}{{{P}_{c}}}\cdot \left[1+{{\left(\frac{{{\omega }_{0}}}{2Q\Delta \omega } \right)}^{2}}\right]\cdot \left[1+\frac{\Delta \omega_{1/f}^{3}}{\left| \Delta \omega\right|} \right] $$

(6.53)

where F is a empirical parameter (or “fudge” factor) and $\Delta \omega_{1/f}^{3}$ is the corner frequency between the 1/f² and 1/f³ regions of the phase noise spectrum. Equation (6.53) is known as the Leeson–Cutler formula [20]. The F parameter accounts for other noise sources other than the losses in the F(jω) system. Such noise sources can include intrinsic and extrinsic noise sources. The “1” factor accounts for the fact that there is a phase noise floor that defines the absolute minimum phase noise achievable at all offset frequencies. The 1/f³ region corresponds to upconversion of 1/f noise (mainly device flicker noise) to near the oscillation frequency. The Leeson–Cutler formula suggests that the boundary between the 1/f³ and 1/f² regions is exactly the boundary between the 1/f and thermal noise regions. However, empirical data suggests otherwise for reasons that are explained in the next section.

6.6.2 Cyclostationary Analysis of VCO Phase Noise

The “fudge” factor F in the Leeson–Cutler formula given by (6.53) has been an unsatisfying factor to many designers for a number of years. One theory that has helped account for much of this “fudge” factor is the cyclostationary analysis of VCO phase noise. In this section, the periodic nature of the VCO output and its effect on phase noise is analyzed in more detail.

Figure 6.32 shows the translation of voltage noise into phase error at various regions of operation given a periodic signal, such as the VCO output voltage. As the figure shows, the amount of jitter resulting can differ drastically depending on the time instant the amplitude noise is injected into the VCO. When noise is injected during the voltage transition of the VCO output, it can potentially alter the zero crossings of the VCO, inducing phase noise. For this reason, the phase noise expression for VCOs is said to be a time-varying function. Moreover, since the output of a VCO is periodic, the noise sources that induce jitter vary periodically with time. Such noise sources are called cyclostationary noise sources [21].

Fig. 6.32

Jitter transfer function for various noise injection times

The output of an oscillator may be given as

$$ {{V}_{out}}(t )=A(t)\cdot f[{{\omega }_{0}}t+\phi (t) ] $$

(6.54)

where the function f is periodic in 2π and φ(t) and A(t) are the phase and amplitude variations due to noise, respectively. Amplitude variations may alter the zero-crossing of the oscillator’s output, and hence translate into phase variation. If the amplitude variation is small enough, the amplitude-to-phase translation may be assumed to be linear. An instantaneous change in voltage due to noise injection would cause an instantaneous change in charge, which is given by

$$ \Delta V=\frac{\Delta q}{{{C}_{node}}}$$

(6.55)

where C_node is the capacitance of the node which experienced charge injection due to noise. The phase variation can be given by [22]

$$ {}\Delta{}\phi ={}\Gamma{}({{\omega }_{0}}t )\frac{{}\Delta{}q}{{{q}_{swing}}}$$

(6.56)

where q_swing = C_node⋅V_swing, and V_swing is the voltage swing of the node which experienced the noise charge injection. Г(ω₀t) is a unitless time-varying function, called the impulse sensitivity function (ISF) [23]. When an internal signal is high or low, amplitude noise will have little or no effect on phase error on the output of the oscillator. This means that the ISF is a small or zero value during that interval. On the other hand, the ISF is maximized at the time of a transition switching of an internal node. Note that once a phase error has occurred, it is not corrected for. Therefore, the phase error accumulates indefinitely as time increases. This type of analysis assumes that the oscillator is a linear time-varying (LTV) system.

Assuming that the total noise in the oscillator can be represented as current noise i(t), the output phase error of the oscillator is given as

$$ \phi (t )=\frac{1}{{{q}_{max}}}\int_{-\infty }^{t}{{}\Gamma{}({{\omega }_{0}})\cdot i(\tau)d\tau } $$

(6.57)

where q_max is the maximum charge injected by the noise source. Since ISF is a periodic function, it can be represented as a Fourier series

$$ {}\Gamma{}({{\omega }_{0}}\tau)=\frac{{{c}_{0}}}{2}+\sum\nolimits_{n=1}^{\infty }{{{c}_{n}}\cos (n{{\omega }_{0}}\tau)} $$

(6.58)

Substituting (6.58) back into (6.57) gives

$$ \phi (t ) = \frac{1}{q_{max}} \left[\frac{c_0}{2} \int_{-\infty }^{t} {i\left(\tau\right)d\tau } + \sum\nolimits_{n=1}^{\infty } {c_n} \int_{-\infty }^{t} {i(\tau)\cos \left(n{\omega_0} \tau\right)d\tau } \right] $$

(6.59)

Consider two cases for i(t): (a) when it is a low-frequency sinusoidal signal with frequency Δω, and (b) when it is a sinusoidal signal with a frequency near the carrier ω_o with frequency ω_o ± Δω. In the first case, only the first integral in (6.59) contains a significant signal, and the resulting output phase error is given as

$$ \phi (t )=\frac{{{I}_{0}}{{c}_{0}}\sin ({}\Delta{}\omega t )}{2{{q}_{max}}{}\Delta{}\omega } $$

(6.60)

where I₀ is the maximum amplitude of the input current. A similar result can be shown for case (b), but with Fourier coefficient c₁. More generally, it can be shown that for a current sinusoidal input with frequency ω_o ± nΔω, the output phase error will be a sinusoid with frequency Δω and magnitude proportional to c_n. These phase errors are then upconverted to ω_o (for c₀) and downconverted to ω_o (for c₂, c₃, …, c_n) to the oscillation frequency by the nonlinear oscillator transfer function. Noise sources near ω_o remain the same. This means that noise injected into the oscillator is only significant if it is near dc, near the oscillator frequency, or a harmonic of the oscillator frequency. A similar result was reached in [24].

The statistics of the timing jitter depends on the correlation of the noise sources involved. In the case of thermal noise, the noise sources are considered to be random and uncorrelated. Therefore, it follows that considering only the thermal noise of an oscillator and jitter measured over a time interval ΔT, the standard deviation of the jitter of the oscillator is given as [25]

$$ {{\sigma }_{{}\Delta{}T}}=\kappa \sqrt{{}\Delta{}T} $$

(6.61)

where κ is a proportionality constant which can be shown to be equal to

$$ \kappa =\frac{{{{}\Gamma{}}_{rms}}}{{{q}_{max}}{{\omega }_{0}}}\sqrt{\frac{1}{2}\frac{\overline{i_{n}^{2}}}{{}\Delta{}f}}$$

(6.62)

where ω₀ is the output target frequency in rads/sec, q_max is equal to C_L⋅V_SW, where C_L is the parasitic capacitance at the output of the oscillator and V_SW is the voltage swing of the oscillator, and $\tfrac{\overline{i_{n}^{2}}}{\Delta f}$is the power spectral density of the thermal noise of the active devices in the oscillator. For CMOS transistors, the drain current noise spectral density is given by [26]

$$ \frac{\overline{i_{n}^{2}}}{{}\Delta{}f}=4kT\gamma \mu {{C}_{ox}}\frac{W}{L}{{({{V}_{GS}}-{{V}_{T}})}^{2}}$$

(6.63)

where γ is a coefficient equal to 2/3 for long-channel transistors. As equations (6.62) and (6.63) show, jitter due to thermal noise can be minimized by reducing the ISF, increasing the voltage swing (at the expense of power consumption), increasing the operating frequency, or reducing the power spectral density of the device thermal noise.

Correlated noise sources are usually a result of low-frequency noise, such as flicker noise, as well as power supply bounces. Flicker noise can be minimized by using large transistors. One interesting result from ISF analysis is that the corner frequency of 1/f² and 1/f³ can be accurately determined to be [27]

$$ {{\omega }_{1/{{f}^{3}}}}={{\omega }_{1/f}}\cdot {{\left(\frac{{{{}\Gamma{}}_{dc}}}{{{{}\Gamma{}}_{rms}}}\right)}^{2}}\approx {{\omega }_{1/f}}\cdot {{\left(\frac{{{c}_{0}}}{{{c}_{1}}}\right)}^{2}}$$

(6.64)

where ω_1/f is the corner frequency of 1/f noise and thermal white noise. Therefore, the upconversion of flicker noise can be minimized by having a more symmetric waveform around the x-axis (for zero dc level) and by maximizing the oscillator’s voltage swing. This is contrary to the original assumption by Leeson when deriving his formula [19].

One important parameter in the design of a VCO is its power supply rejection. The analysis injection of a tone from the power supply near the carrier frequency is equivalent to modulating the amplitude of the VCO. If the modulated envelope is expressed as a sinusoidal signal, the resultant AM modulated signal can be expressed as

$$ {{y}_{vco}}(t )=[1+m\cdot \cos (2\pi {{f}_{m}}t+\phi)]\cdot {{V}_{swing}}\cdot \sin (2\pi {{f}_{c}}t ) $$

(6.65)

where f_m is the frequency of the modulation of the VCO amplitude envelope, f_c is the VCO center frequency, and m is the AM modulation index, which is equal to the ratio of the amplitude of the noise tone to the VCO amplitude. Expanding the expression given by (6.65) leads to

$$ {{y}_{vco}}(t )=\begin{matrix} {{V}_{swing}}\cdot \sin (2\pi {{f}_{c}}t )+\\ \frac{m\cdot {{V}_{swing}}}{2}[\sin (2\pi ({{f}_{c}}+{{f}_{m}})t+\phi)+\sin (2\pi ({{f}_{c}}-{{f}_{m}})t-\phi) ]\end{matrix} $$

(6.66)

which shows that AM modulation results in a pair of side tones around the VCO carrier.

These two side tones are further shaped by two characteristics of the VCO. The first is the bandpass nature of the VCO, as was illustrated in Fig. 6.30. The higher the Q of the VCO, the more filtering is achieved. The filtering improves at a rate of 20 dB per decade of frequency offset, f_m, from the VCO center frequency, f_c. The other characteristic is the shaping of the VCO phase noise within the closed loop response of the PLL. As was shown by (6.31), the VCO phase noise is high-pass filtered when enclosed in a PLL. This means that phase noise at low-­frequency ­offsets from the carrier are well suppressed, whereas, high-frequency noise is passed through. Aligning the bandpass filtering response dependent on the Q of the VCO (which appears as a low-pass filter when viewed on a phase noise plot with the y-axis centered at the VCO center frequency) along with the high-pass nature of the VCO noise shaping in a PLL, leads to a power supply to output transfer function which appears to be bandpass shaped, as shown in Fig. 6.33. This shows that the worst case noise would appear at the PLL closed-loop bandwidth. Note that both x and y axes are logarithmic scales.

Fig. 6.33

Power supply noise-transfer function in VCOs

6.6.3 LC VCO Design

The most prevalent VCO topology is an LC VCO [28]. An LC VCO relies on an inductor–capacitor resonator tank to produce an oscillator. For a lossless LC tank, the tank would simply need an initial excitation signal to start oscillation. Since the tank is lossless, the output voltage could theoretically reach infinity. In any practical LC VCO implementation, there are resistive losses in both the inductor and capacitor. A negative conductance generator would be used to cancel out the losses in the LC tank.

Before discussing the various topologies of LC VCOs, RLC tanks are first reviewed. Consider a parallel RLC resonator shown in Fig. 6.34. The admittance of the tank is given as

Fig. 6.34

Parallel RLC resonator

$$ I(\omega)=\left\{G+j\left[\omega C-\frac{1}{\omega L} \right] \right\}\cdot {{V}_{tank}}$$

(6.67)

where $\text{G }=\text{ 1}/{{\text{R}}_{\text{P}}}$, L and C are the inductance and capacitance components of the resonator, and I(ω) is the current through the LC tank. At resonance frequency, the imaginary components cancel out. The frequency is calculated by setting the imaginary part of (6.67) to zero, yielding

$$ {{f}_{vco}}=\frac{1}{2\pi \sqrt{LC}}$$

(6.68)

where ω = 2πf_vco. Since the tank is not ideal, the amplitude is bounded by R_p. More specifically, the amplitude of the tank is given by

$$ {{V}_{swing}}={{R}_{p}}\cdot I $$

(6.69)

An alternative, yet equivalent to (6.46), definition to the quality factor, Q, of the tank can be defined as

$$ Q={{\omega }_{vco}}\frac{energy~stored}{avg~power~dissipated} $$

(6.70)

Considering a peak current in the tank, I_pk, and using (6.68)–(6.70) can be expanded as

$$ Q=\frac{\frac{1}{2}C{{[{{I}_{pk}}{{R}_{p}}]}^{2}}}{\frac{1}{2}I_{pk}^{2}{{R}_{p}}}=\frac{{{R}_{p}}C}{\sqrt{LC}}=\frac{{{R}_{p}}}{\sqrt{L/C}}$$

(6.71)

Note that equivalent expressions for Q can be given as

$$ Q=\frac{{{R}_{p}}}{{{\omega }_{vco}}L}={{\omega }_{vco}}{{R}_{p}}C $$

(6.72)

Similar expressions for Q can be given for a series RLC resonator, where

$$ Q=\frac{\sqrt{L/C}}{{{R}_{s}}}=\frac{{{\omega }_{vco}}L}{{{R}_{s}}}=\frac{1}{{{\omega }_{vco}}{{R}_{s}}C} $$

(6.73)

where R_s is the resistance associated with series resonance. In a practical LC tank, both the inductor and capacitor have a series parasitic resistance component, as shown in Fig. 6.35. As shown, the series equivalent resistance has been converted into a parallel resistance. It can be shown [29] that the R_p and R_s are related by the following equation

Fig. 6.35

Practical LC tank and its equivalent circuit

$$ {{R}_{p}}={{R}_{s}}{{({{Q}^{2}}+1 )}^{2}}$$

(6.74)

This relationship hold only for narrow frequency ranges around the resonance frequency and for sufficiently high values of Q (Q > 10). The resulting total Q of the tank is given as

$$ {{Q}^{-1}}=Q_{C}^{-1}+Q_{L}^{-1} $$

(6.75)

Where Q_C is the tank Q assuming degradation from the capacitor series resistance only and Q_L is the tank Q assuming degradation from the inductor series resistance only. As will be shown later, Q_L dominates at high VCO frequencies, whereas Q_C dominates at low VCO frequencies.

VCO Topologies

The most popular method of creating a negative transconductance element is to use a cross-coupled MOSFET pair. There are three possible topologies for the LC VCO each with a different cross-coupled MOSFET topology, as shown in Fig. 6.36. In all three topologies, a current source is used to provide current to the VCO. The first of these topologies is the CMOS −g_m based LC VCO. The main advantage of this type of topology is that it can provide symmetric rise and fall waveforms, lowering the flicker noise corner as was explained by (6.64). Symmetric rise and fall times can be adjusted to the first order by properly adjusting the ratio of PFET to NFET devices. This adjustment, of course, would misalign as the process is shifted. The disadvantage of a CMOS −g_m based LC VCO is that it requires extra headroom due to the additional v_{ds, sat} required in cascading PFET and NFET devices along with a current source, when compared to an NMOS or PMOS only −g_m based LC VCO. This limits the maximum voltage swing allowed in the VCO before saturating the VCO signal, which causes the far out noise of the LC VCO to be inferior to that of NMOS or PMOS only −g_m based LC VCOs for the same current consumption in the tank. Note that the center tapped inductor in the PFET only or NFET only LC VCOs can be substituted by a low-impedance bias reference to avoid the voltage swing across the LC tank from going above V_DD or to a negative voltage, respectively. Also note that the current source shown in Fig. 6.36a can be inserted on top, connected to V_DD, as shown in the figure or alternatively at the bottom, connected to ground.

Fig. 6.36

LC VCO topologies based on a CMOS −g_m, b NMOS −g_m and c PMOS −g_m

In low-voltage applications, there may not be enough headroom to add a current source. This is especially true of a CMOS LC VCO, shown in Fig. 6.36a. In order to reduce the required headroom, the current source may be substituted with a resistor. The current across the resistor may be regulated by a feedback amplifier controlling the power supply of the VCO, as shown in Fig. 6.37. Care must be taken in the choice of the resistor. Too large of a resistor value would increase the required headroom, perhaps more than that of a current source. Too small of a resistor value would load the LC tank reducing the effecting swing across the tank, as will be shown later. The reference voltage at the input of the comparator is set by a replica circuit that forces the current through the VCO to match that of the current source of the replica circuit (if the resistor in the VCO is equal to that of the replica bias reference). The design of the error amplifier is critical as it determines the overall power supply rejection and can be a source of phase noise in the VCO.

Fig. 6.37

Low-voltage LC VCO

The design of the VCO involves choosing the center frequency, frequency tuning range, and phase noise performance of the VCO. Since an LC tank is used for the VCO, the center frequency of the VCO was given in (6.68). The total inductance is the designed inductor plus any parasitic inductance in the LC tank. The parasitic inductance becomes important for VCOs with center frequency greater than 5 GHz, necessitating a 3-D EM solver for proper inductance extraction. The total capacitance includes the designed capacitor as well as parasitic capacitances of the MOSFET devices as well as the wire trace connecting the LC tank components.

Varactors

The designed capacitance of the VCO consists of a varactor and a tuning capacitor. A varactor is a device whose capacitance varies with the applied voltage. One terminal of the varactor is the loop filter voltage and the other is the VCO tank voltage. This is the device which controls the VCO gain (MHz/V). Since the total capacitance in the LC tank would consist of the varactor and other tank capacitances, the varactor area would have to be increased if a larger VCO gain is required. Hence higher VCO gain is problematic for two main reasons: more noise due to the varactors and the maximum frequency of the VCO is reduced. Separating the capacitance in (6.68) into a fixed and voltage-dependent terms, then differentiating the equation with respect to voltage applied to the varactor yields an expression for the VCO gain that is given as

$$ {{K}_{v}}=-\frac{1}{2}\cdot L\cdot \frac{dC(V)}{dV}\cdot {{f}_{c}}$$

(6.76)

where f_c is the center frequency of the VCO given by (6.68), L is the inductor of the LC tank, and $\frac{dc(V)}{dV}$

is the large signal gain of the varactor given by the slope of its C–V curve.

There are two types of MOS-based varactors that can be implemented. The first, inversion mode varactor, is shown in Fig. 6.38 [30]. Shown is a PFET device in an n-well. Note that the source and drain are shorted together and form the positive terminal of the varactor. The negative terminal of the varactor is the gate node. As the source-to-gate voltage is increased, an inversion layer forms under the channel. This increases the capacitance seen across the varactor terminals to be equal to the gate oxide capacitance, C_ox. This is equal to C_max shown in Fig. 6.38. As the source-to-gate voltage is reduced to a voltage below the absolute value of the PFET threshold voltage, V_T, the inversion layer disappears the capacitance now consists of the gate-oxide capacitance in series with the depletion capacitance in the N-well region. The presence of the depletion region is guaranteed since the N-well is biased to the highest possible potential, V_DD. The total capacitance is nearly half of the gate-oxide capacitance, and is shown in Fig. 6.38 as C_min. The channel resistance in both inversion and depletion region determine the overall noise performance of the varactor.

Fig. 6.38

Inversion mode varactor a device cross-section and b C–V curve

Although the graph shown in Fig. 6.38 shows a steep C–V curve, one must keep in mind that this is an AC C–V curve. When using a varactor in a VCO, the actual capacitance seen by the tank is a time averaged capacitance as the V_SG is changed from minimum VCO voltage swing to its maximum relative to the loop filter ­voltage. As a result, the large signal C–V curve is much shallower than the AC C–V curve, resulting in much more linear tuning voltage characteristics of the VCO.

Another popular implementation of a MOS varactor is the accumulation mode varactor, sometimes known as an nfet-in-nwell varactor, shown in Fig. 6.39 [31]. Note that since the diffusion materials are n + materials inserted in an N-well, it is not possible for an inversion layer to develop. This fact gives an advantage of an accumulation mode varactor over an inversion mode varactor in terms of its noise performance. As the gate voltage is increased beyond the V_T of the device, like particles, namely electrons, start to accumulate across the channel, creating a conduction band between the source and drain. The capacitance measured from the gate to the diffusion regions is now given as C_ox, or C_max as shown in Fig. 6.39b. When the gate voltage is reduced by the source voltage such that V_GS < V_T, then the device enters depletion region of operations, where a depletion region develops across the channel. This creates a series capacitance with C_ox. The effective capacitance of the varactor is now reduced by half.

Fig. 6.39

Accumulation mode varactor a device cross-section and b C–V curve

Varactors used in VCOs depend on the topology of the loop filter. If a single-ended loop filter is used, then the varactors are arranged as shown in Fig. 6.40. Shown in the diagram is a parallel bank of varactors. If larger K_V (VCO gain) is required, more varactors are used. The voltage level of V_ref is chosen in such a way that the varactor C–V curve is centered for a desired loop filter voltage, usually V_DD/2. Also note that the reference voltage is heavily filtered to avoid any noise degradation due to the reference voltage circuitry. The varactors are then AC coupled from the LC tank to allow independent choice of the DC operating points of the tank itself, which are chosen to minimize phase noise. In differential PLL designs, the reference voltage may be substituted for the second polarity of the differential loop filter.

Fig. 6.40

Practical use of varactors in a an LC VCO

Capacitor Tune Array

Once the VCO center frequency is chosen, the VCO frequency range is determined by the capacitor tune array implementation. The capacitor tuning array consists of digitally tunable capacitor cells. The capacitance of each cell varies between a C_min and a C_max. The ratio between the C_max/C_min determines the tuning efficiency of each cell. The absolute value of C_min and C_max determine the resolution of the capacitor array. The capacitor array can be viewed as a capacitor digital-to-analog converter (DAC), where the output is capacitance, instead of a voltage or current. In this case, the partitioning and sizing of capacitor elements is similar to the DAC design discussion in Sect. 5.6.

The VCO gain (K_v) and the C_min and C_max are chosen such that there are no frequency gaps in the VCO frequency range. Frequency gaps arise when the maximum frequency in one tuning array setting is less than the minimum frequency in the next tuning array setting. This can result from process, voltage, and temperature variation altering both the C–V curve as well as the C_min and C_max values. One way to avoid frequency gaps is to overlap the frequency tuning curves as shown in Fig. 6.41. The end points of each line represent the C_min and C_max of a capacitor tune setting corresponding to an f_max and f_min, respectively. The continuous set of points along of each line represent the set of frequencies corresponding to tuning the varactor capacitance by the PLL’s loop filter voltage (x-axis). As the curve shows, there is significant overlap in frequency between adjacent capacitor tune settings. This is done in order to avoid any frequency gaps that can arise over process, voltage and temperature variations. Another point to note is that both the spacing between adjacent capacitor tune settings and VCO gain increase as the frequency increases. This is due to the increased sensitivity of the LC tank frequency to variations in the capacitor as the LC product is reduced.

Fig. 6.41

Typical VCO tuning curves

The typical capacitor cell element is shown in Fig. 6.42. Typically, the sizes of the cell elements are binary weighted by the bit setting it controls. For example, a 5-bit capacitor cell array would contain 5 elements of the schematic shown in Fig. 6.42, with sizes of 1x, 2x, 4x, 8x, 16x, and 32x of a unit size element corresponding to bits 0, 1, 2, 3, 4, and 5, respectively. Due to varying dimensions for the capacitors and MOSFET elements, the contribution of boundary capacitances such as the fringe and sidewall capacitances to the overall capacitance of the capacitor cell element differ. These differences can create a nonmonotonic behavior in the output frequency of the VCO, which is most pronounced near the mid-codeword when codeword changes from 01…1 to 10…0 or vice versa. As was shown in Sect. 5.6, the DNL in this case is $\sqrt{{{2}^{N-1}}}\sigma$ where $\sigma$ is the standard deviation in the capacitance of an LSB capacitor cell element. Designing for the worst case DNL would necessitate large overlap between the capacitor step sizes, which would reduce the overall frequency tuning range.

Fig. 6.42

Capacitor cell element

As was also shown in Sect. 5.6, this nonmonotonicity can be reduced by using thermally weighted unit elements of the schematic shown in Fig. 6.42. The disadvantage of this approach is that it incurs a large parasitic interconnect capacitance overhead, which limits the maximum attainable VCO frequency. A compromise approach is to use binary weighted elements for the LSBs and thermally weighted elements for the MSBs, similar to a segmented DAC.

The limitations of C_min and C_max values are important to understand. Figure 6.42 can be redrawn showing the parasitic capacitances as shown in Fig. 6.43. When the CTL signal is low, the NFET transistor is off and the C_ds is now in series with the two C₁ capacitances, resulting in a C_min capacitance. The overall differential capacitance is effectively lowered by the series capacitance between the source and drain of the NFET transistor. This capacitance is given by the series capacitance of C_gs and C_gd in parallel with C_ds. The equivalent lumped capacitance, C_x, can be given as

Fig. 6.43

The capacitor tuning cell with parasitic capacitances shown

$$ {{C}_{x}}={{C}_{ds}}+\frac{{{C}_{gs}}{{C}_{gd}}}{{{C}_{gs}}+{{C}_{gd}}}$$

(6.77)

The resistor in series with the gate of the NFET device is necessary in order to prevent signal losses to ground from the C_gd and C_gs capacitances to the preceding inverter. The source-to-bulk capacitance, C_sb, and the source-to-drain capacitance, C_db, form impedances to ground. These two capacitors, C_sb and C_db, (along with any other parallel parasitic capacitance to ground) is referred to as C_p1 and C_p2, respectively. The purpose of biasing the source and drain through the two resistors is to maximize the capacitance difference between the C_min and C_max by utilizing the fact that the FET capacitances are voltage dependent. The C_min capacitance can then be given by

$$ {{C}_{min}}=\frac{{{C}_{1}}}{1+\frac{C_{1}^{2}}{{{C}_{x}}[{{C}_{1}}+{{C}_{p1}}]}+\frac{{{C}_{x}}{{C}_{1}}}{[{{C}_{1}}+{{C}_{p1}}][{{C}_{x}}+{{C}_{p1}}]}}$$

(6.78)

It can be shown that for the ideal case of C_p1 = C_p2 = 0 and C_x→∞, (6.78) reduces to C₁/2.

When the CTL signal is high, the NFET transistor is high and the R_ds, the channel resistance, becomes important. In this state, the differential capacitance of the capacitor tuning cell is maximized, since the series C_ds capacitor is now shunted by a low-impedance R_ds, resulting in a C_max capacitance. Using Fig. 6.43, the impedance across the tuning capacitor cell at the CTL high state can be shown to be

$$ {{\left. {{Z}_{tune}}(s) \right|}_{CTL=1}} = \frac{s + \frac{1}{R\left[C_1 + C_{p2}\right]}}{sC_{p1}\left[s+\frac{C_1 + 2C_{p2}}{C_{p1} R\left[C_1 + C_{p2}\right]} \right] }$$

(6.79)

which is a two pole, one zero system. Figure 6.44 shows how Z_tune(s) varies over frequency. For most practical applications, the oscillating frequency is beyond the second pole shown in the figure. Considering an “equivalent” capacitance, C_eq, that matches the curve at high frequencies (frequencies beyond the second pole), the equivalent C_max can be computed. Equating (6.79) to $\frac{1}{s{{C}_{eq}}}$ and noting the C_eq is C_max results in

Fig. 6.44

Impedance of tuning capacitor cell on the C_max state

$$ C_{max} = \frac{C_{p1} \left[s+\frac{C_1 + 2C_{p2}}{C_{p1} R \left[C_1 + C_{p2} \right]} \right]}{s + \frac{1}{R \left[C_1 + C_{p2}\right]}}$$

(6.80)

It is important to note that the value of equivalent C_max is frequency dependent.

The noise limitations of the capacitor tuning array element are also important to understand. As was shown in Fig. 6.35 and (6.75), the total R_p, the equivalent resistance in a parallel LC tank, is a parallel combination of the equivalent series resistance of the inductor and the capacitor. The following analysis assumes that the R_p degradation due to the capacitor tuning cells is dominant. When the capacitor array is set to its minimum capacitor setting, the series resistance is equal to R_ds. If the NFET and capacitor sizes are scaled with the bit weighting, it can be assumed that the equivalent series resistance scales down with increasing parallel capacitor tuning cells turned on (resistors added in parallel). If N is the number of cells turned on and R_p is the equivalent parallel resistance of the LC tank, the resulting output voltage noise can be given as

$$ v_{n}^{2}=\frac{4kT}{{{R}_{ds}}}N\cdot R_{p}^{2} $$

(6.81)

which is the sum of all the current noise density terms from the capacitor tuning elements whose NFETs are turned on times the square of the equivalent output resistance. Note that R_ds is series resistance of a unit capacitor (LSB size). The output swing of the VCO was given by (6.69). Using (6.81) and (6.69) an expression for the output noise can be shown to be

$$ \frac{v_{n}^{2}}{V_{swing}^{2}}=\frac{\frac{4kT}{{{R}_{ds}}}N\cdot R_{p}^{2}}{{{I}^{2}}\cdot R_{p}^{2}}=\frac{4kTN}{{{I}^{2}}{{R}_{ds}}}$$

(6.82)

which shows that the phase noise degrades as more tuning elements are turned on. This means that phase noise is expected to be worse at lower frequencies, due to more elements turned on (assuming the narrow band tuning range of the VCO). One method, as will be seen shortly, to improve phase noise at lower frequencies is to increase the bias current of the VCO.

Negative Transconductance Optimization

The phase noise optimization of an LC VCO depends on several parameters. One important parameter is the choice of negative transconductance value. An equivalent model of the LC VCO is shown in Fig. 6.45, where the losses in the tank are represented by g_tank (g_tank = 1/R_p) and the negative −g_m due to the cross-coupled FETs is represented by −g_FET. In order to sustain oscillation, the tank losses, g_tank must be canceled by ensuring that g_FET > g_tank. The oscillation amplitude will continue to increase until a nonlinearity is reached that causes the large signal gain to be one at the desired oscillation frequency. This nonlinearity may be supply voltage headroom or bias current limitation across the real impedance component of the tank. The oscillation frequency was given by (6.68).

Fig. 6.45

Equivalent model of cross-coupled FET LC oscillator

As long as the amplitude of oscillation is not limited by the circuit’s voltage headroom, increasing the energy in the tank will lead to reduction in phase noise and jitter. Energy stored in the LC tank is

$$ {{E}_{tank}}=\frac{1}{2}CV_{tank}^{2} $$

(6.83)

Substituting (6.66) into (6.81) and solving for the tank voltage swing yields

$$ V_{swing}^{2}=2{{E}_{tank}}{{\omega }^{2}}L $$

(6.84)

Intuitively, this equation would lead one to believe that increasing the inductance alone would result in lower-phase noise. However, in an LC oscillator, the tank’s voltage and thermal noise voltage increase at the same rate. Under the simplifying assumption that the noise is dominated by upconverted thermal noise (1/f² noise), the ratio of the tank voltage to thermal noise voltage can be shows to be [32]

$$ \frac{V_{swing}^{2}}{\overline{v_{n}^{2}}}=\frac{2{{E}_{tank}}}{kT} $$

(6.85)

where k is Boltzmann’s constant. Using (6.83) and (6.84) the ratio of (6.85) can be rewritten as

$$ \frac{V_{swing}^{2}}{\overline{v_{n}^{2}}}=\frac{I_{bias}^{2}}{{{\omega }^{2}}\left(g_{tank}^{2}L \right)kT} $$

(6.86)

The expression in (6.86) shows that in order to maximize the amplitude to noise ­ratio, the product of $g_{\tan k}^{2}L$ (L/R_p ²) must be minimized for the same current ­consumption. Increasing the bias current also helps to improve the phase noise performance. This equation assumes that the amplitude of oscillation is not limited by supply voltage.

The above analysis is based on the assumption that the tank voltage swing can be increased by increasing the bias current of the LC tank. This region of operation is called the current mode region [33]. If the voltage swing is limited by the power supply (or any other amplitude limiting nonlinearity), the VCO is said to operate in the voltage mode region [33]. Increasing the current further in the voltage mode region only serves to increase the noise with no corresponding increase in tank voltage swing. Furthermore, since saturating the VCO in this manner leads to a distorted sinusoidal output voltage waveform, higher-order harmonic content would grow, which would lead to more noise folding and worse phase noise performance, as was demonstrated in Sect. 6.3.2. The power spectral density of a distorted VCO output waveform is shown in Fig. 6.46.

Fig. 6.46

Noise folding effect in a distorted VCO output waveform

Improving the noise performance once the voltage mode of operation is reached is possible. If the RLC parallel tank resistance, R_p, is dominated by the inductor, then reducing the inductor value would lead to less tank R_p. Consider an LC VCO with inductance L and bias current I. If the swing is maximized such that it is on the edge of the voltage mode of operation and the inductance L is reduced to L/2, the voltage swing is now one-half the original amplitude since R_p has been reduced by a factor of 2. Moreover, the tank is now operating well into the current mode of operation. Increasing the current by a factor of 2 would increase the swing back to the original value. Since the noise (assuming it is dominated by thermal noise) increases with the $\sqrt{I}$, the noise increases by $\sqrt{2}$; however, the voltage noise is obtained by multiplying by $R_{p}^{2}$, which has been reduced by a factor of 2. This leads to $\sqrt{2}$ reduction in noise compared to the original case. This means that the original LC VCO with inductance L and bias current I has 3 dB higher phase noise thank an LC VCO with half the inductance and double the current (assuming the original LC VCO has been optimized to be at the edge of voltage mode of operation).

Summary

In this chapter, wideband frequency synthesizer design has been reviewed. At the heart of a frequency synthesizer is a PLL. The requirements for PLLs in a wireless transceiver were given. This mainly consists of requirements stemming from ­reciprocal mixing effect as well as aperture jitter in both the ADC and the DAC. Linear analysis of the PLL was given, including full analysis of the effect of the various noise components in a PLL. This was followed by a more in-depth nonlinear noise analysis of both the charge pump and the VCO components in a PLL.