Ultra-Low-Voltage Clock References

Abstract

Clock references are indispensable circuit modules. The Internet of Things (IoT) devices, in particular, usually require a reference with high spectral purity for the phase-locked loop to generate the carrier signal and a low-power always-on reference to serve as the timer. This chapter discusses the design of two clock references operating at ultra-low supply voltage (<0.5 V) for energy-harvesting Internet-of-Things sensor nodes. The first is a sub-0.5 V 16/24 MHz crystal oscillator with a fast startup feature to accommodate the periodic duty-cycling scheme of the Internet-of-Things device. We prototyped the design in 65 nm CMOS (complementary metal-oxide semiconductor). The second is a 0.35 V 2.1 MHz fully integrated relaxation oscillator implemented in 28 nm CMOS. It features an asymmetric swing-boosted RC (resistor-capacitor) network and a dual-path comparator to surmount the challenges of sub-0.5 V operation while achieving temperature resilience. This chapter elaborates both designs in detail.

1 Introduction

An Internet of Things (IoT) network is a crucial component of different revolutionary concepts such as Industry 4.0 [1] and smart homes/smart cities [2]. The IoT devices within the networks gather vast amounts of data for dedicated processors/AI models, which boost the precision of analyses. An essential criterion for the IoT device is low power consumption. Ultra-low-power (ULP) radio, intermittently turned on for a short amount of time for data transmission to reduce the average power of the IoT device, is popular for the IoT device as it reduces the power consumption of power-hungry blocks such as the transceiver (TRX) and extends the lifetime of the device [3]. The system will place the device into sleep mode for a specific period, with only critical blocks such as memory and wakeup timers powered on for timing purposes.

On the other hand, there is a trend to power the IoT device with energy harvesters to realize perpetual operation. As the battery has a finite lifetime, there may be chances that the IoT device will miss critical data if it runs out of battery. Also, replacing batteries will be a tremendous task considering that there will be trillions of IoT devices. Further, the battery may pose environmental issues and create safety risks if not handled properly. By replacing the batteries with energy harvesters (EH), the lifetime of the device increases, and we can obviate the labor to replace the batteries, which otherwise requires a substantial effort. EH, such as solar cells (typical available power indoor: 10–100 μW/cm²) and thermoelectric generators (typical available power: 10–1000 μW/cm²), are promising in this perspective [4,5,6]. Yet, they usually only output voltage with amplitudes ~0.3 V–0.4 V and are unstable with environmental factors (temperature and light intensity) [4]. We can use a boost converter to stabilize and step up the voltage to the standard I/O voltage, but this increases the footprint (cost) and power consumption of the IoT device. These criteria open a prospective research direction for ultra-low-voltage (ULV) circuits, powered directly by these energy harvesters, and avert the penalties of the interim converters.

Clock references are indispensable parts of the TRX. Wide-ranging purposes such as the low-power wakeup timer, the phase-locked loop, the data converters, etc. require different clock references. Hence, this chapter elaborates on the design and measurement results of two ultra-low-voltage clock references in deep-submicron silicon processes. Section 2 introduces the regulation-free sub-0.5 V 16/24 MHz crystal oscillator for energy-harvesting Bluetooth Low Energy (BLE) radios implemented in 65 nm CMOS [7], whereas Sect. 3 demonstrates a fully integrated 0.35-V 2.1 MHz temperature-resilient relaxation oscillator using an asymmetric swing-boosted RC network implemented in 28 nm CMOS [8].

2 Regulation-Free Sub-0.5 V 16/24 MHz Crystal Oscillator for Energy-Harvesting BLE

2.1 Motivation

The crystal oscillator (XO) is an essential circuit module for modern TRXs. It provides a stable clock reference for different parts such as data converters, phase-locked loops, sensors, etc. Despite its excellent frequency stability, it can take a few milliseconds for the XO to settle into the steady state [9,10,11] without any fast startup technique [12] due to the high-quality factor of the crystal (~10⁵). This startup time (t_s) dominates the “on” latency of the radio, and its startup energy (E_S) may significantly degrade the effectiveness of duty-cycling of an ultra-low-power radio. If the active energy (E_TRX) of a TRX is 1280 nJ (on-time of 128 μs [13] and active power of 10 mW [14]), the percentage of energy spent for starting the XO in every working cycle is ~42% for E_S of 1000 nJ for a conventional XO and a duty cycle of 0.1%. Such a percentage will go further up as recent circuit techniques can manage to suppress the active power of the TRX (P_TRX) [15,16,17]. Then, reducing E_S for the ULP radios is of paramount importance to reduce its average power consumption. Recent efforts in both academia and industry succeeded in shortening the t_s and E_S of the XO [13, 14, 18,19,20,21,22,23].

This section reports a regulation-free sub-0.5 V XO according to the system aspect of the EH BLE radios described in [24,25,26,27]. Unlike the existing fast startup XOs based on standard or I/O voltages to power up their inverter-like or active-load amplifiers [13, 18,19,20,21], the proposed XO is ULV-enabled by using single-/multi-stage resistive-load amplifiers [28]. This architecture circumvents the ineluctable voltage headroom limit, rendering it compatible with the ULV application. Specifically, we propose a dual-mode g_m scheme and a Scalable Self-reference Chirp Injection (SSCI) technique for the XO to surmount the operating challenges in both startup and steady state (Fig. 1). The reported XO includes load capacitors of 6 pF and suits common commercially available crystals. Yet, we can also apply the technique to crystals with different load capacitances.

Fig. 1

Overview of the proposed XO and illustration of t_S improvement by two techniques: SSCI and inductive three-stage g_m. The L_M, C_M, and R_M are the modeled inductance, capacitance, and resistance of the crystal, respectively, whereas C_S is the crystal’s stray capacitance

2.2 Fast Startup XO Using Dual-Mode g_m Scheme and SSCI

For a crystal’s resonant frequency (f_m) at tens of MHz, its t_s (milliseconds) dominates the “on” latency of a duty-cycled radio, raising the average power consumption. In addition, for energy-limited EH sources, the E_S of the XO is crucial as it may demand a large instant current from the EH source or reservoir. Recent XOs [13, 18,19,20,21,22] succeeded in reducing both t_s and E_S. Herein, we propose two techniques, the dual-mode g_m and the SSCI, for balancing the XO performances in both startup (i.e., t_s and E_S) and steady state [i.e., power consumption and phase noise (PN)]. The envelope of the XO during startup at the time t is

$$ {A}_{\textrm{env}}(t)={A}_i\bullet {e}^{\frac{R_{\textrm{N}}-{R}_{\textrm{M}}}{2{L}_{\textrm{M}}}t}, $$

(1)

where A_i is the initial amplitude and R_N is the negative resistance of the overall impedance viewed from the crystal core. The L_M and R_M are the motional inductance and resistance of the crystal, respectively. The aim of the SSCI is to increase A_i instantly after enabling the XO, while the dual-mode g_m allows a boosted R_N afterward. They together bring down t_S without momentarily raising the startup power, culminating in a lower E_S and a relaxed power-source design.

2.2.1 Scalable Self-Reference Chirp Injection (SSCI)

Signal injection to the XO can bring down t_s if the injection frequency is close to f_m of the crystal [19]. Instead of waiting for the XO to build up its oscillation amplitude, we can use an auxiliary oscillator (AO) to excite the crystal. Yet, due to the high Q nature of the crystal, such signal injection is only effective if its frequency error from f_m is <0.5% [13]. There were several signal injection techniques for kick-starting the XO reported. We can categorize them into three groups: constant frequency injection (CFI) [18, 21, 22], dithering injection [13], and chirp injection (CI) [19].

CFI injects a clock signal into the crystal with a constant frequency precisely matching f_m. Albeit this scheme is very efficient and simple in concept, the AO requires calibration as well as a delicate design that will be challenging in a sub-0.5 V design. As an example, the XO in [21] achieves t_s values of 58/10/2 μs from 1.84/10/50 MHz crystals. Yet, it has a supply voltage of 1 V. Also, the ring oscillator entails frequency calibration after fabrication.

Dithering injection toggles the AO frequencies to compensate for the frequency deviation caused by temperature and voltage variations. As such, the injection signal can cover a wider frequency range than that of CFI. Still, trimming is necessary to compensate for the process variation. When compared with CFI, its effect on shortening t_s is lower since the signal power spreads to a wider spectrum. For instance, the XO in [13] exhibits a slashed t_S of <400 μs by using dithered-signal injection (dithered step size: 2%).

Here, we consider CI to be more robust and low cost, as it relies on a frequency-rich signal to excite the crystal and avoids frequency calibration. The principle is alike dithering but covers a wider frequency range. It gradually sweeps the oscillating frequency and progressively decreases/increases the frequency. As such, this chirping sequence can generate a spectrum between the highest frequency f_H to the lowest frequency f_L, as evinced by its Fourier transform [29]. If f_L < f_m < f_H regardless of PVT variations, the crystal will persistently receive the power. Despite its weaker effectiveness on t_S reduction since the power spreads to a wider band, CI has the benefit of no trimming on the AO. It is especially suitable for low-cost and ULV radios, where there is the possibility of exacerbating the frequency variation of the AO against voltage and temperature. In [19], a R_N-boosting technique applies together with CI, showing a t_S of 158 μs without trimming or calibration on the AO. Still, the related RC sweeping unit for modulating the frequency of the AO is area hungry (estimated ~90% of the chip area) due to its large time constant (at the order of 10 μs) for generating the chirping sequence. Table 1 summarizes the key features of the three signal injection techniques.

Table 1 Overview of different signal injection techniques to kick-start the XO

Herein, we introduce the SSCI (Fig. 2) that only entails an untrimmed oscillator with relaxed precision. Its frequency range can easily cover f_m variation against PVT. Unlike the RC-based chirping [19], we incorporate a five-stage RO with a finite state machine (FSM) to control the oscillating frequency of the RO via a cap-bank. Subsequently, the circuit can generate the chirping sequence by referencing its own signal and requiring no area-hungry RC units to modulate the oscillating frequency. The FSM counts the number of pulses and sequentially raises C_OSC by sending the control signal f_ctrl to the RO. Additionally, compared to the analog sweeping technique in [19], the FSM can digitally scale the total injection time (t_CI), decided by the number of exciting cycles at each cap-bank value C_OSC:

$$ {t}_{\textrm{CI}}=N\times \sum \limits_i{t}_i, $$

(2)

where N is the number of cycles to repeat at each C_OSC and t_i is the period of a single cycle at i-th C_OSC. The average amplitude of oscillation on the crystal after the chirping sequence is proportional to $\sqrt{t_{\textrm{CI}}}$ [19, 29]. Thus, N can be programmed to adjust t_CI, rendering the XO easily compatible with different crystal parameters (i.e., an optimum t_CI depends on L_M, R_M and R_N (C_S) [19]). This digital-intensive architecture is more area-efficient. The oscillation signal at the RO has a varying duty cycle with VT variation. To maximize the injection energy (i.e., 50% duty cycle), the chirp-modulated signal is a div-by-2 output of the RO. This output serves as both the exciting signal for the crystal via the output driver and the trigger signal for the FSM. After the injection, the FSM automatically powers down the RO.

Fig. 2

Proposed SSCI. It generates a chirping signal to kick-start the XO using an untrimmed RO with relaxed precision. The FSM (finite state machine) provides feasibility to scale t_CI, accommodating different crystal packages (i.e., L_M and C_S)

2.2.2 Dual-Mode g_m Scheme

The XO using a one-stage g_m (A_XO-1), especially for the Pierce oscillator, is popular as it can optimize the steady-state PN [13, 19,20,21]. The g_m offers a negative resistance compensating for the equivalent resistance of the crystal. Its value also determines the growth of the oscillation amplitude before the XO reaches the steady state.

From Fig. 3a, by omitting the resistive loss induced by A_XO-1, the impedance between the I/O (Z_amp-1) becomes

$$ {Z}_{\textrm{amp}-1}=-\frac{g_{\textrm{m}}}{4{\omega_0}^2{C_{\textrm{L}}}^2}+\frac{1}{j{\omega}_0{C}_{\textrm{L}}}, $$

(3)

where C_L is the designated crystal’s load capacitance and ω₀ is the angular oscillating frequency 2πf₀. With Z_amp shunted by the crystal’s stray capacitance (C_S), it affects the negative resistance (R_N) of the overall impedance looking from the crystal core (Z_C):

$$ {R}_{\textrm{N}}\equiv -\operatorname{Re}\left({Z}_{\textrm{c}}\right)=\frac{-\operatorname{Re}\left({Z}_{\textrm{amp}}\right)}{{\left[{\omega}_0{C}_{\textrm{s}}\operatorname{Re}\left({Z}_{\textrm{amp}}\right)\right]}^2+{\left[1-{\omega}_0{C}_{\textrm{s}}\operatorname{Im}\left({Z}_{\textrm{amp}}\right)\right]}^2} $$

(4)

Fig. 3

XO using (a) a one-single g_m (A_XO-1) for the steady state and (b) a three-stage g_m (A_XO-3) for the startup

If ω₀C_S|Z_amp| ≪ 1, we can have R_N ≈ −Re(Z_amp) that matches the expression in [13] for A_XO-1. A large R_N favors more t_S reduction according to Eq. (1). Yet, for |Z_amp| to be comparable with 1/ω₀C_S [i.e., a higher g_m and thus |Re(Z_amp)| to speed up the startup], we have to cogitate the effect from C_S. Then, we can deduce the specific R_N of A_XO-1 (i.e., R_N,1) from Eq. (4) as

$$ {R}_{\textrm{N},1}=\frac{4{g}_{\textrm{m}}{C_{\textrm{L}}}^2}{{\left({g}_{\textrm{m}}{C}_{\textrm{s}}\right)}^2+16{C_{\textrm{L}}}^2{\omega_0}^2{\left({C}_{\textrm{L}}+{C}_{\textrm{S}}\right)}^2}, $$

(5)

Taking the derivative of Eq. (5), we can obtain the maximum value of R_N,1 with respect to g_m at a fixed C_L:

$$ {R}_{\textrm{N},1,\max }=\frac{C_{\textrm{L}}}{2{\omega}_0{C}_{\textrm{s}}\left({C}_{\textrm{L}}+{C}_{\textrm{s}}\right)}, $$

(6)

where we apply g_m = 4ω₀C_L(1 + C_L/C_s). Obviously, Im(Z_amp-1) can only be negative (capacitive) for A_XO-1, and R_N,1 has an upper limit if only g_m is the sizing parameter [19, 20]. For instance, the R_N,1 is limited to 1.2 kΩ with C_S = 2 pF, f₀ = 24 MHz and C_L = 6 pF, even if we apply an oversized g_m = 14.5 mS. There were efforts to raise R_N,1 by increasing g_m or tuning C_L temporarily during the startup [20, 30, 31]. Yet, increasing g_m incurs larger power consumption and is unfavorable toward the reduction of E_S. Further, Eq. (6) binds R_N,1, with a maximum of 1/2ω₀C_S (i.e., 1.66 kΩ in the above example when C_L ≫ C_S and g_m ≈ 4ω₀C_L²/C_s).

Inspecting Eq. (4), if a positive Im(Z_amp) is possible to counteract the effect of C_S, we can boost R_N to surmount the aforesaid R_N limit. The idea is to mimic a μH-range inductor on-chip for this purpose. Interestingly, a three-stage g_m (A_XO-3) with designated capacitive loads (Z_o1–2) can effectively mimic an inductive effect during the startup (Fig. 3b). Although [32] applied a multistage g_m to save the XO’s steady-state power, here, we explore first its inductive feature for t_S reduction. For A_XO-3, we define its Z_amp as Z_amp-3. We can maneuver both the Re(Z_amp-3) and Im(Z_amp-3) between a positive and a negative values by adjusting the inter-stage impedances, as demonstrated in [7]. For instance, if we set g_m1,2 = 0.4 mS, g_m,3 = 1.5 mS, r_o1,2 = 7 kΩ, C_L = 6 pF, ω₀ = 2π × 24 MHz, and C_o1 = C_o2 = 0.5 pF, we can obtain a Z_amp-3 = −1.6 + 1.2 jkΩ. We can utilize the Im(Z_amp-3) > 0, manifesting that Z_amp-3 is inductive, to mitigate C_s and break the limitation (Eq. (6)). Foregoing, we can have Re(Z_C-3) = −2.4 kΩ due to the inductive A_XO-3. Then, we can achieve a higher R_N even with similar power consumption when compared with the A_XO-1, enabling an energy-efficient startup. Due to the intricate expression of R_N,3, we do its optimization numerically, before proceeding to the transistor level implementation. Besides, the technique is also applicable to different f₀. Apparently, for the same power budget, A_XO-3 is inferior to A_XO-1 in terms of the steady-state PN, as each stage shares a smaller bias current and the noises accumulate. Also, Im(Z_C-3), which determines the XO’s oscillating frequency, deviates from the designated value due to the presence of C_o1 and C_o2. This affects the accuracy of f₀. Consequently, it is desirable to implement a dual-mode g_m scheme that can balance the startup and steady-state performances. During the startup where the PN and accuracy of f₀ are irrelevant, we enable A_XO-3 and connect to the crystal to attain a larger R_N for fast startup. When the crystal gains sufficient energy for oscillation, A_XO-3 is off and disconnected from the crystal while A_XO-1 takes over to sustain the oscillation. As a result, the XO can benefit from both A_XO-3 (fast startup) and A_XO-1 (low PN and accurate f₀).

2.3 Transistor-Level Implementation

We design the core elements of the XO (e.g., A_XO-1, A_XO-3, and RO) to operate below a 0.5 V V_DD. Only the static and DC circuits (digital logics and constant-g_m bias circuit) operate at 0.7 V to facilitate the design. These circuits, mostly powered off during the steady state, consume <5 μA. Thus, an on-chip switched capacitor charge pump can easily generate the 0.7 V supply and share it with other blocks at the system level as described in [26].

Subthreshold common-source (CS) amplifiers with resistive loads (Fig. 4a, b) constitute the basis of both A_XO-1 and A_XO-3. Unlike other solutions that use current-source loads [13, 20, 21], the resistive load aids in preserving a moderate g_m even with V_DD < 0.35 V, for a small bias current (simulated at I_dc = 100 μA). For instance, the simulated g_m of A_XO-1 is 1.3 mS at V_DD = 0.3 V and −40 °C, being four times higher than that of the current-source load (assuming an identical g_m with V_DD = 0.35 V at 20 °C). Further, at high temperature, the intrinsic output resistance of the transistor decreases rapidly. This affects the stability of R_N and causes variation on t_s, especially for A_XO-3. The A_XO-1 with resistive load has a trade-off of lower immunity to the power supply noise (noise power from V_DD modulated to the output of XO with resistive load that is 3 dB larger than its current-source-load counterpart at 1 kHz offset). Also, it has a large f₀ variation with the g_m of the A_XO-1 not fixed. Still, this is manageable for the BLE standard (< ±50 ppm [33]), as well as other IoT protocols (e.g., ZigBee: ±40 ppm). A small nominal I_dc of 100 μA is adequate for the expected PN.

Fig. 4

Circuit implementation of (a) A_XO-1 and (b) A_XO-3

A feedback resistor R_F self-biases A_XO-1, whereas A_XO-3 is an AC-coupled three-stage CS amplifier aided by a constant-g_m bias circuit. As the g_m of the A_XO-3 has a considerable impact on R_N,3, the constant-g_m bias circuit secures A_XO-3 to be inductive and a stable R_N,3 for robust-and-fast startup against PVT. We choose the channel lengths of the transistors such that their output resistances are ~10× larger than the resistors R_1–3. This soothes the temperature dependency of R_N,3 as R_1–3 and then dominates r_o1–3. We design A_XO-3 to have similar power consumption (~100 μA) as A_XO-1. As such, the power consumption does not vary instantaneously, easing the design and layout of the power supply. Each current branch includes CMOS switches where we can isolate A_XO-1 or A_XO-3 from the crystal, while lowering their leakage power (simulated <14 nW at 0.35 V and 20 °C) when disabled. Their sizes allow that their on-resistances are negligible when compared with R_1–3.

Both the parasitic capacitances of the transistors and the finite I/O resistance of A_XO-3 affect the R_N,3. Thus, we should further optimize R_N,3 via simulation. The total g_m budget is 2.3 mS (total bias current: 100 μA, assuming a g_m/I_D = 23 V⁻¹), with r_o1–3 set according to the g_m of each gain stage. Figure 5a shows the locus plots of Z_amp-1 and Z_amp-3 implemented with practical transistors and integrated passives. Z_amp-1 is capacitive over all frequencies, while Z_amp-3 is inductive over the 13–46 MHz range, which is compatible with different f₀. Optimized at the most popular XO frequency of 24 MHz, the optimum R_N,3 is 2.4 kΩ after paralleling it with a C_S of 2 pF. This result is ~9× higher than R_N,1 under the same g_m budget and surpasses R_N,1,max (Fig. 5b). The boosting effect is insensitive to the frequency between 15 and 34 MHz, under R_N,3/R_N,1 > 6.

Fig. 5

(a) Locus plot of the Z_amp-1,-3 against frequency. (b) Simulated R_N,1 and R_N,3 with a fixed total g_m budget of 2.3 mS and the boosting ratio against frequency

Ideally, we should enable A_XO-3 during the entire startup phase. Yet, the g_m’s of M_1–3 deviate from their small-signal values when the oscillation amplitude is growing. This results in an aggravated R_N,3. As a consequence, the optimum active time of A_XO-3 t_sw is the time when R_N,3 ≈ R_N,1, which means A_XO-3 no longer helps t_s reduction. We can find the optimal t_sw via simulations with measured crystal parameters to avoid any extra detection and control mechanism.

To realize the SSCI, we implement a five-stage RO constituted by CS amplifiers with source degeneration. Compared to the RO with inverters or relaxation oscillator, a RO with CS amplifiers balances the frequency stability and compatibility with the sub-0.5 V V_DD. The source resistor (R_S in Fig. 2) also reduces the variation of the oscillating frequency against V_DD. From simulation, the frequency variation of RO reduces by ~20% over a 0.3–0.5 V V_DD. We set R_D as 36 kΩ. The current consumption of the RO is 20 μA. We implemented the div-by-2 unit and FSM with standard logic.

We designed the f_H and f_L of the SSCI module as 36 and 12 MHz, respectively, chosen to satisfy f_L < f_m < f_H even with PVT variation (Fig. 6). The total size of the C_OSC, simulated to be 135 fF, outputs an f_L of 12 MHz (after div-by-2). Then, we determine the resolution of the cap-bank, decided by the minimum duration of t_CI; since for a complete chirping sequence, we need to sweep all of the states at least once, we set the minimum t_CI (i.e., N = 1) as the resolution (number of pulses), defined in Eq. (2). The optimum t_CI, according to [19] and the measured crystal parameter, becomes 4.6 μs. Thus, we set C_OSC as a binary-coded 6-bit cap-bank (unit cap: 2.14 fF), corresponding to a minimum t_CI of 4 μs with the designated f_H and f_L. Even though there is a discrepancy between the applied and optimum t_CI, it almost does not affect the t_s as the t_CI is only present for a short period when compared with t_s. As the amplitude of oscillation after the CI is proportional to $\sqrt{t_{\textrm{CI}}}$, even the applied t_CI is 13% shorter than the optimum; the amplitude is only 7% smaller. Due to the high growth of the oscillation amplitude of the A_XO-3 (time constant in Eq. (1): 9.33 μs), we can compensate for the discrepancy between the applied and optimum t_CI by the A_XO-3 quickly, for example, the growth of oscillation amplitude countervails the 0.6 μs discrepancy (~1.07×). No significant difference in t_s will emerge, even with PVT variation on the t_CI (Fig. 7).

Fig. 6

(a) Monte Carlo-simulated f_L with V_DD = 0.4 V and T = 90 °C; (b) Monte Carlo-simulated f_H with V_DD = 0.3 V and T = −40 °C. N = 30 for both cases

Fig. 7

Increase in t_s caused by the deviation of t_CI from the optimum duration

The RO generates an oscillating signal at 2f_H with C_OSC = 0 fF (with oscillating frequency governed by the parasitic capacitances) and C_OSC progressively increased by the FSM bit-by-bit according to N to C_OSC = 135 fF wherein the RO oscillates at 2f_L. In this work, the variable N is digitally configurable among 1, 2, 4, and 8.

2.4 Experimental Results and Comparison with State of the Art

The XO, fabricated in 65 nm CMOS with fixed on-chip C_L of 6 pF, occupied an active area of 0.023 mm² (Fig. 8a), of which 36% corresponds to the C_L (Fig. 8b). The target f₀ can be flexible between 16 and 24 MHz. We first verify the SSCI functionality. Figure 9a exhibits the measurement of the oscillating frequency of the RO (after div-by-2) against C_OSC, which is consistent with the post-layout simulation. The average f_L and f_H across five dies at room temperature are 10.93 MHz (σ: 0.32 MHz) and 35.96 MHz (σ: 1.21 MHz), respectively. Figure 9b confirms the chirping sequence with N = 1, and Fig. 9c plots the duration of t_CI against N.

Fig. 8

(a) Chip micrograph. (b) Area breakdown of the XO

Fig. 9

(a) Measured and simulated oscillating frequencies of the RO versus C_OSC at different conditions, robust to cover f₀ of the crystal even with V_DD and temperature variations. (b) Measured chirping sequence (N = 1). (c) Injection duration t_CI against N. For the latter two figures, V_DD = 0.35 V, T = 20 °C

Then, we tested the XO with a 24 MHz crystal (package: 3.2 × 2.5 mm²) without any startup aid at room temperature (20 °C) and V_DD = 0.35 V. The measured crystal parameters L_M, R_M, C_M, and C_S are 11.1 mH, 19 Ω, 3.95 fF, and 1.3 pF, respectively. Under these conditions, we have t_s = 1.3 ms (Fig. 10a). The t_s decreases to 530 μs with A_XO-3 enabled during the startup.

Fig. 10

Measured startup waveform (a) without startup aid and (b) with SSCI and A_XO-3 enabled

We estimate R_N,1 and R_N,3 from the growth of the oscillation amplitude according to Eq. (1), which we can write as

$$ \ln \left(\frac{A_{\textrm{env}}\left({t}_0+\Delta t\right)}{A_{\textrm{env}}\left({t}_0\right)}\right)=\frac{R_{\textrm{N}}-{R}_{\textrm{M}}}{2{L}_{\textrm{M}}}\bullet \Delta t. $$

(7)

By measuring the growth of the oscillation amplitude within a specific time interval, we can estimate the R_N of the XO. For A_XO-1, the growth of oscillation is 1.01×/μs, and thereby we calculate R_N,1 as 230 Ω (Fig. 11), which is close to the prediction (as described in Sect. 2.3). Similarly, we find R_N,3 ≈ 2.2 kΩ. Owing to two reasons, the reduction of t_s is not commensurate with the R_N-boosting ratio between A_XO-3 and A_XO-1. Firstly, as described in Sect. 2.3, M_1–3 will deviate from their nominal operating points and deteriorate R_N,3. We can reveal this by measuring t_s against t_sw (Fig. 12)_. When t_sw is short (<60 μs) where M_1–3 are in the subthreshold region, the small-signal model is still valid to estimate t_s against t_sw (i.e., slope of the curve (~ −10) closely matches with −R_N,3/R_N,1 + 1). As t_sw further increases, the oscillation drives M_1–3 away from its original operating point and worsens R_N,3. Hence the slope of the curve declines and eventually reaches zero whereas the A_XO-3 no longer aids t_s-reduction. Secondly, the XO entails an overhead time to enter the steady state after switching to A_XO-1. After this, the XO still takes ~380 μs to enter the steady state. Here, the nonideality of the ULV A_XO-3 limits the improvement on t_s. In fact, for the amplifiers with standard I/O voltage and higher output swing, the reduction of t_s should be more profound and better matched with the R_N-boosting ratio.

Fig. 11

Estimated R_N from the exponential growth of X_OUT’s amplitude (before the transistors enter the triode/cutoff region)

Fig. 12

Total t_s versus t_sw, the enabling time of A_XO-3 (without SSCI)

With both A_XO-3 and SSCI enabled, we further decrease t_S to 400 μs (3.3× reduction) and the corresponding E_S is 14.2 nJ (2.8× reduction) (Fig. 10b). When switching from A_XO-3 to A_XO-1 that have different output impedances and, subsequently, operating frequencies, there is an instantaneous change in the output swing, since the magnitude of current passing through the crystal does not change abruptly. The percentage of energy consumed in the startup phase by the SSCI, A_XO-3, and A_XO-1 is: 7%, 39%, and 53%, respectively. We verified that t_sw can tolerate ±50% uncertainty for <10%t_S variation, implying that we can obtain an adequate t_s even with nonoptimal t_sw (e.g., variation on PVT and crystal’s parameters). This also justifies that the existing RO will be good enough to control t_sw, avoiding any external detection and control mechanism.

For the transient frequency of the XO, it takes ~300 μs to settle for a ±20 ppm f₀ accuracy (i.e., 50 kHz drifting from the center frequency of 2.44 GHz in a packet, as defined in [33]). This result is 3.5× faster than the case without startup aid (Fig. 13). The steady-state power is 31.8 μW at 0.35 V, and the PN is −134 dBc/Hz at 1 kHz offset, being adequate for most IoT applications and comparable to other state-of-the-art XOs with a standard voltage (e.g., PN of −136 dBc/Hz at 1 kHz and f₀ = 26 MHz in [10]).

Fig. 13

Transient f₀ profiles of the XO (V_DD = 0.35 V, T = 20 °C)

The XO can uphold a steady-state output swing >80% of V_DD for V_DD = 0.3–0.5 V. The t_s varies <25% from its mean (400 μs) for V_DD = 0.3–0.5 V (Fig. 14a). Only the RO of the SSCI fails to start if V_DD drops down to 0.25 V, but A_XO-3 is still in place to aid t_S reduction. Over −40–90 °C, t_S variation is <7.5% (Fig. 14b). We obtained similar results for a 16 MHz crystal (i.e., Δf₀/f₀ = 13.4 ppm over 0.3–0.5 V, Δf₀/f₀ = 21.9 ppm over −40–90 °C, and t_S variation, 9.8%).

Fig. 14

Measured XO (f₀ = 24 MHz) performances. (a) Startup time against V_DD. (b) Startup time against temperature

Table 2 benchmarks the performance of the XO with the prior art. In terms of E_s, this work is >2.6× better than [20] and slightly higher than [21]. Furthermore, we can consider this circuit in the vanguard, since it proves the feasibility of regulation-free operation under a wide range of sub-0.5 V V_DD, while conforming to the frequency-stability specification of the BLE (Bluetooth Low Energy) standard.

Table 2 Performance summary and comparison with recent art

3 A 0.35 V 5200 μm² 2.1 MHz Temperature-Resilient Relaxation Oscillator with 667 fJ/cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator

3.1 Motivation

For the crystal-less IoT node [34] and wakeup receiver [35], low-power and fully integrated kHz-to-MHz clock sources with moderate frequency inaccuracy are pivotal to their operations. For instance, [35] requires a frequency reference with ~2.5% frequency accuracy to calibrate the digitally controlled oscillator of the wakeup receiver. Although the crystal oscillator offers better frequency stability, a typical MHz-range crystal oscillator can consume tens of μW, which is impermissible for the always-on module of an IoT node. In fact, we expect a μW-range power budget in the standby mode [23]. Also, the presence of an off-chip crystal can restrict the volume miniaturization of the IoT nodes.

The ring oscillator is a viable solution among the fully integrated oscillators due to its outstanding power efficiency, tuning range, and compactness [36]. Yet, the oscillating frequency of the ring oscillator is prone to PVT variations that require extra circuitry for compensation. For the LC oscillator, it has a proper balance between the integration level and frequency stability [37, 38]. Yet, the LC tank is too bulky for MHz-range applications.

Recent relaxation oscillators (RxOs) [39,40,41,42,43,44,45,46,47] proved their potential by attaining fast settling time, moderate intrinsic frequency stability, tiny footprint, and high energy efficiency. A typical RxO consists of a period-defining network, amplifiers, and logic gates. The period-defining network periodically (dis)charges the capacitors therein, and the amplifiers compare the voltages on the capacitors with a reference voltage. The logic gates read the output from the amplifiers and generate the required output correspondingly.

For IoT nodes powered by sub-0.5 V energy-harvesting sources such as the thermoelectric generator and solar cell, ULV operation adds to the RxO design constraints. Existing RxO architectures [39,40,41,42,43,44] do not favor sub-0.5 V operation, which severely confines the voltage headroom. Hence the linearity and accuracy of the current and voltage references are inferior, and their degraded precisions can affect the RxO’s stability. Also, at high temperature, the transistor’s leakage current (I_Leak) limits the performance of the current/voltage reference.

Recently, a swing-boosted differential RxO proposed in [45] featured a symmetric swing-boosted RC network to define the period of the RxO, enabling no current or voltage reference while delivering a swing-boosted output to improve the noise performance. As this architecture does not entail current or voltage reference, it allows scaling down of the V_DD without affecting the RC network precision. Nevertheless, it has the common-mode voltage (V_CM) of the RC network restricted to mid V_DD, which implies V_CM < 0.25 V for sub-0.5 V operation, thereby hindering the operation of its subsequent comparator.

This section proposes a RxO that surmounts the challenges of sub-0.5 V operation and achieves high area and energy efficiencies. The key techniques are (1) an asymmetric RC network to free the V_CM restriction while preserving a swing-boosted output and (2) a dual-path comparator with delay compensation to allow temperature resilience. Prototyped in 28 nm CMOS, the RxO occupied a tiny area (5200 μm²) and attained superior energy efficiency (667 fJ/cycle) and figure of merit (FoM₁ = 181 dB) with respect to the prior art.

3.2 Asymmetric Swing-Boosted RC Network

Figure 15a depicts the schematic of the swing-boosted RC network. As demonstrated in [45], the RxO utilizing this RC network exhibits low jitter (σ_jit) attributed to its swing-boosted output voltages (V_x,y) from the symmetric RC network (k = 1).

Fig. 15

(a) Simplified schematic of the swing-boosted differential RxO. (b) Timing diagram of the output of the RC network with k = 1, with V_CM fixed to 0.5 V_DD. (c) Timing diagram of the output of the RC network with k > 1 such that V_CM,U and V_CM,D suit the design of the subsequent ULV comparator (this work)

Considering Ø₁ (Fig. 15b), V_x is initially at the ground and V_top connects to V_DD, whereas V_y is initially at V_DD and V_bot connects to the ground. V_x charges to V_DD and V_y charges to the ground with time constant (τ) RC. When they cross at V_CM such that V_y < V_x, the comparator inverts its outputs. Consequently, the chopper alternates the connections, where V_top now connects to the ground and V_bot connects to V_DD. As the charges across the capacitors conserve, V_x and V_Y change to V_CM + V_DD and V_CM − V_DD after the transition. The process in Ø₂ is complementary, and the operation repeats Ø₁ after another transition. Hence, the differential signal V_x,y has a swing of 2 × V_DD. Since the σ_jit of the RxO is inversely proportional to the slope of V_x,y at the threshold (S_xy), raising the swing of V_x,y increases S_xy and improves the σ_jit.

The RC network symmetry restricts V_CM to mid V_DD regardless of the oscillation phases (Ø₁,₂). As V_DD decreases to <0.5 V, the V_CM shrinks to <0.25 V, which is insufficient to properly bias a differential pair with a tail current source. To break this limit, we propose an asymmetric RC network (k > 1), in which one RC branch has a larger τ. From Fig. 15c, this act facilitates V_x,y to (dis)charge at different τ. The leaps on V_x and V_y after the chopping are still ±V_DD, whereas the V_CM of V_x and V_y alternate between V_CM,U and V_CM,D in Ø₁ and Ø₂, respectively. As such, we can design k that allows proper V_CM,U (V_CM,D) and thereby favors the operation of the subsequent ULV comparator.

Analyzing the waveform in Fig. 15c, we can derive four equations governing the (dis-)charge of the asymmetric RC network:

$$ \left({V}_{\textrm{CM},\textrm{D}}+{V}_{\textrm{DD}}\right){e}^{-\frac{T_1}{k\textrm{RC}}}={V}_{\textrm{CM},\textrm{U}}, $$

(8)

$$ \left({V}_{\textrm{CM},\textrm{D}}-2{V}_{\textrm{DD}}\right){e}^{-\frac{T_1}{\textrm{RC}}}+{V}_{\textrm{DD}}={V}_{\textrm{CM},\textrm{U}}, $$

(9)

$$ \left({V}_{\textrm{CM},\textrm{U}}+{V}_{\textrm{DD}}\right){e}^{-\frac{T_2}{\textrm{RC}}}={V}_{\textrm{CM},\textrm{D}}, $$

(10)

$$ \left({V}_{\textrm{CM},\textrm{U}}-2{V}_{\textrm{DD}}\right){e}^{-\frac{T_2}{\textrm{kRC}}}+{V}_{\textrm{DD}}={V}_{\textrm{CM},\textrm{D}}. $$

(11)

Assuming that T₁ = T₂, solving Eqs. (8)–(11) leads to

$$ {\left(\frac{V_{\textrm{DD}}-{V}_{\textrm{CM},\textrm{D}}}{{\textrm{V}}_{\textrm{DD}}+{\textrm{V}}_{\textrm{CM},\textrm{D}}}\right)}^k=\frac{V_{\textrm{CM},\textrm{D}}}{2{V}_{\textrm{DD}}-{V}_{\textrm{CM},\textrm{D}}}, $$

(12)

$$ {\left(\frac{V_{\textrm{CM},\textrm{U}}}{2{V}_{\textrm{DD}}-{V}_{\textrm{CM},\textrm{U}}}\right)}^k=\frac{V_{\textrm{DD}}-{V}_{\textrm{CM},\textrm{U}}}{V_{\textrm{DD}}+{V}_{\textrm{CM},\textrm{U}}}, $$

(13)

$$ k=\frac{T}{2\textrm{RC}}/\ln \left(\frac{1+3{e}^{-T/2\textrm{RC}}}{1-{e}^{-T/2\textrm{RC}}}\right), $$

(14)

where T₁ = T₂ = T/2. Therefore, we can calculate the required k to achieve a sufficient separation of V_CM,U (V_CM,D) by numerically solving Eqs. (12) and (13), as well as the corresponding T by Eq. (14). Figure 16a illustrates the V_CM,U, V_CM,D, and T versus k.

Fig. 16

(a) The simulated V_CM,U, V_CM,D, and the oscillating frequency versus k. Choosing a k > 1 enables a lower (higher) V_CM,D (V_CM,U), facilitating the ULV operation. (CLK) The S_XY from mathematical modeling and simulated 1/σ_jit from an ideal RxO with asymmetric RC network versus k. Overdesigning k decreases the S_XY and thus aggravates σ_jit

The S_xy around the threshold crossing determines the σ_jit with the following equation [48]:

$$ {\sigma}_{jit}=\alpha \frac{V_{n, xy}}{S_{xy}}, $$

(15)

where 𝛼 is a constant of proportionality and V_n,xy is the equivalent noise from the RC network and the subsequent comparator appearing at its output. We can determine S_xy by solving for the difference between the derivative of V_X and V_Y when t = T/2 (the time when crossing occurs),

$$ {S}_{\textrm{x}\textrm{y}}=\frac{d{V}_{\textrm{x},\textrm{y}}}{dt}\left(t=\frac{T}{2}\right). $$

(16)

For instance, in Ø₂, V_X and V_Y become

$$ {V}_X(t)=\left({V}_{\textrm{CM},\textrm{U}}+{V}_{\textrm{DD}}\right){e}^{-\frac{t}{\textrm{RC}}}, $$

(17)

$$ {V}_Y(t)=\left({V}_{\textrm{CM},\textrm{U}}-2{V}_{\textrm{DD}}\right){e}^{-\frac{t}{k\textrm{RC}}}+{V}_{\textrm{DD}}, $$

(18)

where we set t = 0 as the beginning of Ø₂. Taking the derivative of V_X with respect to t and substituting t = T/2, we can get

$$ \frac{d{V}_X}{dt}\left(t=\frac{T}{2}\right)=-\frac{1}{\textrm{RC}}\left({V}_{\textrm{CM},\textrm{U}}+{V}_{\textrm{DD}}\right){e}^{-\frac{T}{2\textrm{RC}}}, $$

(19)

and substituting Eq. (10) into Eq. (19):

$$ \frac{d{V}_X}{dt}\left(t=\frac{T}{2}\right)=-\frac{1}{\textrm{RC}}{V}_{\textrm{CM},\textrm{D}}. $$

(20)

Similarly, we can obtain the slope of V_Y at t = T/2:

$$ \frac{d{V}_Y}{dt}\left(t=\frac{T}{2}\right)=-\frac{1}{k\textrm{RC}}\left({V}_{\textrm{CM},\textrm{D}}-{V}_{\textrm{DD}}\right). $$

(21)

Then, S_xy in Ø₂ is

$$ {S}_{xy}=-\frac{1}{\textrm{RC}}\left({V}_{\textrm{CM},\textrm{D}}-\frac{V_{\textrm{CM},\textrm{D}}}{k}+\frac{V_{\textrm{DD}}}{k}\right), $$

(22)

where we can find the relationship between V_CM,D and k from Eq. (12). Note in (3.22) that when k = 1 (symmetric RC network as in [45]), S_xy = −V_DD/RC, showing that a higher V_DD improves S_xy and thus σ_jit. Figure 16b shows the S_xy as a function of k. Under the identical RC and V_DD, increasing k results in decreasing S_xy. We can calculate S_xy similarly in Ø₁; provided that T₁ = T₂, S_xy in Ø₁ should be equivalent (in negative) to S_xy in Ø₂.

Based on Fig. 16a, b, we can have the following takeaway: a large k allows V_CM,U (V_CM,D) to approach V_DD (ground), easing the use of an NMOS (N-metal-oxide semiconductor) (PMOS [p-channel metal-oxide semiconductor])-input amplifier for comparisons. Yet, upsizing k penalizes σ_jit since σ_jit ∝ 1/S_xy. Besides, pushing V_CM,U (V_CM,D) close to V_DD (ground) saturates the input pairs of the subsequent amplifiers. Then, there is a trade-off between the minimum V_DD and σ_jit for the RxO utilizing the asymmetric RC network. The minimum gate voltage at the NMOS-input amplifier is ~0.2 V (i.e., 0.1 V for the tail current source +0.1 V for the gate-source voltages of the differential pair), and the minimum V_DD of the comparator is ~0.35 V (explained in Sect. 3.3). To yield a minimum V_CM,U of 0.2 V to drive the NMOS-input amplifier with 15% margin, we choose k = 2.4 such that V_CM,U is 0.23 V (0.66 × V_DD). During the fabrication, the mismatch between the resistors diverts V_CM,U (V_CM,D) from their desired values. Nevertheless, since k is the ratio between the resistors, we can minimize its variation through a delicate layout and a common centroid technique. This means that a 15% margin is adequate to safeguard the operation of the RxO. Correspondingly, we positioned V_CM,D at 0.33 × V_DD to favor the PMOS-input amplifier.

With k = 2.4 in Fig. 16b, S_xy reduces by 39%. To verify the degradation of σ_jit, we built an ideal RxO utilizing the asymmetric RC network with a noise source and simulated the σ_jit with different values of k. We juxtapose the simulated 1/σ_jit of such RxO in Fig. 16b. The 1/σ_jit decreases (hence σ_jit increases) at a similar rate of k with S_xy. The 1/σ_jit at k = 2.4 decreases by 36%, thus verifying our analysis.

3.3 Circuit Implementation

3.3.1 ULV Comparator with Dual-Path Amplifiers

In [45], the RxO utilizes an inverter-based amplifier for voltage comparison. Although this amplifier has excellent noise performance, it is not suitable for ULV operation as it requires a minimum voltage headroom of 2(V_GS + V_DS). We proposed the asymmetric RC network in Sect. 3.2 for ULV operations, where we can adjust the V_CM,U (V_CM,D) according to k. To cope with different V_CM at two phases of oscillations under a ULV headroom, we utilize a comparator with dual-path amplifiers to handle the voltage comparisons across V_x,y. The comparator consists of an NMOS-input, a PMOS-input amplifier, and logic gates to generate the CLK signal. The NMOS-input amplifier, enabled in Ø₁, is capable of handling a higher input V_CM, where V_X and V_Y cross at V_CM,U, with the PMOS-input amplifier disabled. The complementary operation happens in Ø₂. As such, both amplifiers can perform comparisons under the ULV headroom. When compared with the case using k = 1 and only a PMOS-input amplifier, the variation of the RxO’s oscillating period (T_OSC) reduces by ~40%.

Figure 17a, b presents the proposed ULV RxO, with each amplifier built by cascading three gain stages, each formed by a fully differential common-source (CS) amplifier (Fig. 18a), to boost the overall voltage gain. The simulated gains of the cascaded amplifiers are >27 dB. Following the amplifiers, the logic gates generate the CLK signals and operate the chopper of the RC network after boosting to CLK_H (explained below).

Fig. 17

(a) Proposed ULV swing-boosted RxO featuring an asymmetric RC network and a dual-path comparator. We track the delays of the amplifiers to tackle the frequency fluctuation against temperature and voltage variations. (b) Schematic of the logic gates. The SR latch, together with the delay unit, guarantees that the RxO only generates desired oscillating signal without glitch

Fig. 18

(a) Schematic of the differential CS amplifier (NMOS). (b) CMFB circuit for the NMOS CS amplifier

Since we can adjust the V_CM,U (V_CM,D) of the RC network between V_DD and ground by choosing an appropriate k, the main limitation for the minimum V_DD of the RxO derives from two factors: the dual-path amplifier and the logic gates. Assuming all transistors biased in the subthreshold region with the gate voltages bounded between V_DD and ground, the minimum V_DD of the differential CS amplifier is V_SD,1 + V_DS,3 + V_DS,5 (in Fig. 18a) if we assume the V_DS-drop on M₆, the transistor for power-gating, is negligible. To maintain operation in the subthreshold region, the |V_DS| of a transistor should be >3 × V_T, where V_T is the thermal voltage. The V_T reaches 34 mV at 120 °C. Hence, the minimum V_DD of the differential CS amplifier is 306 mV in theory. We allow ~10% margin for the design and choose a V_DD of 0.35 V. On the other hand, the necessary V_DD for the logic gates to operate under the desired oscillating frequency also limits the minimum V_DD. In the selected CMOS 28 nm process, the delay of the logic gates with V_DD of 0.35 V varies <1% of T_OSC from −20 to 120 °C, evincing that a V_DD of 0.35 V is sufficient to power the logic gates.

The comparator’s delay (t_delay) affects the T_OSC stability. As described later, a delay generator compensates for t_delay under different operating conditions. Here, we target a maximum Δt_delay ~ 25% of T_OSC across −20 to 120 °C such that the resultant T_osc variation after compensation is <2.5%, reserving a 10% mismatch margin between t_delay and the delay generator. The simulated t_delay (N + P channel) ranges from 17 ns at 120 °C to 146 ns at −20 °C under a power consumption of 500 nW (at 27 °C), with a variation ~10% above the target.

The gate voltages of M₃ and M₄ determine the operating region of M₅ (Fig. 18a). To guarantee M₅ operates in the subthreshold region, V_DS,5 needs to be higher than 3 × V_T. We can either increase V_in,P (V_in,N), which is the RC network output for the first amplifier, by upsizing k or decreasing the V_GS of M₃ and M₄. As explained in Sect. 3.2, upsizing k deteriorates the σ_jit. On the other hand, under the same bias current and channel length, decreasing V_GS incurs a wider M₃(M₄), thus exacerbating the t_delay and the RxO’s frequency stability. From the simulation, the amplifier’s delay raises by 26% with the V_GS of M₃(M₄) reduced by 10 mV (with the width of M₃(M₄) enlarged). We aim for a V_GS of 0.1 V for M₃(M₄) to achieve a proper trade-off between the t_delay and σ_jit.

Since each amplifier is only responsible for comparing V_x and V_y in one phase, we can have them power-gated based on the CLK state to reduce the power consumption. For instance, in Ø₁ where CLK is high and the common-mode voltage of V_x and V_y is at V_CM,U, we enable the NMOS-input amplifier for comparison, while powering down the PMOS-input amplifier. The operation reverses in Ø₂. This duty-cycling scheme saves 26% of the total RxO power budget.

To ensure that M₁ and M₂ operate in the subthreshold region, a common-mode feedback (CMFB) circuit generates their gate voltages (Fig. 18b). The CMFB circuit compares the common-mode output voltage of the amplifier to V_ref and corrects V_FB. We scaled the transistors’ sizes of the CMFB circuit from the main amplifier such that the PVT variations have the same effect on the amplifier and CMFB circuit to enhance its robustness.

We utilized a SR latch to read the results from the amplifiers and yield the desired state of CLK. Also, we used a delayed CLK ($\overline{\textrm{CLK}}\Big)$ signal CLK_D ($\overline{\textrm{CL}{\textrm{K}}_{\textrm{D}}}\Big)$ to mask out the glitches and avert the undesired transition of CLK due to glitches from the amplifiers during the switching. For instance, as illustrated in Fig. 17b, before the end of Ø₁ (CLK and CLK_D are high), both S and R of the SR latch are high and maintain the state of CLK. Therein, with the NMOS-input amplifier enabled, we disable the PMOS-input amplifier. Once V_X > V_Y, R becomes low and S is still at high (since $\overline{\textrm{CL}{\textrm{K}}_{\textrm{D}}}$ is low), which forces CLK to low. Then, the circuit enables the PMOS-input amplifier, while disabling the NMOS-input amplifier. During the switching of the amplifiers, we may have an undesired transition on V_out,N/V_out,P. The CLK_D signal and the NAND gates guarantee that these undesired glitches do not affect the state of CLK. After a delay of τ_d, CLK_D goes low. Both S and R are high again, and the SR latch maintains the state of CLK until V_out,P goes high (V_X < V_Y). The operation repeats itself after another transition of CLK. A simple RC circuit and inverters with τ_d of ~80 ns implement the delay unit. We selected τ_d to allow sufficient margin before the zero-crossing point of V_XY without affecting the comparison, yet it would be long enough to filter out the glitches from the amplifiers during the switching amid PVT variation.

A constant-g_m bias circuit aids the amplifiers in withstanding voltage and temperature variations [49]. A switched-capacitor voltage doubler (Fig. 19a) powers the bias circuit, which extends the voltage headroom (2 × V_DD ≈ 0.7 V). As we can reuse the CLK signal from the RxO itself to operate the voltage doubler, the power (11%) overhead is low. During the start-up, there is no CLK signal yet to drive the voltage doubler, and hence there would be no output from the bias circuit without any auxiliary signal. Thus, a start-up pulse (duration ~1 μs, generated on-chip after V_DD rises) enables an auxiliary ring oscillator (RO) to operate the voltage doubler in this start-up phase (Fig. 19b, c). With the V_2X boosted up to ~2 × V_DD, the bias circuit functions properly within this period. Then, we disable the start-up pulse and the auxiliary RO, with the RxO starting to operate. Like this, the RO does not pose interference to the RxO nor affect the accuracy of the RxO’s frequency. The RO’s frequency ranges from 15.2 to 35.1 MHz across −20–120 °C.

Fig. 19

(a) Schematic of the switched capacitor voltage doubler. (b) The auxiliary RO that drives the voltage doubler during the startup. (c) Timing diagram of the auxiliary RO and the voltage doubler

3.3.2 Delay Generators

The temperature dependency of t_delay affects RxO’s T_OSC. Ideally, T_OSC is only dependent on the RC network. However, the t_delay after the zero-crossings of V_x,y prolongs the duration of each phase. As t_delay is temperature-dependent, it deteriorates the RxO’s frequency stability. Raising the amplifiers’ power budget can diminish the ratio t_delay/T_OSC, but it penalizes the RxO energy efficiency. In [42], a period controller compensates t_delay by doubling the current injected into the period-defining capacitors, in which the current injection duration tracks t_delay. As such, it can correct T_OSC to minimize its temperature sensitivity. Yet, the period controller entails an extra comparator for copying t_delay, penalizing the power budget.

Since the delay of an amplifier relates to its bias current, we introduce a delay generator to create a pulse, with its width inversely proportional to the bias current. As demonstrated in Fig. 20a, two delay generators (for NMOS- and PMOS-input amplifiers) with scaled currents from the main amplifiers generate the pulses after the edges of CLK_H. From the simulation, the width of the pulses Ø_F closely tracks t_delay (error <7.6% of t_delay or <2.3% of T_OSC). To compensate t_delay, we halve the τ of the RC branches when Ø_FH = 1 by closing switches S₁ and S₂ in Fig. 17a. The open-loop compensation scheme alleviates the long settling time of the oscillator. Furthermore, this compensation method can even off the temperature dependency of the resistors in the RC network, avoiding area-hungry composite resistors to obtain a zero temperature coefficient (TC) [42, 46].

Fig. 20

(a) Proposed delay generator to track the t_delay at different operating conditions and its timing diagram. (b) Matching between t_delay and t_DN + t_DP against temperature variation (under nominal case). (c) Principle of the delay compensation: when Ø_FH is high, τ of the RC branches halved thus V_x,y (dis)charge at a double rate to compensate t_delay. (d, e) The Monte Carlo-simulated t_DP and t_DN (100 runs) at 27 °C with different input codes for the capacitor banks

We implemented the delay-controlling capacitors C_N and C_P as four-bit capacitor banks, with their values programmed to balance the process variation once after fabrication. The design of the tuning ranges of the capacitances can cover the variations of t_delay amid process variations. The t_delay of NMOS-input and PMOS-input amplifiers vary from 15 to 45 ns and 36 to 60 ns, respectively, from the Monte Carlo simulation (100 runs, at 27 °C). Consequently, we design the delay generator and the capacitor banks capable of generating pulses of width in this range by adjusting their codes correspondingly (Fig. 20d, e). With the proposed compensation scheme, the simulated variation of T_OSC decreases from 25% to 2.1% over −20–120 °C. For the constant-g_m biasing, the current decreases with temperature. Hence, both I_BN and I_BP, the biasing currents of the NMOS-input and PMOS-input amplifiers, are minimum at −20 °C. Consequently, the t_DN and t_DP are largest at −20 °C and decrease to their minimum toward 120 °C. Therefore, we have the overall resolutions of t_DN and t_DP confined at low temperature (7 ns and 13 ns). Still, these resolutions are sufficient to uphold the 2.5% frequency error requirement. In case a finer resolution is necessary, the number of bits of the capacitor banks can increase.

3.3.3 CLK Boosters

The non-idealities of the switches influence the performance of the RxO. For example, the nonzero on-resistances (R_ON) of the transistors that constitute switches S_1–6 (in Fig. 17a) affect the τ of the RC network. Under sub-0.5 V, the transistors work in the subthreshold region. Then, the situation emerges as R_ON increases exponentially with –(V_GS − V_TH), where the worst case of |V_GS| is 0.5 × V_DD without any boosting technique. Further, as R_ON is prone to temperature variations (R_ON increases with a decreasing temperature), it inevitably affects the frequency stability of the RxO. To alleviate the impact, we should minimize R_ON in comparison with R in the RC network. One possibility is reducing R_ON by upscaling the widths of the transistors that compose the switches. Yet, this act leads to another problem: in the deep submicron CMOS process, the I_Leak in the off-state, especially at high temperature, restricts the RxO’s performance and operation range. Considering the switches S_1–2 in Fig. 17a again, at high temperature, the transistors with high I_Leak equivalently reduce τ. Altogether, there is a trade-off between their R_ON at low temperature and I_Leak at high temperature.

To tackle this challenge, we employ clock boosters [50] to triple the swing of the digital signals (CLK_H, $\overline{{\textrm{CLK}}_{\textrm{H}}}$, and Ø_FH). The clock booster, powered from V_DD, increases the swing of the periodic signal (high, 2 × V_DD; low, –V_DD) without additional power supply. With a boosted swing, the worst |V_GS| for the transistors now becomes 1.5 × V_DD. Besides, benefitting from the negative voltage (–V_DD) at the logic low level, it effectively suppresses I_Leak, even at 120 °C. For example, this scheme not only tightens the variations of the R_ON of an NMOS switch across −20–120 °C by 8600× (V_D = V_S = 0.5 × V_DD, Fig. 21a) but also shrinks I_Leak in the off-state at 120 °C from 307 to 0.8 nA (Fig. 21b), rendering the RxO robust in an extreme environment.

Fig. 21

(a) R_ON of an NMOS from −20 to 120 °C with different V_G. For both cases, V_D = V_S = 0.175 V. The increased swing on V_G reduces the variations of R_ON by 8600×. (b) I_Leak of the same NMOS in (a) in the off-state. With a negative V_G, the I_Leak reduces by 389× at 120 °C. For both cases, V_D = 0.35 V and V_S = 0 V

3.4 Measurement Results

We fabricated a prototype of the RxO in 28 nm CMOS 1P10M technology. It occupied a core area of 5200 μm², dominated by the comparator (28%) and RC network (26%) (Fig. 22a, b). The RxO consumed 1.4 μW at 22 °C on average (N = 7) (Fig. 23a, b)), where the comparator (49%, from simulation) dominates (Fig. 22c). After the fabrication, we apply three-point trim to the capacitor banks of the delay generator based on the measured frequency of the RxO.

Fig. 22

(a) Chip micrograph of the fabricated RxO in 28 nm CMOS. (b) Area breakdown of the RxO. (c) Power breakdown of the RxO (from simulation)

Fig. 23

Measured performance of the RxO from seven chip samples. (a) Power consumption versus temperature. (b) Power consumption versus V_DD. (c) Frequency stability versus temperature. (d) Frequency stability versus V_DD

Peripheral equipment such as the oscilloscope (for observing the waveform in real-time) and the frequency counter (for measuring the frequency f) have high input capacitances. The digital buffers with a V_DD of 0.35 V and reasonable sizing are not capable of driving these equipment. Thus, we utilize on-chip-level shifters to raise the output signals for swings of 0.9 V. Afterward, we feed such signals to digital buffers with a V_DD of 0.9 V (supplied independent of the RxO’s V_DD) to drive the peripheral equipment.

The mean oscillating frequency of the RxO is 2.1 MHz. It has an energy efficiency of 667 fJ/cycle, rendering it the most energy-efficient RxO reported in the MHz-range. After calibrations, the deviations of the RxOs’ frequencies are <2.5% from −20 to 120 °C (Fig. 23c). The resulting TC is 158 ppm/°C on average. The mean variation of the RxO’s frequencies from 0.35 to 0.38 V (~9% of V_DD) is 2.5% (Fig. 23d). The line sensitivity, where we also take the supply voltage into account $\left[\left(\frac{\Delta f}{f}\right)/\left(\frac{\Delta V}{V}\right)\right]$, is 26.8%. The large sensitivity of the RxO to voltage variation is attributable to the subthreshold operation and low V_DS across the transistors of the amplifiers. From the simulation, the bias current of the NMOS-input amplifier increases by 25% from 0.35 to 0.38 V, hence affecting the t_delay and the RxO’s frequency. Still, the 0.35–0.38 V range is sufficient for IoT devices powered by solar cells and installed in the typical indoor environment (e.g., home and office), as the open-circuit voltage of a solar cell varies 30 mV amid a change in light intensity of ~3× [51, 52]. If we relax the requirement on frequency stability or recalibration of the frequency at different V_DD is feasible, the working range of the RxO can extend to 0.5 V and then limited by the breakdown voltage of the CMOS process (1 V) due to the voltage doubler and clock booster.

The RMS period jitter of the RxO is 800 ps (0.15% of T_OSC) (Fig. 24a). The accumulated jitter increases at a rate of √N up to ~60 cycles, in which the thermal noise is the dominant noise source (Fig. 24b). When compared with [45], the high period jitter is attributable to the low supply voltage, low power, and different amplifiers handling the comparison in Ø₁ and Ø₂. Still, the RxO is appropriate for the devices in which ULV and ultra-low power are the priorities (e.g., wakeup receiver [35]). The long-term stability is 210 ppm (gating time >0.1 s). To characterize the supply noise rejection of the RxO, we superimpose a sinusoidal signal on V_DD and measure the corresponding period jitter. In the presence of a 20 mV_pp sinusoidal signal (1 kHz) at the supply, the period jitter of the RxO exhibits a value of 2 ns.

Fig. 24

(a) Measured period jitter of the RxO (52,000 hits on the oscilloscope). (b) Accumulated jitter of the RxO

We also characterize the startup time of the RxO, which is crucial if the RxO is power gating to further suppress the power consumption of the IoT node. As the asymmetric RC network requires finite clock cycles to produce a consistent output signal, the RxO’s frequency settles after the third clock pulse (Fig. 25a, b). Over the entire temperature range, the RxO enters the steady state within 3.6 μs after enabling V_DD (Fig. 25c).

Fig. 25

(a) Startup waveform of the RxO, with V_DD switched on at t = 0 s. (b) Transient frequency during startup. The RxO reaches steady state within three clock cycles or 3.6 μs after enabling V_DD. (c) The startup time of the RxO at different temperatures

Herein we benchmark the RxO using two FoM. First, we evaluated the RxO using the FoM proposed in [44]

$$ \textrm{Fo}{\textrm{M}}_1=10\log \left(\frac{f\bullet {T}_{\textrm{range}}}{\textrm{Power}\bullet \textrm{TC}}\right), $$

(23)

with the temperature range T_range. This FoM takes into account the trade-off among f, power, T_range, and TC. The FoM₁ of the RxO is 181 dB, which is comparable to the state of the art in spite of the ULV V_DD of 0.35 V. Then, we evaluated the RxO using the conventional FoM:

$$ \textrm{Fo}{\textrm{M}}_2=\textrm{PN}-20\log \left(\frac{f}{f_{\textrm{offset}}}\right)+10\log \left(\frac{\textrm{Power}}{1\ \textrm{mW}}\right), $$

(24)

where PN is the phase noise at the offset frequency from the carrier f_offset. The PN of the RxO at 10 kHz offset is −68.4 dBc/Hz, resulting in an FoM₂ of −143.4 dBc/Hz.

Table 3 summarizes the performance of the RxO and compares it with recent art. This work is the first sub-0.5 V temperature-resilient (<2.5%) RxO achieving a high power efficiency of 667 fJ/cycle (Fig. 26). When compared with the RxO with a symmetric swing-boosted RC network [45], this RxO operates at a 4× less V_DD, while achieving a comparable TC after compensation.

Table 3 Performance summary and comparison with the state-of-the-art RXOs

Fig. 26

Comparison with state-of-the-art fully integrated oscillators. Red circle, relaxation oscillator; blue circle, frequency-locked-loop type oscillator. A larger circle implies a relatively higher oscillating frequency. The figure only shows selected oscillators with frequencies between 0.1 and 10 MHz

4 Conclusions

This chapter detailed the analysis and design of two ULV MHz-range clock references for different purposes, with both clock references implemented and taped out in deep-submicron CMOS, exhibiting well-founded and pioneering measurement results. The first is a regulation-free sub-0.5 V XO for energy-harvesting BLE radios. We introduced two circuit techniques, dual-mode g_m and SSCI, to reduce the startup time t_s and energy E_s. The dual-mode g_m exploits the inductive feature of three-stage g_m (A_XO-3) to counteract the crystal’s C_S during the startup and the low-noise feature of one-stage g_m (A_XO-1) to preserve the PN in the steady state. The XO prototyped in 65 nm CMOS has a compact area (0.023 mm²) that is >3.1× smaller than the prior art. The measured t_s and E_s of the XO, with a 24 MHz crystal, are 400 μs and 14.2 nJ, respectively. The frequency stability against voltage (0.3–0.5 V) is 17.9 ppm and temperature (−40–90 °C) is 14.1 ppm; both conform to the BLE standard.

The second clock reference is a 2.1 MHz temperature-resilient RxO with a 0.35 V supply voltage for ultra-low-power IoT nodes. We jointly design an asymmetric swing-boosted RC network and a dual-path comparator to tackle the challenges of ULV (<0.5 V) operation. The open-loop delay generator compensates for the temperature-sensitive delay of the comparator. Fabricated in 28 nm CMOS, it has an active area of only 5200 μm² and achieves the best energy efficiency of 667 fJ/cycle among the previously reported MHz-range RxOs. Further, it also has a high figure of merit of 181 dB in spite of the ULV headroom and can settle within 3.6 μs after enabling the supply voltage.