Keywords

1 Introduction

In the last few decades, microelectronics has become the most essential driving factor behind all technological advancements [1, 2]. In microelectronic systems such as the central processing unit (CPU), metal oxide semiconductor field effect transistor (MOSFET), dynamic random-access memory (DRAM) and flash memory, the dielectric layer is a key component [3, 4]. Although the dielectric material's primary role is to improve capacitive coupling between nearby metals and semiconductors, it also inhibits leakage current between electrodes, which reduces energy consumption (in CPUs and DRAMs) and long-term dependability (in flash memory) [5]. Other than microelectronic systems, dielectric material is also used in Micro-electromechanical Systems (MEMS) specifically in RF MEMS switches for satellite reconfigurable antennas to achieve lower insertion loss and lower power consumption than semiconductor switches [6,7,8].

In microelectronics, silicon dioxide (SiO2) has been utilised as an ideal dielectric material for decades because of its ease of growth, low-charge density and better interface with silicon. During downscaling of SiO2 layer, the leakage current caused by the quantum tunnelling phenomenon become prominent [9], causing major difficulties with power consumption and device performance. To overcome the scaling restriction of microelectronic device, conventional dielectric layers are replaced with advanced high permittivity (high-k) materials [10,11,12]. Various high k materials, such as barium strontium titanate (BST, BaSrTiO3), tantalum oxide (Ta2O5), titanium oxide (TiO2), hafnium oxide (HfO2), zirconium oxide (ZrO2), silicon nitride (Si3N4), and aluminium oxide (Al2O3), aluminium nitride (AlN) are being investigated to meet the need. Among various metal oxide, Ta2O5 is the most promising gate insulator and also appropriate candidate for use of memory dielectric in storage capacitors in place of SiO2, because of its high dielectric constant, high breakdown field, high amorphous-to-crystalline transition temperature and better chemical stability [11,12,13,14,15]. In addition, Ta2O5 has high bandgap (4.5–5 eV) to achieve a sufficient barrier height to reduce the leakage current. Because of the above properties, Ta2O5 thin film has drawn tremendous attention for high-density dynamic random-access memory (DRAMs) and metal–oxide–semiconductor field-effect transistors (MOSFETs). On the other hand, the charge density of the dielectric layer needs to be systematically investigated since the constraints imposed by the charging mechanisms in the dielectric material will impact the collapse of bridges and cantilevers of RF MEMS [16]. Charges are injected and subsequently trapped in the dielectric layer in electrostatically actuated MEMS switches, when the bridge comes into contact with the dielectric under the pull-in voltage. This charge injection creates a change in the actuation voltage, which eventually leads to a stiction effect, which severely limits the device performance [17]. The improvement of the fabrication process as well as the exploration of alternate materials for dielectric layers is necessary to overcome the limits of RF MEMS reliability. Ta2O5 is a promising option for the use of dielectric layer in RF MEMS switches because of its excellent material properties [18, 19]. The dielectric constant of Ta2O5 is significantly greater than that of the conventional dielectric material utilised in RF MEMS switches. This feature has the critical benefit of the enhancement of capacitance ratio in RF MEMS based capacitive switches using Ta2O5 as the dielectric layer by improvement in the switching performance [20]. Hence, the systematic study of the electrical behavior of Ta2O5 films is required prior to its microelectronic applications.

Several physical and chemical deposition strategies for fabrication of Ta2O5 thin films have been carried out, whereas sputtering is found to be a low-temperature, non-toxic, CMOS compatible technology that produces homogeneous smooth thin films of better quality [21, 22]. Regardless of the Ta2O5 synthesis process, the deposition parameters have a significant impact on the modulation of morphological and electrical properties of the sputtered films. Hence, the effect of sputtering pressure and substrate temperature on the structural and electrical properties of Ta2O5 thin films is investigated in this research work.

2 Experimental Details

Tantalum oxide thin dielectric films were deposited on p-type silicon [(100), 1–10 Ω cm] wafers using an RF magnetron sputtering technique using a pure tantalum target (99.95%) in the presence of high-quality oxygen and argon gas. During the sputtering process, the sputtering power and Ar/O2 gas flow ratio were fixed as 300 W and 3:2, respectively. The sputtering pressure was varied from 4 × 10–3 mbar to 1 × 10–2 mbar and the substrate temperature was varied from room temperature to 300 ℃. During the variation of the sputtering pressure, the substrates were kept at room temperature and while varying the substrate temperature the sputtering pressure was fixed at 6.0 × 10–3 mbar. After the deposition, all the films were undergone post-deposition annealing treatment. The annealing was carried out at 900 ℃ for 1 h in air ambient. The thickness of the films was kept around 50 nm. X-ray diffraction (XRD) (Rigaku ultima IV), Atomic force microscope (AFM) (Park System XE7), were used to investigate the structural, morphological properties of the thin film. To study the electrical properties of Ta2O5 films, metal oxide semiconductor (MOS) structure was fabricated using thermal evaporation of aluminum. The capacitance-voltage (C–V) measurement technique was used to calculate the interface charge density, oxide charge density, and dielectric constant, while the current–voltage (I–V) studies were used to estimate the leakage current of the films. The C-V and I–V behaviour were investigated using an Agilent E4980 precision LCR meter.

3 Results and Discussion

Figure 1 shows the XRD patterns of the Ta2O5 thin film, deposited at various sputtering pressure and substrate temperatures, on Si substrate. There was not evolution of crystalline peaks for as-deposited Ta2O5 thin films. When the films are annealed at 900 ℃, β—phase of orthorhombic structures is obtained. The position of the diffraction peaks is in agreement with the JCPDS data (Card No. 25–0922) [23]. The crystallinity of the film increases with increase in the sputtering pressure as shown in Fig. 1a. The increase in sputtering pressure produces sufficient sputtering species (Ar) and reacting species (O2). Hence, the film of better stoichiometry is produced during sputtering. Figure 1b indicates the crystallinity of Ta2O5 at various substrate temperatures. As the annealed Ta2O5 film is polycrystalline in nature with orthorhombic structure, with increase in substrate temperature the crystallinity of the film improved slightly. The increase in substrate temperature has provided sufficient energy to the adatoms to migrate to the favorable sites to preliminarily produce dense and homogeneous structure. However, the temperature and duration of deposition is not enough for the orientation of ad-atoms. Therefore, post-deposition annealing is required for structural improvement.

Fig. 1.
figure 1

XRD pattern of Ta2O5 thin films deposited at different (a) sputtering pressure and (b) substrate temperature followed by 900 ℃ annealing.

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Fig. 2.
figure 2

AFM micrographs of Ta2O5 thin films for different sputtering pressure (a) 4.0 × 10–3 mbar (b) 6.0 × 10–3 mbar (c) 8.0 × 10–3 mbar (d) 1.0 × 10–2 mbar

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Figures 2 and 3 depicts the AFM micrographs of Ta2O5 thin films for various sputtering pressure and substrate temperature respectively. Surface roughness, estimated from AFM images, is found to be increased from 4 nm to 4.8 nm with increased sputtering pressure from 4.0 × 10–3 mbar to 1.0 × 10–2 mbar, as shown in Fig. 4a. The increase in roughness of the sputtered film with pressure is due to the grain growth as a result of rise in crystallinity as seen from XRD plots. In addition, the average distance between molecule collisions rises because there are fewer gas molecules in the chamber at lower sputtering pressure and the chance of particle collision decreases and sputtered particles have enough energy to homogeneously organise themselves on the substrate. As the sputtering pressure rises, the bombardment of the target atoms by the sputtering Ar+ increases, and as a result of the huge number of target atoms ejected, the scattering of the sputtered species improves, lowering the kinetic energy of the impacting ions. As a result, at greater pressures, adatom mobility on the substrate surface is reduced and the roughness increases. On the other hand, the surface roughness decreases, when the deposition temperature rises [Fig. 4b]. At higher substrate temperature, sputtered particles have increased mobility, which gives rise to homogeneous nucleation and grain development. As a result, the atoms uniformly distributed to produce smoother surface.

Fig. 3.
figure 3

AFM micrographs of Ta2O5 thin films for different substrate temperature (a) room temperature (b) 100 ℃ (c) 200 ℃ (d) 300 ℃

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Fig. 4.
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AFM surface roughness of Ta2O5 thin films for different (a) sputtering pressure and (b) substrate temperature

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Capacitance–voltage measurements of Ta2O5 based MOS structures are carried out, with a sweep in bias voltage from −5 V to 5 V, to investigate the electrical characteristics. Figure 5 depicts the normalized high frequency (1 MHz) C–V curve of the Al/Ta2O5/Si MOS structure for various sputtering pressures and substrate temperatures. The oxide charge density (Qox), interface charge density (Dit), and dielectric constant of the Ta2O5 thin film were determined from the C–V curve. With a bias voltage sweep, the accumulation, depletion, and inversion regions are clearly observed. Here, Cox represent the oxide capacitance per unit area.

Fig. 5.
figure 5

Capacitance–voltage characteristics of the Ta2O5 thin film deposited at different (a) sputtering pressure and (b) substrate temperature

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The accumulation capacitance is used to compute the dielectric constant, which is found to be increased from 14.8 to 18.8 with the increase in sputtering pressure from 4.0 × 10–3 mbar to 8.0 × 10–3 mbar and from 17.2 to 19.1 with the rise in substrate temperature from room temperature to 300 ℃, respectively. The dielectric constant increases with the increase in the sputtering pressure because the crystallinity of the film improved with increase sputtering pressure and hence, at the accumulation region the capacitance of the film increases [24]. The shift in C–V curves, indicates a reduction in oxide charge density as the sputtering pressure rises. Figure 6 shows the Qox and Dit values for various sputtering pressures and substrate temperatures. When the sputtering pressure is increased from 4.0 × 10–3 mbar to 8.0 × 10–3 mbar, the interface trap density found to be decreased. Similarly, the oxide charge density decreases with increase in substrate temperature. This may be due to the modulation is grain size and their boundaries. Defects, voids, unsaturated bonds, and impurities are commonly found along grain boundaries, which act as trap centres. Films of smaller grains have larger grain boundary area, which means there are more trapping centres accessible for collecting free carriers. With the rise in granular dimensions, the surface area of the grain boundaries is comparatively annihilated and therefore, the defect density has decreased. The interface charge density (Dit) is found to be maximum at lower sputtering pressure, which may be due to the high-energetic atom bombardments as the mean free path of the atomic species are comparatively larger during sputtering. The films grown at moderate substrate temperature yield lower Dit.

Fig. 6.
figure 6

Oxide (Qox) and interface (Dit) charge densities of Ta2O5 thin films deposited at various (a) sputtering pressure and (b) substrate temperature

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Fig. 7.
figure 7

Current–voltage characteristics of the Ta2O5 thin films deposited at various (a) sputtering pressure and (b) substrate temperature

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Current–voltage (I–V) curves for Al/Ta2O5/Si structures for various sputtering pressures and substrate temperatures are shown in Fig. 7. A rapid rise in current occurs at lower bias voltages, and then the current becomes quasi-saturated. The lower leakage current is achieved for a sputtering pressure of 8.0 × 10–3 mbar. The decrease in leakage current with increasing sputtering pressure is related to rise in grain size, with fewer grain boundaries accessible to offer a current conducting channel [25]. Similarly with increase in substrate temperature the leakage current decreases and found to be minimal for sample prepared at 300 ℃. This may be due to the improvement of film quality by the reduction of voids, unsaturated bonds with the enhancement of crystallinity. Hence, the Ta2O5 films grown at 8.0 × 10–3 mbar and substrate temperature of 300 ℃ found suitable for microelectronic applications.

4 Conclusion

Ta2O5 thin films were deposited on p-type silicon wafer using RF sputtering technique to study its structural and electrical properties. The sputtering pressure and substrate temperature have been varied to optimize the growth parameters of Ta2O5 thin films. The sputtering pressure was varied from 4.0 × 10–3 mbar to 1.0 × 10–2 mbar and the substrate temperature was varied from room temperature to 300 ℃. From XRD study it was found that the Ta2O5 film is polycrystalline in nature and possesses β—phase of orthorhombic structure. With increase in sputtering pressure and substrate temperature the crystallinity of the Ta2O5 thin film is found to be increases. The roughness of the film is found to be increased with increase in sputtering pressure and decreased with increase in substrate temperature. From the C-V and I-V measurements, the dielectric constant, oxide charge density, interface charge density and leakage current are estimated. The oxide charge density and leakage current for film prepared at 8.0 × 10–3 mbar sputtering pressure is found to be minimum with the enhancement of dielectric constant. The Ta2O5 film, deposited at 8.0 × 10–3 mbar sputtering pressure and 300 ℃ of substrate temperature, has possessed high dielectric constant, lower leakage current and low oxide charge. Hence, this film can be used as an alternative dielectric layer in microelectronics and MEMS devices.