Abstract
In recent years, many hardware implementations of the SHA-3 have been proposed to improve throughput, frequency, efficiency, or area. However, the increasing demand for hashing larger data requires other improved implementations of this function in terms of throughput. In this work, two different implementations of the Secure Hash Algorithm SHA-3 are proposed, the designs are based on the pipeline technique. Our main focus was to maximize the throughput of this function, also to analyze the impact of the use of the pipelining technique on this function The proposed designs are coded using VHDL language and implemented on two different devices Virtex 5 and 6 FPGA. The designs reach a maximum Throughput almost double 16.24 Gbps in the 2 stages external pipelining, and 17.01 Gbps in the internal pipelining. In contrast, it’s worth 8.12 Gbps on Virtex 5 for 512 bits output length in the case of one stage. However, this increase in the throughput will negatively affect the Area needed to implement the design.
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Assad, F., Fettach, M., Elotmani, F., Tragha, A. (2022). Two-Stage Pipelining Implementation of the Secure Hash Algorithm SHA-3 on Virtex-5 and Virtex-6 FPGAs. In: Maleh, Y., Alazab, M., Gherabi, N., Tawalbeh, L., Abd El-Latif, A.A. (eds) Advances in Information, Communication and Cybersecurity. ICI2C 2021. Lecture Notes in Networks and Systems, vol 357. Springer, Cham. https://doi.org/10.1007/978-3-030-91738-8_51
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