Abstract
The secure hash algorithm 3 (SHA-3) is an important technique for ensuring data authentication, integrity, and confidentiality. Improving the round function to enhance speed and resource efficiency has been a primary concern in most studies. However, processing long messages can consume a significant amount of time when retrieving data from external memory. Specifically, after completing one block of the message, the processor, such as the Central Processing Unit (CPU), is required to prepare the input for handling the next block. In this research, we present a high-performance and flexible hardware architecture for SHA3-512, specifically designed for applications with short and long messages without software intervention. We contribute two techniques. Firstly, we introduce an architecture designed to handle multiple messages, each with either a single block or multiple blocks. Secondly, we utilize a sequential processing technique for padding, catering to both short and long messages. Additionally, we implement the pipeline technique for the round function. The proposed SHA3-512 architecture is synthesized on Cyclone 5CSXFC6D6F31C6, achieving an impressive throughput of 12.05 Gbps at a clock frequency of 125.57 MHz, with each hash computation taking six clock cycles.
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This research is funded by University of Science, VNU-HCM under grant number 
T-VT 2022–03.
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Dang, TP., Tran, TK., Hoang, TT., Pham, CK., Huynh, HT. (2023). A High-Performance Pipelined FPGA-SoC Implementation of SHA3-512 for Single and Multiple Message Blocks. In: Dao, NN., Thinh, T.N., Nguyen, N.T. (eds) Intelligence of Things: Technologies and Applications. ICIT 2023. Lecture Notes on Data Engineering and Communications Technologies, vol 187. Springer, Cham. https://doi.org/10.1007/978-3-031-46573-4_27
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DOI: https://doi.org/10.1007/978-3-031-46573-4_27
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