Abstract
This chapter describes the application of VLASIC for analyzing the effects of adding redundancy to a design. Redundancy analysis is accomplished by means of a post-processor that uses the chip fault lists generated by VLASIC and a description of chip redundancy to predict yield in the presence of redundancy. We first discuss previous work in predicting the yield of redundant chips, then describe our redundancy analysis system, and finally provide examples of its use.
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© 1987 Springer Science+Business Media Dordrecht
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Walker, D.M.H. (1987). Redundancy Analysis System. In: Yield Simulation for Integrated Circuits. The Springer International Series in Engineering and Computer Science, vol 33. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-1931-4_7
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DOI: https://doi.org/10.1007/978-1-4757-1931-4_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5201-1
Online ISBN: 978-1-4757-1931-4
eBook Packages: Springer Book Archive