Abstract
An Application Specific Inflexible FPGA (ASIF) is an FPGA with reduced flexibility and improved density that can implement a predetermined set of application circuits which will operate at mutually exclusive times. A homogeneous ASIF is presented in the previous chapter; this chapter extends the work to heterogeneous domain. An ASIF that is reduced from a heterogeneous FPGA is called as heterogeneous ASIF. A heterogeneous ASIF can contain hard-blocks such as multipliers, adders, RAMS etc. In order to generate a heterogeneous ASIF, first a minimal FPGA architecture is defined that can implement any of the applications under consideration. Later these application circuits are efficiently placed and routed to minimize total routing switches required by the heterogeneous FPGA architecture. After that, all unused routing switches are removed from the FPGA to generate a heterogeneous ASIF.
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© 2012 Springer Science+Business Media New York
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Farooq, U., Marrakchi, Z., Mehrez, H. (2012). Tree-Based ASIF Using Heterogeneous Blocks. In: Tree-based Heterogeneous FPGA Architectures. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3594-5_6
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DOI: https://doi.org/10.1007/978-1-4614-3594-5_6
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Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-3593-8
Online ISBN: 978-1-4614-3594-5
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