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The demand for Digital processing of data is seamlessly increasing for various day to day applications around us. It is because of the easier, faster and cheaper way of processing and storing data in digital format, yet efficiently. This in-turn has resulted in demand for Mixed Signal processing systems to interface with the analog and digital world. The challenges in designing a Mixed Signal system are to suppress phase noise, higher switching speeds and optimum conversion capabilities with least power dissipation. PLL, OPAMP, DAC, ADC, etc. are some of the key building blocks in an Analog and Mixed Signal System.

In this chapter a Two Stage OPAMP is designed and modeled using SPICE based on the specifications provided for 180 nm technology. The simulations are carried out using LTspice tool to extract and verify the design parameter. A layout is designed for the OPAMP. DRC and LVS debug tools are used to verify the design rules and connectivity of the layout. Parasitics are also extracted and analyzed for the design. All these processes are carried out using Cadence Virtuoso Schematic and Layout editor tool for 180 nm technology.

The prerequisite to approach this chapter would be an adequate knowledge of CMOS designs in Analog domain and basic knowledge of layout designs and SPICE modeling.

4.1 Schematic Design of OPAMP

4.1.1 Introduction

An Operational Amplifier is a DC coupled high gain electronic voltage amplifier with differential inputs and usually a single output [1]. A two stage OPAMP consists of three major blocks – Differential Amplifier stage, Gain Stage with Compensation capacitor to lower the gain at high frequencies and Buffer. An OPAMP is used in a variety of applications in linear circuit applications: Differential amplifier, inverting and non-inverting amplifier, Integrator, Differentiator, Comparator, Voltage follower, etc. and in non-linear circuit applications: Peak detector, logarithmic, exponential outputs, PLL, ADC, DAC, etc. The functional block diagram of a Two Stage OPAMP is shown in Fig. 4.1 [2].

Fig. 4.1
figure 1_4

The functional block diagram of a two stage OPAMP

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4.1.2 Two Stage OPAMP Design

A Two Stage OPAMP is designed and simulated in this section [2]. The design is done using SPICE modeling and the simulations are carried out using LTspice to extract and verify the design parameters against the designed values. The model file obtained from MOSIS-TSMC library for 180 nm technology [3] is used in the OPAMP modeling and simulations.

4.1.2.1 Specifications

The Two Stage OPAMP is designed for TSMC 180 nm technology for the following specification:

  • Open Loop Gain, Av >100 V/V (40 dB)

  • Power Supply, VDD  =  −VSS  =  2.5 V

  • Gain Bandwidth at −3 dB gain, f 3db >5 MHz

  • Load Capacitance, C L  =  10 pF

  • Slew Rate, SR  >  10 V/μs

  • Output Voltage Swing, V out  =  ± 2 V

  • Input Common Mode Range, ICMR  =  −1 V to +2 V

  • Maximum Power Dissipation, P d  ≤  2 mW

  • Phase Margin, Φ m ≥   60°

  • Channel Length, L  =  180 nm

For 180 nm technology, the MOS device parameters obtained from MOSIS-TSMC fabrication process lab is as follows:

For NMOS:

  • K n ’  =  (μn Cox)/2  =  177.2 μA/V²

  • V tn  =  0.35 V

  • λ n  =  0.09/V

For PMOS:

  • K p ’  =  (μp Cox)/2  =  −35.6 μA/V²

  • V tp  =  −0.39 V

  • λ p  =  0.1/V

4.1.2.2 Schematic of OPAMP

The schematic diagram of Two Stage OPAMP for which aspect ratios for MOS transistors and compensation capacitance values is required to be calculated is shown in Fig. 4.2 [4].

Fig. 4.2
figure 2_4

The schematic diagram of two stage OPAMP

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4.1.2.3 Design Calculations

The Two Stage OPAMP is designed as per the specifications listed in Sect. 4.1.2.1. The end results of the design calculations are the channel width of each of the MOS transistor and Compensation capacitor value for the OPAMP. The design procedure followed is mentioned below [4]:

  1. 1.

    Calculation of Compensation capacitance (Cc):

It is known that placing the output pole 2.2 times higher than the Gain Bandwidth permitted a 60° Phase Margin. From the specifications, required Phase Margin is 60°.

Hence we have,

$$\text{Cc}>(2.2/10){\text{C}}_{\text{L}}$$
$$\text{Cc}>(0.22)\times 10\text{ pF}$$
$$\text{Cc}>2.\text{2 pF}$$
$$\text{Cc }=\text{ 3pF}$$
  1. 2.

    Calculation of Tail Current (Iss):

The tail current, Iss or I5 is given by,

$$\text{Iss }=\text{SR }\times \text{ Cc}$$
$$\text{Iss }=10\text{ V}/\mu \text{s }\times \text{ 3 pF}$$
$$\text{Iss }=30\mu \text{A}$$
  1. 3.

    Calculation of Aspect ratios (W/L)3 and (W/L)4 for M3 and M4:

The aspect ratio for M3 is calculated based on the ICMR (max) given in the specification.

$${\left(\text{W}/\text{L}\right)}_{3}=\left(2\times {\text{I}}_{5}\right)/{\left[{\text{K}}_{\text{p}}^\prime\left({\text{V}}_{\text{DD}}-{\text{V}}_{\text{in}-\mathrm{max}}-\left|{\text{V}}_{\text{tp}}\right|+{\text{V}}_{\text{tn}}\right)\right]}^{2}$$
$${\left(\text{W}/\text{L}\right)}_{3}=\left(2\times 30\times {10}^{-6}\right){\left[2.5-2-0.39+0.35\right]}^{2}$$
$${\text{(W}/\text{L)}}_{3}=3.98$$
$${\text{(W}/\text{L)}}_{3}=\text{ (W}/\text{L}{)}_{4}=4$$
  1. 4.

    Calculation of Aspect ratios (W/L)1 and (W/L)2 for M1 and M2:

The aspect ratio for M1 is calculated based on the Gain specification given.

$$\text{Av }=\text{ }[2/(\lambda \text{n}+\lambda \text{p)}]\times {\left[(2\times {\text{ K}}_{\text{n}}^\prime\times \text{ W)}/\text{(Iss }\times \text{ L)}\right]}^{1/2}$$

Given Specification, Av  >  100 V/  V

Substituting and solving the values in the above equation, we get,

$$\text{(W}/\text{L)}{1}_{}=7.64$$
$$\text{(W}/\text{L)}{1}_{}=\text{ (W}/\text{L}{)}_{2}=8$$
  1. 5.

    Calculation of Aspect ratios (W/  L)5 and (W/  L)8 for M5 and M8:

The aspect ratio for M5 is calculated based on ICMR (min) specification.

$${\text{V}}_{\text{ds5}}={\text{V}}_{\text{in}}\left(\mathrm{min}\right)-{\text{V}}_{\text{ss}}-\left[{\text{I}}_{5}/\left({K}_{\text{n}}^\prime\left(\text{W}/\text{L}\right)_{1}\right)-\text{Vtn}\right]$$

Substituting the values from the specification data and previous calculations,

We get,

$${\text{V}}_{\text{ds5}}=1.00\text{5 V}$$
$$\left(\text{W}/\text{L}\right)_{5}=\left(2\times {\text{I}}_{5}\right)/\left[{K}_{\text{n}}^\prime\times \left({\text{V}}_{\text{ds}5}\right)^{2}\right]$$

Substituting the values in the above equation, we get,

$${\text{(W}/\text{L)}}_{5}=0.34$$
$${\text{(W}/\text{L)}}_{5}=\text{ (W}/\text{L}{)}_{8}=1$$
  1. 6.

    Calculation of Aspect ratio (W/L)6 for M6:

The Transconductance of the input transistor M1 is given by,

$${\text{g}}_{\text{m1}}=\text{ (Gain Bandwidth) x (Compensation Capacitance)}$$
$${\text{g}}_{\text{m1}}=2\pi \times 5\times {10}^{6}\times 3\times {10}^{-12}$$
$${\text{g}}_{\text{m1}}=94.25\mu \text{S}$$

The Transconductance of the transistor M6 is calculated for the given specification of Phase Margin  ≥  60°

$$\text{gm6}\ge 10\text{gm1}$$
$$\text{gm6 }=942.5\mu \text{S}$$

The aspect ratio for M6 is calculated as follows:

$$\left(\text{W}/\text{L}\right)_{6}={\text{g}}_{\text{m6}}/\left[{\text{K}}_{\text{p}}^\prime\times {\text{V}}_{\text{ds6 }}\text{(sat)}\right]$$

Substituting values in the above equation, we get,

$${\text{(W}/\text{L)}}_{6}=54$$
  1. 7.

    Calculation of Aspect ratio (W/L)7 for M7:

The current flowing through transistor M6 is given by

$${\text{I}}_{6}=({\text{g}}_{\text{m6}})/\left[2\times {\text{K}}_{\text{p}}^\prime\times \text{ (W}/\text{L}{)}_{6}\right]$$

Substituting the values in the equation,

$${\text{I}}_{6}=230\mu \text{A}$$

The aspect ratio for M7 is given by the following equation:

$${\text{(W}/\text{L)}}_{7}=\text{ (W}/\text{L}{)}_{5}\times ({\text{I}}_{6}/{\text{I}}_{5})$$

Substituting values in the above equation, we get,

$$\text{(W}/\text{L)}_{7}\text=8$$

4.1.2.4 Design Calculation Results

The maximum power dissipation for the design is verified against the specification as follows:

Power Dissipation,

$$\text{Pd(max) }=({\text{I}}_{5}+{\text{I}}_{6})\times \text{ (VDD }+\left|\text{VSS}\right|)$$
$$\text{Pd(max) }=(30\mu +230\mu )\times (2.5+|-2.5|)$$
$$\text{Pd(max) }=1.\text{3 mW}$$

Max. power dissipation for the design is less than the specified limit of 2 mW.

The channel width required for each of the MOS transistors for the OPAMP designed is calculated from the aspect ratios. For 180 nm process technology the channel width is tabulated as shown in Table 4.1

Table 4.1 Channel width of MOS transistors designed for 180 nm technology OPAMP
Full size table

Other important parameters calculated in the design steps are as follows:

  • Compensation Capacitance, C c  =  3 pF

  • Load Resistance (Arbitrary value), R L  =  100 kW

  • Current flowing through M5 (Tail Current), I 5  =  30 μA

  • Current flowing through M6, I 6  =  230 μA

4.1.2.5 Definition of Design Parameters

Definition of design parameters that are extracted from the simulation of TS-OPAMP are as follows:

  1. 1.

    Open Loop Gain: The Gain of the OPAMP for the input at positive input terminal without feedback and negative terminal input grounded

  2. 2.

    Gain Bandwidth: The frequency Bandwidth of the system at which the gain drops to −3 dB gain

  3. 3.

    Phase Margin: It is the difference measured in degrees between the absolute phase angle of OPAMP output signal and 180°

  4. 4.

    Input Common Mode Range (ICMR): The range of input voltage where the OPAMP has approximately unity gain

  5. 5.

    Input Offset Voltage: The input required to make the output of the OPAMP to zero volts

  6. 6.

    Output Voltage Swing: The range of the maximum voltage points till which the OPAMP output can swing

  7. 7.

    Slew Rate: It is the maximum rate of change of output signal at any point of time

  8. 8.

    Transfer Function: It is a function of Output of the OPAMP with respect to the Input

  9. 9.

    Output Impedance: The Impedance offered by the OPAMP at the output terminal

  10. 10.

    Power Dissipation: The total power dissipated by the OPAMP during its operation

4.1.2.6 Simulations and Verification

The Two Stage OPAMP designed for 180 nm process technology is simulated using LT Spice and the design specifications are verified against the extracted values [5]. The model file obtained from MOSIS-TSMC library for 180 nm technology is used in the OPAMP modeling and simulations.

  • Extraction of Open Loop Gain, Gain Bandwidth and Phase Margin at 0db Gain

AC analysis done to extract the above mentioned parameters. The simulation waveform obtained (Bode Plot) is shown in Fig. 4.3 .

Fig. 4.3
figure 3_4

Simulation of TS-OPAMP to extract AC analysis parameters at 0 dB gain

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Configuration: Open Loop (Extracted parameters at 0 dB gain)

  • Gain: 28 dB

  • Bandwidth: 4 MHz

  • Phase Margin: (180°  +  Φ)  =  180° – 102°  =  78°

  • Extraction of Open Loop Gain, Gain Bandwidth and Phase Margin at -3db Gain

AC analysis done to extract the above mentioned parameters. The simulation waveform obtained (Bode Plot) is shown in Fig. 4.4.

Fig. 4.4
figure 4_4

Simulation of TS-OPAMP to extract AC analysis parameters at 3 dB gain

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Configuration: Open Loop (Extracted parameters at −3 dB gain)

  • Gain: 28 dB

  • Bandwidth: 5.5 MHz

  • Phase Margin: (180°  +  Φ)  =  180° – 108°  =  72°

  • Extraction of ICMR

The simulation waveform obtained to extract ICMR is shown in Fig. 4.5.

Fig. 4.5
figure 5_4

Simulation of TS-OPAMP to extract ICMR for the design

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Configuration: Unity Gain Feedback

  • ICMR: −1.2 V to +2.1 V

  • Extraction of Input Offset Voltage

The simulation waveform obtained to extract Input Offset Voltage is shown in Fig. 4.6.

Fig. 4.6
figure 6_4

Simulation of TS-OPAMP to extract input offset voltage for the design

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Configuration: Open Loop

  • IOV: −92 mV

  • Extraction of Output Voltage Swing

The simulation waveforms obtained to extract Output Voltage Swing is shown in Fig. 4.7.

Fig. 4.7
figure 7_4

Simulation of TS-OPAMP to extract output voltage Swing

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Configuration: Open Loop

  • OVS: −1.1 V to 2.1 V

  • Extraction of Transfer function and Output Impedance

The simulation results obtained to extract Transfer function and Output Impedance of the design is shown in Fig. 4.8.

Fig. 4.8
figure 8_4

Snapshot of the transfer function computed for TS-OPAMP design

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Configuration: Open Loop

  • Transfer Function: 12.795

  • Output Impedance: 8.6 kW

  • Extraction of Maximum Power Dissipation

The simulation waveform obtained to extract maximum Power Dissipation of the TS-OPAMP designed is shown in Fig. 4.9.

Fig. 4.9
figure 9_4

Simulation of TS-OPAMP to extract max. Power dissipation of the design

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Configuration: Unity Gain Feedback

  • Max. Power Dissipation,

    $${\text{P}}_{\text{d}}=(38.8\mu \text{A }+122\mu \text{A) }\times (2.\text{5 V}+|-2.\text{5 V}|)$$
    $${\text{P}}_{\text{d}}=0.80\text{4 mW}$$

  • Extraction of Slew Rate

The simulated waveform obtained to extract Slew Rate for the design is shown in Fig. 4.10.

Fig. 4.10
figure 10_4

Simulation of TS-OPAMP to extract slew rate for the design

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Configuration: Unity Gain Feedback

  • Slew Rate (SR)  =  (V2 – V1)/ (T2 – T1)

$$\text{SR}=\left[0.94\text{V}-\left(-0.79\text{V}\right)\right]/\left(100.23\mu \text{s}-100.01\mu \text{s}\right)$$
$$\text{SR }\approx \text{ 8V}/\mu \text{s}$$

4.1.3 Results

The result obtained from the simulations carried out for TS-OPAMP is verified against the specification. The comparison results are tabulated as in Table 4.2.

Table 4.2 Comparison of design specification against results obtained for TS-OPAMP design
Full size table

4.2 Layout Design of OPAMP

4.2.1 Introduction

The Two Stage OPAMP designed in Sect. 4.1 is implemented to obtain the layout with optimal area and least parasitics for 180 nm technology. A schematic of TS-OPAMP is also drawn along with the layout. Cadence Virtuoso tool is used to draw schematic and layout for the design. After obtaining the layout with clean DRC and LVS, the netlist along with the parasitics is extracted with the help of the tool. Post layout simulation is carried out using this netlist to verify the design specifications.

4.2.2 Layout Design

In this section, the procedure for schematic and layout design of TS-OPAMP is illustrated.

4.2.2.1 Schematic Design of OPAMP

The schematic design is required to carry out LVS after drawing the layout section to verify the connectivity of the circuit. The screenshot of the schematic design of TS-OPAMP is shown in Fig. 4.11. The components are chosen as per the designed results available in Table 4.2. Metal plate capacitor is selected for the layout design for compensation capacitor.

Fig. 4.11
figure 11_4

Schematic of TS-OPAMP

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4.2.2.2 Layout Design of OPAMP

The Layout of OPAMP is drawn as per the schematic in Fig. 4.11. From the Table 4.2 it can be noted that MOSFET M7 has very large channel width. In order to avoid delays and other parasitic effects caused due to large channel width, fingering is done to break up the MOSFET into 10 MOSFETs of equal channel width [6]. The screenshot of MOSFET M7 with finger – 10 is shown in Fig. 4.12.

Fig. 4.12
figure 12_4

Screenshot of MOSFET with finger-10

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Since the finger for M7 is 10, the total channel width of 9.8 μm is divided into 10 MOSFETs with channel width of 0.98 μm each. The Fig. 4.12 shows the alternate connections made to the source of MOSFET to connect it to the VDD power line. Similarly, alternate connections are done for the drain as well.

The screenshot of completed layout design of TS-OPAMP is shown in Fig. 4.13.

Fig. 4.13
figure 13_4

Screenshot of completed layout design of TS-OPAMP

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The completed layout of TS-OPAMP is verified for DRC. Once the layout is DRC clean, LVS is performed against the schematic to verify the connectivity of the design. LVS match is obtained for the design. The screenshot of LVS match indicator for the design is shown in Fig. 4.14.

Fig. 4.14
figure 14_4

Screenshot of LVS match for TS-OPAMP design

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For the LVS matched layout design, the SPICE netlist along with parasitics is extracted using RCXT tool in Cadence Virtuoso. Graphical view of the parasitics such as, resistance and capacitance in the layout design is also observed. Some of the screenshots obtained to illustrate the parasitics in the layout design are shown in the following figures.

The screenshot of the complete TS-OPAMP layout with parasitics identified is shown in Fig. 4.15 .

Fig. 4.15
figure 15_4

Screenshot of TS-OPAMP layout with parasitics identified in the design

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The parasitics existing at poly of MOSFET having 10 fingers is shown in Fig. 4.16 .

Fig. 4.16
figure 16_4

Screenshot of parasitics in MOSFET layout having 10 fingers in TS-OPAMP layout design

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The parasitics identified in metal plate compensation capacitor is shown in Fig. 4.17.

Fig. 4.17
figure 17_4

Screenshot of parasitics identified in layout of compensation capacitor

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4.2.3 Summary and Results

The DRC clean and LVS match layout design of TS-OPAMP obtained have parasitics that affect the function of the design. Post layout simulation using the generated SPICE netlist for the design is carried out in LTspice to verify the specification parameters. The layout design has approximately 67 Resistances and 68 Capacitance parasitics. The area of the layout of TS-OPAMP is calculated as follows:

$$\text{Approximate}\text{Height of the Cell (H)}=10\mu \text{m}$$
$$\text{Approximate}\text{Width of the Cell (W)}=12\mu \text{m}$$
$$\text{Area}=\text{H}\times \text{W}=10\mu \text{m}\times 12\mu \text{m}=120{\mu }^{2}{\text{m}}^{2}$$

The total area used by the TS-OPAMP layout designed cell including unused area is approximately 120 μ²m²

The layout can be improved by meticulously planning the placement of MOSFETs to obtain optimized area with least parasitics. The unused area in the design can be effectively used to reduce the area metrics for the layout design. The width of the OPAMP cell is an arbitrary value as there is no reference cell with least width available. This applies also to the height of the OPAMP.