Task scheduling on multiple heterogeneous processors is notorious for its computation intractability. Although previous design-time task schedulers have tackled this intractability with fast heuristics, it remains time-consuming to explore the design space for large input TF. This chapter presents a novel method that combines the graph partition and the TF interleaving technique to tackle the trade-off exploration problem in a scalable way. Based on this method, we have developed a hierarchical scheduler that can employ the existing design-time schedulers and can significantly accelerate the design space explorations for large TF.
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(2007). Scalable Design-Time Scheduling. In: Ma, Z., et al. Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogeneous Platforms. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6344-2_5
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DOI: https://doi.org/10.1007/978-1-4020-6344-2_5
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-6328-2
Online ISBN: 978-1-4020-6344-2
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