Abstract
Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an architecture that relies on dynamic reconfiguration of hardware resources to implement low-power and programmable processors for DSP applications. In this paper, we evaluate this architectural approach and compare it to other programmable architectures.
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© 1998 Springer-Verlag Berlin Heidelberg
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Abnous, A., Seno, K., Ichikawa, Y., Wan, M., Rabaey, J. (1998). Evaluation of a low-power reconfigurable DSP architecture. In: Rolim, J. (eds) Parallel and Distributed Processing. IPPS 1998. Lecture Notes in Computer Science, vol 1388. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-64359-1_673
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DOI: https://doi.org/10.1007/3-540-64359-1_673
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