Access provided by Autonomous University of Puebla. Download to read the full chapter text
Chapter PDF
Keywords
- PMOS Transistor
- Velocity Saturation
- Inversion Charge
- Drain Induce Barrier Lowering
- Channel Length Modulation
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
Vittoz, E. “Micropower techniques”, Design of VLSI Circuits for Telecommunication and Signal Processing, J. E. Franca and Y. P. Tsividis, Eds., Chapter 5, Prentice Hall, 1993.
Vittoz, E.; Enz, C.; Krummenacher, F. “A basic property of MOS transistors and its circuit implications”, Workshop on Compact Models - 6th Int. Conf. Modeling and Simulation of Microsystems (MSM 2003) California, USA: San Francisco, February 2003, 23-27. Charge Model/Surface Potential Model Development
Maher, M. A.; Mead, C. A. “A physical charge-controlled model for the MOS tran-sistors”, Advanced Research in VLSI, P. Losleben, Ed. Cambridge, MA: MIT Press, 1987.
Iniguez, B.; Moreno, E. G. “A physically based C-finite continuous model for small-geometry MOSFET”, IEEE Trans. Electron Dev., February 1995, 42(2), 283-7.
Enz, C. C.; Krummenacher, F.;Vittoz, E. A. “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications”, J. Analog Int. Circ. Signal Processing, 1995, 8, 83-114.
Cunha, A. I. A.; Schneider, M. C.; Galup-Montoro, C. “An explicit physical model for the long-channel MOS transistor including small-signal parameters”, Solid-State Electron., November 1995, 38(11), 1945-1952.
Cunha, A. I. A.; Gouveia-Filho, O.; Schneider, M. C.; Galup-Montoro, C. “A current-based model of the MOS transistor”, Proc. IEEE Int. Symp. on Circ. & Syst. (ISCAS’97), June 1997, 3, 1608-1611.
Bucher, M.; Enz, C.; Lallement, C.; Theodoloz, F.; Krummenacher, F. “Scalable GM/I based MOSFET model”, Int. Semicond. Dev. Research Symp. (ISDRS’97), Virginia: Charlottesville, December 1997, 615-618.
Tsividis, Y. “Operation and modelling of the MOS transistor”, 2nd edition, McGraw-Hill, 1999.
Bucher, M. “Analytical MOS transistor modeling for analog circuit simulation”, Ph. D. Thesis No. 2114 (1999), Swiss Federal Institute of Technology, Lausanne (EPFL) , Switzerland, 2000.
Enz, C.; Bucher, M.; Porret, A. -S.; Sallese, J. -M.; Krummenacher, F. “The foun-dations of the EKV MOS transistor charge-based model”, Workshop on Compact Models - 5th Int. Conf. Modeling and Simul. Microsystems (MSM 2002), Puerto Rico, USA: San Juan, April 2002, 666-669.
Sallese, J. -M.; Bucher, M.; Krummenacher, F.; Fazan, P. “Inversion charge lineariza-tion in MOSFET modeling and rigorous derivation of the EKV compact model”, Solid-State Electron., 2003, 47, 677-683.
Gildenblat, G.; Wang, H.; Chen, T. -L.; Gu, X.; Cai, X. “SP: An advanced surface-potential-based compact MOSFET model”, IEEE J. Solid-State Circuits, September 2004, 39(9), 1394-1406.
Watts, J.; McAndrew, C.; Enz, C.; Galup-Montoro, C.; Gildenblat, G.; Hu, C.; van Langevelde, R.; Miura-Mattausch, M.; Rios, R.; Sah, C. -T. “Advanced compact models for MOSFETs”, Workshop on Compact Models - Nanotech 2005, California, USA: Anaheim, May 2005, 9-12. Polydepletion and Quantum Effects
Sallese, J. -M.; Bucher, M.; Lallement, C. “Improved analytical modelling of polysili-con depletion for CMOS circuit simulation”, Solid-State Electron., June 2000, 44(6), 905-912.
Bucher, M.; Sallese, J. -M.; Lallement, C. “Accounting for quantum effects and polysilicon depletion in an analytical design-oriented MOSFET model”, IEEE Int. Conf. Simul. Semicond. Processes and Dev. (SISPAD 2001), D. Tsoukalas and C. Tsamis, Eds., Athens, Greece: Springer, September 2001, 296-299, ISBN 3-211-83708-6.
Lallement, C.; Sallese, J. -M.; Bucher, M.; Grabinski, W.; Fazan, P. “Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model”, IEEE Trans. Electron Dev., February 2003, 50 (2), 406-417. Charge/Transcapacitances Modelling
Ward, D. E. “Charge based modeling of capacitance in MOS transistors”, Technical Report G201-11, Integrated Circuits Laboratory, Stanford University, June 1981.
Bucher, M.; Sallese, J. -M.; Lallement, C.; Grabinski, W.; Enz, C. C.; Krummenacher, F. “Extended charges modelling for deep submicron CMOS”, Int. Semicond. Device Research Symp. (ISDRS’99), Virginia: Charlottesville, December 1999, 397-400.
Bucher, M.; Enz, C.; Krummenacher, F.; Sallese, J. -M.; Lallement, C.; Porret, A. -S. “The EKV 3. 0 MOS transistor compact model: Accounting for deep submicron aspects”, (Invited Paper), Workshop on Compact Models - 5th Int. Conf. Modeling and Simul. Microsystems (MSM 2002), Puerto Rico, USA: San Juan, April 2002, 670-673. Mobility Modelling, Low-T MOS Application
Martin, P.; Bucher, M.; Enz, C. “MOSFET modeling and parameter extraction for low temperature analog circuit design”, Journal de Physique IV, 12, 2002, Pr3-51-56, Les Editions de Physique, Les Ulis, France.
Saramad, S.;Anelli, G.; Bucher, M.; Despeisse, M.; Jarron, P.; Pelloux, N.; Rivetti, A. “Modeling of an integrated active feedback preamplifier in a 0. 25 µm CMOS tech-nology at cryogenic temperatures”, IEEE Trans. Nucl. Sci., August 2003, 50(8).
Martin, P.; Bucher, M. “Comparison of 0. 35 and 0. 21 µm CMOS technologies for low temperature operation (77 K-200 K) and Analog Circuit Design”, 6th European Workshop on Low Temperature Electronics (WOLTE 6), The Netherlands: Noordwijk, June 2004, 23-26. Series Resistance, Overlap Capacitance
Cserveny, S. “Relationship between measured and intrinsic transconductances of MOSFETs”, IEEE Trans. Electron Dev., 1990, 37(11), 2413-2414.
Prégaldiny, F.; Lallement, C.; Mathiot, D. “A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs”, Solid-State Electron., 2002, 46, 2191-2198.
Gildenblat, G.; Cai, X.; Chen, T. -L.; Gu, X.; Wang, H. “Reemergence of the surface potential based compact models”, IEDM Tech. Digest, 2003, 863-866. High-Frequency and Noise Modelling of the MOSFET
Enz, C.; Cheng, Y. “MOS transistor modeling for RF IC design”, IEEE Trans. Solid-State Circuits, February 2000, 35(2), 186-201.
Porret, A. -S.; Sallese, J. -M.; Enz, C. “A compact non quasi-static extension of a charge-based MOS model”, IEEE Trans. Electron Devices, 2001, 48(8), 1647-1654.
Scholten, A.; “A large signal non-quasi-static MOS model for RF circuit simulation”, IEEE Int. Conf. Simul. Semicond. Processes and Dev. (SISPAD 2001), D. Tsoukalas and C. Tsamis, Eds., Athens, Greece: Springer, September 2001, 373-376, ISBN 3-211-83708-6.
Enz, C. “An MOS transistor model for RF IC design valid in all regions of operation”, IEEE Trans. Microwave Theory and Tech., 2002, 50(1), 342-359.
Porret, A. -S. “Design of a low-power and low-voltage UHF transceiver integrated in a CMOS process”, Ph. D. Thesis No. 2542 (2002), Swiss Federal Institute of Technology, Lausanne (EPFL), Switzerland, 2002.
Porret, A. -S.; Enz, C. C. “Non-quasi-static (NQS) thermal noise modeling of the MOS transistor”, IEE Proc. Circuits, Dev. and Syst., 2004, 151(2), 155-166.
Bucher, M.; Bazigos, A.; Nastos, N.; Papananos, Y.; Krummenacher, F.;Yoshitomi, S. “Analysis of harmonic distortion in deep submicron CMOS”, Proc. 11th IEEE Int. Conf. Electron., Circ. & Syst. (ICECS 2004), 395-398, Tel Aviv, Israel, December 2004, 13-15.
Roy, A. S.; Enz, C. C. “Compact modeling of thermal noise in the MOS transistor”, IEEE Trans. Electron Dev., April 2005, 52(4), 611-614.
Yoshitomi, S. “Challenges of compact modeling for deep-submicron RF-CMOS devices”, 12th Int. Conf. Mixed Design (MIXDES 2005), Krakow, Poland, June 2005, 22-25. Transconductance Analysis
Binkley, D.; Bucher, M.; Foty, D. “Design-oriented characterization of CMOS over the continuum of inversion level and channel length”, Proc. IEEE Int. Conf. Electron., Circ. & Syst. (ICECS’2k), Kaslik, Lebanon, December 2000, 161-164.
Bucher, M.; Kazazis, D.; Krummenacher, F.; Binkley, D.; Foty, D.; Papananos, Y. “Analysis of transconductances at all levels of inversion in deep submicron CMOS”, Proc. 9th IEEE Conf. Electronics, Circ. & Syst. (ICECS 2002), Dubrovnik, Croatia, September 15-18, 2002, III, 1183-1186. Parameter Extraction
Machado, G.; Enz, C.; Bucher, M. “Estimating key parameters in the EKV MOSFET model for analogue circuit design and simulation”, Proc. IEEE Int. Symp. Circ. & Syst. (ISCAS’95), Seattle, Washington, April 30-May 3, 1995, 1588-1591.
Bucher, M.; Lallement, C.; Enz, C. “An efficient parameter extraction methodology for the EKV MOSFET model”, Proc. IEEE Int. Conf. Microelectronic Test Structures (ICMTS’96), Trento, Italy, March 25-28, 1996, 9, 145-150.
Lallement, C.; Bucher, M.; Enz, C. “Modelling and characterization of non-uniform substrate doping”, Solid-State Electronics, December 1997, 41(12), 1857-1861.
Bazigos, A.; Bucher, M. “The EKV3. 0 model code and parameter extraction”, EKV Model Users’ Group Meeting and Workshop, EPFL, Lausanne, Switzerland, November 4-5, 2004. Model Development
Bucher, M.; Lallement, C.; Enz, C.; Krummenacher, F. “Accurate MOS modelling for analog circuit simulation using the EKV model”, Proc. IEEE Int. Symp. Circ. & Syst. (ISCAS’96), Atlanta, Georgia, May 1996, 703-706.
Bucher, M.; Lallement, C.; Enz, C.; Theodoloz, F.; Krummenacher, F. “The EPFL-EKV MOSFET model equations for simulation, version 2. 6”, Technical Report, Elec-tronics Laboratory, EPFL, June 1997. [Available Online:] http://legwww. epfl. ch/ekv
Bucher, M.; Enz, C.; Krummenacher, F.; Sallese, J. -M.; Lallement, C.; Porret, A. -S. “The EKV3. 0 compact MOS transistor model: Accounting for deep submi-cron aspects”, Workshop on Compact Models-MSM 2002, Puerto Rico, April 2002, 670-673.
Bucher, M.; Enz, C.; Krummenacher, F.; Sallese, J. -M.; Lallement, C.; Porret, A. -S. “The EKV3. 0 compact MOS transistor model: Accounting for deep submi-cron aspects”, Workshop on Compact Models-MSM 2002, Puerto Rico, April 2002, 670-673.
Bucher, M.; Lallement, C.; Krummenacher, F.; Enz, C. “A MOS transistor model for mixed analog-digital IC design”, R. Reis and J. Jess Eds., In Design of System on a Chip. Devices & Components, Kluwer Acad. Publ., 2004, ISBN 1-4020-7928-1.
Bucher, M.; Krummenacher, F.; Bazigos, A. “The EKV3. 0 MOSFET model for advanced analog IC design”, EKV Model Users’ Group Meeting and Workshop, EPFL, Lausanne, Switzerland, November 4-5, 2004. Verilog-A Modelling
Lemaître, L.; Grabinski, W.; McAndrew, C. “Compact device modeling using Verilog-AMS and ADMS”, Electron Technol. Internet J., 2003, 2(35), 1-5, ISSN 0700-9816.
Bazigos, A.; Bucher, M.;Yoshitomi, S. “Benchmarking the EKV3. 0 MOSFET model in Verilog-A and 0. 14 µm CMOS”, Int. Conf. on Mixed Design (MIXDES 2004), Sczcecin, Poland, June 24-26, 2004, 104-109.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer
About this chapter
Cite this chapter
Bucher, M., Bazigos, A., Krummenacher, F., Sallese, JM., Enz, C. (2006). EKV3.0: An advanced charge based MOS transistor model.A design-oriented MOS transistor compact model. In: GRABINSKI, W., NAUWELAERS, B., SCHREURS, D. (eds) TRANSISTOR LEVEL MODELING FOR ANALOG/RF IC DESIGN. Springer, Dordrecht. https://doi.org/10.1007/1-4020-4556-5_3
Download citation
DOI: https://doi.org/10.1007/1-4020-4556-5_3
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-4555-4
Online ISBN: 978-1-4020-4556-1
eBook Packages: EngineeringEngineering (R0)