Access provided by Autonomous University of Puebla. Download to read the full chapter text
Chapter PDF
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
BSIM3 and BSIM4: www-device. eecs. berkeley. edu
Velghe, R. M. D. A., Klaassen, D. B. M., Klaassen, F. M., “MOS Model 9”, NL-UR 003/94, Philips Electron. N. V., 1994. internet: www.semiconductors.philips.com/Philips_Models.
Watts, J., et al., “Advanced compact models for MOSFETs”, In Proc. NSTI-Nanotech, 2005, 3-12.
Gildenblat, G., Wang, H., Chen, T. L., Gu, X., Cai, X., “SP: An advanced surface-potential-based compact MOSFET model”, IEEE J. Solid-State Circ., 2004, 39, 1394-1406.
Chen, T. L., Gildenblat, G., “Analytical approximation for the MOSFET surface potential”, Solid-State Electron., 2001, 45, 335-339.
Chen, T. L., Gildenblat, G., “Symmetric bulk charge linearisation in charge-sheet MOSFET model”, Electron. Lett., 2001, 37, 791-793.
Gildenblat, G., Chen, T. L., “Overview of an advanced surface-potential-based model (SP)”, In Proc. NSTI-Nanotech, 2002, 657-661.
Wang, H., Chen, T. L., Gildenblat, G., “Quasi-static and nonquasi-static compact MOSFET models based on symmetric linearization of the bulk and inversion charges”, IEEE Trans. Electron Dev., 2003, 50, 2262-2272.
Gu, X., Wang, H., Chen, T. L., Gildenblat, G., “Substrate current in surface-potential-based models”, In Proc. NSTI-Nanotech, 2003, 310-312.
Gildenblat, G., Chen, T. L., Gu, X., Wang, H., Cai, X., “SP: An advanced surface-potential-based compact MOSFET model”, In Proc. CICC, 2003, 233-240.
Gildenblat, G., Cai, X., Chen, T. L., Gu, X., Wang, H., “Reemergence of the surface-potential-based compact MOSFET models”, In IEDM Tech. Digest, 2003, 863-866
Gu, X., Chen, T. L., Gildenblat, G., Workman, G. O., Veeraraghavan, S., Shapira, S., Stiles, K., “A surface potential-based compact model of n-MOSFET gate-tunneling current”, IEEE Trans. Electron Dev., 2004, 51, 127-135.
Gildenblat, G., McAndrew, C. C., Wang, H., Wu, W., Foty, D., Lemaitre, L., Bendix, P., “Advanced compact models: Gateway to modern CMOS design”, In Proc. ICECS, 2004, 638-641.
Wu, W., Chen, T. L., Gildenblat, G., McAndrew, C. C., “Physics-based mathematical conditioning of the MOSFET surface potential equation”, IEEE Transactions on Electron Dev., July 2004, 51, 1196-1200.
Wang, H., Gildenblat, G., “A robust large signal non-quasi-static MOSFET model for circuit simulation”, In Proc. IEEE CICC, 2004, 5-8.
Chen, T. L., Gildenblat, G., “An extended analytical approximation for the MOSFET surface potential”, Solid-State Electron., 2005, 49, 267-270.
Wu, W., et al., “SP-SOI: A third generation surface potential based compact SOI MOSFET model”, In Proc. IEEE CICC, 2005, 819-822.
van Langevelde, R., Klaassen, F. M., “An explicit surface-potential-based MOSFET model for circuit simulation”, Solid-State Electron., 2000, 44, 409-418.
van Langevelde, R., Tiemeijer, L. F., Havens, R. J., Knitel, M. J., Roes, R. F. M., Woerlee, P. H., Klaassen, D. B. M., “RF-distortion in deep-submicron CMOS technologies”, In IEDM Tech. Digest, 2000, 807-810.
van Langevelde, R., Scholten, A. J., Havens, R. J., Tiemeijer, L. F., Klaassen, D. B. M., “Advanced compact MOS modeling”, In Proc. ESSDERC, 2001, 81-88.
van Langevelde, R., Scholten, A. J., Duffy, R., Cubaynes, F. N., Knitel, M. J., Klaassen, D. B. M., “Gate current: Modeling, L extraction and impact on RF performance”, In IEDM Tech. Digest, 2001, 289-292.
van Langevelde, R., Scholten, A. J., Klaassen, D. B. M., “MOS Model 11, level 1101”, NL-UR 2002/802, Philips Electron. N. V., 2002. www.semiconductors. philips.com/Philips Models/mos models/model11/
van Langevelde, R., Scholten, A. J., Klaassen, D. B. M., “Physical background of MOS Model 11, level 1101”, NL-UR 2003/00238, Philips Electron. N. V., 2003. www.semiconductors.philips.com/Philips Models/mos_models/model11/
van Langevelde, R., Paasschens, J. C. J., Scholten, A. J., Havens, R. J., Tiemeijer, L. F., Klaassen, D. B. M., “New compact model for induced gate current noise”, In IEDM Tech. Digest, 2003, 867-870.
van Langevelde, R., Scholten, A. J., Klaassen, D. B. M., “Recent enhancements of MOS model 11”, In Proc. NSTI-Nanotech, 2004, 60-65.
Klaassen, D. B. M., van Langevelde, R., Scholten, A. J., “Compact CMOS modeling for advanced analog and RF applications”, IEICE Trans. Electron., 2004, E87-C, 854-866.
Pao, H. C., Sah, C. T., “Effects of diffusion current on characteristics of metal-oxide (Insulator)-semiconductor transistors”, Solid-State Electron., 1966, 9, 927-937.
Brews, J. R., “A charge-sheet model of the MOSFET”, Solid-State Electron., 1978, 21, 345-355.
Tsividis, Y. P., Operation and modeling of the MOS transistor, New York: McGraw-Hill, 1999.
Scholten, A. J., Smit, G. D. J., Durand, M., van Langevelde, R., Dachs, C. J. J., Klaassen, D. B. M., “A new compact model for junctions in advanced CMOS technologies”, In IEDM Tech. Digest, 2005, 209-212.
Wang, H. et al., “Unified non-quasi-static MOSFET model for large-signal and small-signal simulations”, In Proc. IEEE CICC, 2005, 823-826.
PSP: pspmodel. ee. psu. edu
Arora, N. D. MOSFET models for VLSI circuit simulation, Wien: Springer-Verlag, 1993.
McAndrew, C. C., Victory, J. J., “Accuracy of approximations in MOSFET charge models”, IEEE Trans. Electron Dev., 2002, 49, 72-81.
Sah, C. T., “A history of MOS transistor compact modeling”, In Proc. NSTI-Nanotech, 2005, 437-390.
Boothroyd, A. R., Tarasewicz, S. W., Slaby, C., “MISNAN -A physically based continuous MOSFET model for CAD applications”, IEEE Trans. Comput. Aided Design, 1991, 10, 1512-1529.
Rios, R., Murdanai, S., Shih W. K., Packan, P., “An efficient surface potential solution algorithm for compact MOSFET models”, In IEDM Tech. Digest, 2004, 755-758.
Miura-Mattausch, M. et al., “HiSIM: A MOSFET model for circuit simulation con-necting circuit performance with technology, ” In IEDM Tech. Digest, 2002, 109-112.
Turchetti, C., Masetti, G., “A CAD-oriented analytical MOSFET model for high-accuracy applications”, IEEE Trans. Comput. Aided Design, 1984, 3, 117-122.
Bagheri, M., Tsividis, Y., “A small-signal DC-to-high-frequency non-quasistatic model for four-terminal MOSFETs valid in all regions of operation”, IEEE Trans. on Electron Dev., 1985, 32, 2383-91.
Howes, R. et al., “A charge-conserving silicon-on-sapphire SPICE MOSFET model for analog design”, IEEE Int. Symp. Circ. Systems, 1991, 4, 2160-2163.
Nguyen, T. N., Plummer, J. D., “Physical mechanisms responsible for short channel effects in MOS devices”, In IEDM Tech. Digest, 1981, 596-599.
Skotnicki, T., Merckel, G., Pedron, T., “The voltage-doping transformation: A new approach to modeling of MOSFET short-channel effects”, IEEE Electron Dev. Lett., 1988, 9, 109-112.
Miura-Mattausch, M., “Analytical MOSFET model for quarter micron technologies”, IEEE Trans. Comput. Aided Design, 1994, 13, 610-615.
Joardar, K., Gullapulli, K. K., McAndrew, C. C., Burnham M. E., Wild, A., “An improved MOSFET model for circuit simulation”, IEEE Trans. Electron Dev., 1998, 45, 134-148.
Van de Wiele, F., “A long-channel MOSFET model”, Solid-State Electron., 1979, 22, 991-987.
Huang, C. L., Arora, N., “Characterization and modeling of the n-and p-Channel MOSFETs inversion-layer mobility in the range 25-125 °C, Solid-State Electron., 1994, 37, 97-103.
Bendix, P., Rakers, P., Wagh, P., Lemaitre, L., Grabinski, W., McAndrew, C. C., Gu, X., Gildenblat, G., “RF distortion analysis with compact MOSFET models”, In Proc. IEEE CICC, 2004, 9-12.
Scharfetter; D. L., Gummel, H. K., “Large-signal analysis of a silicon read diode oscillator”, IEEE Trans. Electron Dev., 1969, 16, 64-77.
El-Mansy, Y. A., Boothroyd, A. R., “A simple two-dimensional model for IGFET operation in the saturation region”, IEEE Trans. Electron Dev., 1977, 24, 254-262.
Cao, K. M. et al., “Modeling of pocket implanted MOSFETs for anomalous analog behavior”, In IEDM Tech. Digest, 1999, 171-174.
Ward, D. E., Dutton, R. W., “A charge-oriented model for MOS transistor capacitances”, IEEE J. Solid-State Circ., 1978, 13, 703-708.
Foty, D. MOSFET Modeling with SPICE: Principles and Practice, Upper Saddle River, NJ: Prentice-hall, 1997.
Liu, W. MOSFET Models for SPICE Simulations Including BSIM3v3, BSIM4, New York: Wiley, 2001.
Victory, J., Yan, Z., Gildenblat, G., McAndrew, C., Zheng, J., “A physically based scalable varactor model and extractor methodology for RF applications”, IEEE Trans. Electron Dev., 2005, 52, 1343-1353.
Chen, J., Chan, T. Y., Ko, P. K., Hu, C., “Subbreakdown drain leakage current in MOSFET”, IEEE Electron Dev. Lett., 1987, 8, 515-517.
Kane, E. O., “Zener tunneling in semiconductors”, J. Phys. Chem. Solids, 1959, 12, 181-188.
JUNCAP level 1: www.semiconductors.philips.com/Philips_Models
Hurkx, G. A. M., de Graaff, H. C., Kloosterman, W. J., Knuvers, M. P. G., “A new analytical diode model including tunneling and avalanche breakdown”, IEEE Trans. Electron Dev., 1992, 39, 2090-2098.
Wright, P. J., Saraswat, K. C., “Thickness limitations of SiO2 gate dielectrics for MOS ULSI”, IEEE Trans. Electron Dev., 1990, 37, 1884-1892.
Choi, C. H., Nam, K. Y.;Yu, Z., Dutton, R. W., “Impact of gate direct tunneling current on circuit performance: A simulation study”, IEEE Trans. Electron Dev., 2001, 48, 2823-2829.
Tsu, R., Esaki, L., “Tunneling in a finite superlattice”, Appl. Phys. Lett., 1973, 22, 562-564.
Scholten, A. J., Tiemeijer, L. F., van Langevelde, R., Havens, R. J., Zegers-van Duijnhoven, A. T. A., Venezia, V. C., “Noise modeling for RF CMOS circuit simulation”, IEEE Trans. Electron Dev., 2003, 50, 618-632.
Hung, K. K., Ko, P. K., Hu, C., Cheng, Y. C., “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors”, IEEE Trans. Electron Dev., 1990, 37, 654-665.
Hung, K. K., Ko, P. K., Hu, C., Cheng, Y. C., “A physics-based MOSFET noise model for circuit simulators”, IEEE Trans. Electron Dev., 1990, 37, 1323-1333.
van der Ziel, A. Noise Solid-State Dev. Circuits, NewYork: Wiley-Interscience, 1986.
Klaassen, F. M., Prins, J., “Thermal noise of MOS transistors”, Philips Res. Reports, 1967, 22, 505-514.
Klaassen, F. M., “Comments on hot carrier noise in field-effect transistors”, IEEE Trans. Electron Dev., 1971, 18, 74-75.
Paasschens, J. C. J., Scholten, A. J., van Langevelde, R., “Generalisations of the Klaassen-Prins equation for calculating the noise of semiconductor Devices”, IEEE Trans. Electron Dev., 2005, 52, 2463-2472.
Scholten, A. J., Tiemeijer, L. F., de Vreede, P. W. H., Klaassen, D. B. M., “A large signal non-quasi-static MOS model for RF circuit simulation”, In IEDM Tech. Digest, 1999, 163-166.
Mancini, P., Turchetti, C., Masetti, G., “A non-quasi-static analysis of the transient behavior of the long-channel MOSFET valid in all regions of operation”, IEEE Trans. Electron Dev., 1987, ED-34, 325-334.
Hwang, S. W., Yoon, T. W., Kwon, D. H., Kim, K. H., “A physics-based SPICE-compatible non-quasi-static MOS transient model for RF circuit simulation”, Jpn. J. Appl. Phys., 1998, 37, L119-L121.
CMC-website: www.eigroup.org/cmc
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer
About this chapter
Cite this chapter
Langevelde, R., Gildenblat, G. (2006). PSP: An advanced surface-potential-based MOSFET model. In: GRABINSKI, W., NAUWELAERS, B., SCHREURS, D. (eds) TRANSISTOR LEVEL MODELING FOR ANALOG/RF IC DESIGN. Springer, Dordrecht. https://doi.org/10.1007/1-4020-4556-5_2
Download citation
DOI: https://doi.org/10.1007/1-4020-4556-5_2
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-4555-4
Online ISBN: 978-1-4020-4556-1
eBook Packages: EngineeringEngineering (R0)